From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from linux.microsoft.com (linux.microsoft.com []) by mx.groups.io with SMTP id smtpd.web12.6904.1621396818566077158 for ; Tue, 18 May 2021 21:00:20 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="body hash did not verify" header.i=@linux.microsoft.com header.s=default header.b=fNNYjyUz; spf=fail (domain: linux.microsoft.com, ip: , mailfrom: mikuback@linux.microsoft.com) Received: from localhost.localdomain (unknown [167.220.2.74]) by linux.microsoft.com (Postfix) with ESMTPSA id BA52F20B8008; Tue, 18 May 2021 21:00:19 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com BA52F20B8008 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1621396819; bh=wyYxGrIuokM+0xj5jc3XXkjTPn+eDPejv4DblgEYF9s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fNNYjyUzlcEhFjYlr4cuane+kF/HBTTaue2xlTARE7d991xq2T9iK6FxvTtBEr3z3 htNbXcfjcBZFAZ1XSKa9g0aAU78Ix6BePCurF7D1fPEG4gyFF4+zLfM0xtcjt3G4vM fou6Hx47+tbveEQxkWgKbjX162zQ1SCgJcHBMvwY= From: "Michael Kubacki" To: devel@edk2.groups.io Cc: Ray Ni , Rangasai V Chaganty Subject: [edk2-platforms][PATCH v2 06/35] IntelSiliconPkg: Add PCH SPI PPI Date: Tue, 18 May 2021 20:59:18 -0700 Message-Id: <20210519035947.1234-7-mikuback@linux.microsoft.com> X-Mailer: git-send-email 2.28.0.windows.1 In-Reply-To: <20210519035947.1234-1-mikuback@linux.microsoft.com> References: <20210519035947.1234-1-mikuback@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Kubacki REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3307 This SPI PPI definition is intended to serve as the single definition for Intel platform and silicon packages. Cc: Ray Ni Cc: Rangasai V Chaganty Signed-off-by: Michael Kubacki --- Silicon/Intel/IntelSiliconPkg/Include/Ppi/Spi.h | 25 +++++++++++++++++= +++ Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 3 +++ 2 files changed, 28 insertions(+) diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Ppi/Spi.h b/Silicon/In= tel/IntelSiliconPkg/Include/Ppi/Spi.h new file mode 100644 index 000000000000..b2410bd17300 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/Ppi/Spi.h @@ -0,0 +1,25 @@ +/** @file + This file defines the PCH SPI PPI which implements the + Intel(R) PCH SPI Host Controller Compatibility Interface. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_SPI_PPI_H_ +#define _PCH_SPI_PPI_H_ + +#include + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPchSpiPpiGuid; + +/** + Reuse the PCH_SPI_PROTOCOL definitions + This is possible becaues the PPI implementation does not rely on a Pei= Service pointer, + as it uses EDKII Glue Lib to do IO accesses +**/ +typedef PCH_SPI_PROTOCOL PCH_SPI_PPI; + +#endif diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/= Intel/IntelSiliconPkg/IntelSiliconPkg.dec index fb8391000347..70f030e3a295 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -71,6 +71,9 @@ [Guids] gEdkiiMicrocodeStorageTypeFlashGuid =3D { 0x2cba01b3, 0xd391, 0x4598, = { 0x8d, 0x89, 0xb7, 0xfc, 0x39, 0x22, 0xfd, 0x71 } } =20 [Ppis] + ## Include/Ppi/Spi.h + gPchSpiPpiGuid =3D {0xdade7ce3, 0x6971, 0x4b75, {0x82, 0x5e, 0xe, 0xe0= , 0xeb, 0x17, 0x72, 0x2d}} + gEdkiiVTdInfoPpiGuid =3D { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0= x67, 0xaf, 0x2b, 0x25, 0x68, 0x4a } } gEdkiiVTdNullRootEntryTableGuid =3D { 0x3de0593f, 0x6e3e, 0x4542, { 0x= a1, 0xcb, 0xcb, 0xb2, 0xdb, 0xeb, 0xd8, 0xff } } =20 --=20 2.28.0.windows.1