From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.8647.1621412577039820556 for ; Wed, 19 May 2021 01:22:57 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: pranav.madhu@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B2E7BED1; Wed, 19 May 2021 01:22:56 -0700 (PDT) Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 872FC3F73D; Wed, 19 May 2021 01:22:55 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar Subject: [edk2-platforms][PATCH V1 2/6] Platform/Sgi: ACPI PPTT table for RD-N2-Cfg1 platform Date: Wed, 19 May 2021 13:52:43 +0530 Message-Id: <20210519082247.3003-3-pranav.madhu@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210519082247.3003-1-pranav.madhu@arm.com> References: <20210519082247.3003-1-pranav.madhu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable The RD-N2-Cfg1 platform includes eight single-thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also includes a system level cache of 8MB. Add PPTT table for RD-N2-Cfg1 platform with this information. Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 1 + Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 166 ++++++++++++= ++++++++ 2 files changed, 167 insertions(+) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf b/Plat= form/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf index 8c8ce462c9d3..59e9dfceec76 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf @@ -22,6 +22,7 @@ Mcfg.aslc RdN2Cfg1/Dsdt.asl RdN2Cfg1/Madt.aslc + RdN2Cfg1/Pptt.aslc Spcr.aslc Ssdt.asl SsdtRos.asl diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc b/Platform= /ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc new file mode 100644 index 000000000000..5890544c0b92 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc @@ -0,0 +1,166 @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-N2-Cfg1 platform +* +* This file describes the topological structure of the processor block o= n the +* RD-N2-Cfg1 platform in the form as defined by ACPI PPTT table. The RD-= N2-Cfg1 +* platform includes eight single-thread CPUS. Each of the CPUs include 6= 4KB +* L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platfor= m also +* includes system level cache of 8MB. +* +* Copyright (c) 2021, ARM Limited. All rights reserved. +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology= Table +**/ + +#include +#include +#include +#include + +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" + +/** Define helper macro for populating processor core information. + + @param [in] PackageId Package instance number. + @param [in] ClusterId Cluster instance number. + @param [in] CpuId CPU instance number. +**/ +#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[ClusterId]), /* Parent */ = \ + ((PackageId << 4) | ClusterId), /* ACPI Id */ = \ + 2 /* Num of private resource *= / \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[ClusterId].Core[CpuId].DCache), = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[ClusterId].Core[CpuId].ICache) = \ + }, = \ + = \ + /* L1 data cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L1 instruction cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L2 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_1MB, /* Size */ = \ + 2048, /* Num of sets */ = \ + 8, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + } + +/** Define helper macro for populating processor container information. + + @param [in] PackageId Package instance number. + @param [in] ClusterId Cluster instance number. +**/ +#define PPTT_CLUSTER_INIT(PackageId, ClusterId) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package), /* Parent */ = \ + ((PackageId << 4) | ClusterId), /* ACPI Id */ = \ + 0 /* Num of private resource *= / \ + ), = \ + = \ + /* Initialize child core */ = \ + { = \ + PPTT_CORE_INIT (PackageId, ClusterId, 0) = \ + } = \ + } + +#pragma pack(1) +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RD_PPTT_SLC_PACKAGE Package; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU= RE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( + OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), + + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + Package.Slc), + + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ + 0, /* Next level of cache */ + SIZE_8MB, /* Size */ + 8192, /* Num of sets */ + 16, /* Associativity */ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ + 64 /* Line size */ + ), + + { + PPTT_CLUSTER_INIT (0, 0), + PPTT_CLUSTER_INIT (0, 1), + PPTT_CLUSTER_INIT (0, 2), + PPTT_CLUSTER_INIT (0, 3), + PPTT_CLUSTER_INIT (0, 4), + PPTT_CLUSTER_INIT (0, 5), + PPTT_CLUSTER_INIT (0, 6), + PPTT_CLUSTER_INIT (0, 7), + } + } +}; + +/* + * Reference the table being generated to prevent the optimizer from rem= oving + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; --=20 2.17.1