* [edk2-platforms][PATCH V1 1/6] Platform/Sgi: Add initial support for RD-N2-Cfg1 platform
2021-05-19 8:22 [edk2-platforms][PATCH V1 0/6] Platform/Sgi: Add initial support for RD-N2-Cfg1 platform Pranav Madhu
@ 2021-05-19 8:22 ` Pranav Madhu
2021-05-24 14:12 ` Sami Mujawar
2021-05-19 8:22 ` [edk2-platforms][PATCH V1 2/6] Platform/Sgi: ACPI PPTT table " Pranav Madhu
` (5 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Pranav Madhu @ 2021-05-19 8:22 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar
From: Aditya Angadi <aditya.angadi@arm.com>
Arm's RD-N2-Cfg1 platform is a variant of the RD-N2 platform. Compared
to RD-N2 platform, RD-N2-Cfg1 has a reduced core count of eight Neoverse
N2 CPUs and a smaller interconnect mesh. As part of the initial platform
support for RD-N2-Cfg1 platform, add the corresponding ACPI tables,
platform and flash description files.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc | 57 ++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 68 ++++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 110 ++++++++++++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc | 109 +++++++++++++++++++
Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc | 12 +++
5 files changed, 356 insertions(+)
diff --git a/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc b/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc
new file mode 100644
index 000000000000..0bd149bf56ab
--- /dev/null
+++ b/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc
@@ -0,0 +1,57 @@
+## @file
+# Platform Description file for RD-N2-Cfg1 platform.
+#
+# Copyright (c) 2017 - 2020, Arm Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = RdN2Cfg1
+ PLATFORM_GUID = aca676d8-3acb-43d0-9e05-95e1ce6bf5d3
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001B
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = AARCH64|ARM
+ BUILD_TARGETS = NOOPT|DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Platform/ARM/SgiPkg/SgiPlatform.fdf
+ BOARD_DXE_FV_COMPONENTS = Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc
+ BUILD_NUMBER = 1
+
+# include common definitions from SgiPlatform.dsc
+!include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+!include Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
+
+# include common/basic libraries from MdePkg.
+!include MdePkg/MdeLibs.dsc.inc
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+ # GIC Base Addresses
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x30100000
+ gArmSgiTokenSpaceGuid.PcdGicSize|0x200000
+
+ # ARM Cores and Clusters
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|1
+ gArmPlatformTokenSpaceGuid.PcdClusterCount|8
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+
+[Components.common]
+ Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
new file mode 100644
index 000000000000..8c8ce462c9d3
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
@@ -0,0 +1,68 @@
+## @file
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2021, Arm Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = RdN2Cfg1AcpiTables
+ FILE_GUID = c712719a-0aaf-438c-9cdd-35ab4d60207d # gArmSgiAcpiTablesGuid
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dbg2.aslc
+ Fadt.aslc
+ Gtdt.aslc
+ Iort.aslc
+ Mcfg.aslc
+ RdN2Cfg1/Dsdt.asl
+ RdN2Cfg1/Madt.aslc
+ Spcr.aslc
+ Ssdt.asl
+ SsdtRos.asl
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/SgiPkg/SgiPlatform.dec
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmPlatformTokenSpaceGuid.PcdClusterCount
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+ gArmTokenSpaceGuid.PcdPciBusMin
+ gArmTokenSpaceGuid.PcdPciBusMax
+
+ gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress
+ gArmSgiTokenSpaceGuid.PcdGpioController0Size
+ gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
+ gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
+ gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuBase
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkSize
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt
+ gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioNetSize
+ gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt
+ gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv
+ gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
new file mode 100644
index 000000000000..d68523bc43ed
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
@@ -0,0 +1,110 @@
+/** @file
+* Differentiated System Description Table (DSDT) for RD-N2-Cfg1 platform
+*
+* This file describes the peripheral devices, system hardware features and the
+* information about supported power events.
+*
+* Copyright (c) 2021, Arm Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.11.1, Differentiated System Description
+ Table (DSDT)
+**/
+
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+
+DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
+ EFI_ACPI_ARM_OEM_REVISION) {
+ Scope (_SB) {
+ Device (CL00) { // Cluster 0
+ Name (_HID, "ACPI0010")
+ Name (_UID, 0)
+
+ Device (CP00) { // Neoverse N2 core 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0)
+ Name (_STA, 0xF)
+ }
+ }
+
+ Device (CL01) { // Cluster 1
+ Name (_HID, "ACPI0010")
+ Name (_UID, 1)
+
+ Device (CP01) { // Neoverse N2 core 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 1)
+ Name (_STA, 0xF)
+ }
+ }
+
+ Device (CL02) { // Cluster 2
+ Name (_HID, "ACPI0010")
+ Name (_UID, 2)
+
+ Device (CP02) { // Neoverse N2 core 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 2)
+ Name (_STA, 0xF)
+ }
+ }
+
+ Device (CL03) { // Cluster 3
+ Name (_HID, "ACPI0010")
+ Name (_UID, 3)
+
+ Device (CP03) { // Neoverse N2 core 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 3)
+ Name (_STA, 0xF)
+ }
+ }
+
+ Device (CL04) { // Cluster 4
+ Name (_HID, "ACPI0010")
+ Name (_UID, 4)
+
+ Device (CP04) { // Neoverse N2 core 4
+ Name (_HID, "ACPI0007")
+ Name (_UID, 4)
+ Name (_STA, 0xF)
+ }
+ }
+
+ Device (CL05) { // Cluster 5
+ Name (_HID, "ACPI0010")
+ Name (_UID, 5)
+
+ Device (CP05) { // Neoverse N2 core 5
+ Name (_HID, "ACPI0007")
+ Name (_UID, 5)
+ Name (_STA, 0xF)
+ }
+ }
+
+ Device (CL06) { // Cluster 6
+ Name (_HID, "ACPI0010")
+ Name (_UID, 6)
+
+ Device (CP06) { // Neoverse N2 core 6
+ Name (_HID, "ACPI0007")
+ Name (_UID, 6)
+ Name (_STA, 0xF)
+ }
+ }
+
+ Device (CL07) { // Cluster 7
+ Name (_HID, "ACPI0010")
+ Name (_UID, 7)
+
+ Device (CP07) { // Neoverse N2 core 7
+ Name (_HID, "ACPI0007")
+ Name (_UID, 7)
+ Name (_STA, 0xF)
+ }
+ }
+ } // Scope(_SB)
+}
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
new file mode 100644
index 000000000000..e28f6e41d10d
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
@@ -0,0 +1,109 @@
+/** @file
+* Multiple APIC Description Table (MADT) for RD-N2-Cfg1 platform
+*
+* This file lists all the processors available on the platform that the OSPM
+* can enumerate and boot. It also lists all the interrupt controllers available
+* in the system.
+*
+* Copyright (c) 2021, Arm Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.12, Multiple APIC Description Table
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+
+#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
+ FixedPcdGet32 (PcdCoreCount))
+
+// Multiple APIC Description Table
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts[3];
+} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ ),
+ // MADT specific fields
+ 0, // LocalApicAddress
+ 0 // Flags
+ },
+ {
+ // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+ // PmuIrq, GicBase, GicVBase,
+ // GicHBase, GsivId, GicRBase,
+ // Efficiency)
+ // Note: The GIC Structure of the primary CPU must be the first entry
+ // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core2
+ 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core3
+ 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core4
+ 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core5
+ 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core6
+ 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core7
+ 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ },
+ // GIC Distributor Entry
+ EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
+ 0, 3),
+ // GIC Redistributor
+ EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
+ SIZE_16MB),
+ // GIC ITS
+ {
+ EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000),
+ EFI_ACPI_6_2_GIC_ITS_INIT(1, 0x30080000),
+ EFI_ACPI_6_2_GIC_ITS_INIT(2, 0x300C0000),
+ },
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing
+// the data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc b/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc
new file mode 100644
index 000000000000..ef0c02afb4f4
--- /dev/null
+++ b/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc
@@ -0,0 +1,12 @@
+## @file
+# Flash Description include file for RD-N2-Cfg1 platform.
+#
+# Copyright (c) 2021, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+# Per-platform additional content of the DXE phase firmware volume
+
+ # ACPI support
+ INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [edk2-platforms][PATCH V1 1/6] Platform/Sgi: Add initial support for RD-N2-Cfg1 platform
2021-05-19 8:22 ` [edk2-platforms][PATCH V1 1/6] " Pranav Madhu
@ 2021-05-24 14:12 ` Sami Mujawar
0 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-05-24 14:12 UTC (permalink / raw)
To: Pranav Madhu, devel; +Cc: Ard Biesheuvel, nd
Hi Pranav,
Please see my response inline marked [SAMI].
Regards,
Sami Mujawar
On 19/05/2021 09:22 AM, Pranav Madhu wrote:
> From: Aditya Angadi <aditya.angadi@arm.com>
>
> Arm's RD-N2-Cfg1 platform is a variant of the RD-N2 platform. Compared
> to RD-N2 platform, RD-N2-Cfg1 has a reduced core count of eight Neoverse
> N2 CPUs and a smaller interconnect mesh. As part of the initial platform
> support for RD-N2-Cfg1 platform, add the corresponding ACPI tables,
> platform and flash description files.
>
> Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
> ---
> Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc | 57 ++++++++++
> Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 68 ++++++++++++
> Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 110 ++++++++++++++++++++
> Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc | 109 +++++++++++++++++++
> Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc | 12 +++
> 5 files changed, 356 insertions(+)
>
> diff --git a/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc b/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc
> new file mode 100644
> index 000000000000..0bd149bf56ab
> --- /dev/null
> +++ b/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc
> @@ -0,0 +1,57 @@
> +## @file
> +# Platform Description file for RD-N2-Cfg1 platform.
> +#
> +# Copyright (c) 2017 - 2020, Arm Limited. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +##
> +
> +################################################################################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################################
> +[Defines]
> + PLATFORM_NAME = RdN2Cfg1
> + PLATFORM_GUID = aca676d8-3acb-43d0-9e05-95e1ce6bf5d3
> + PLATFORM_VERSION = 0.1
> + DSC_SPECIFICATION = 0x0001001B
> + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
> + SUPPORTED_ARCHITECTURES = AARCH64|ARM
[SAMI] Is AARCH32 supported? The build appears to fail for both AARCH32
and AARCH64. Can you check, please?
[/SAMI]
> + BUILD_TARGETS = NOOPT|DEBUG|RELEASE
> + SKUID_IDENTIFIER = DEFAULT
> + FLASH_DEFINITION = Platform/ARM/SgiPkg/SgiPlatform.fdf
> + BOARD_DXE_FV_COMPONENTS = Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc
> + BUILD_NUMBER = 1
> +
> +# include common definitions from SgiPlatform.dsc
> +!include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
> +!include Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
> +
> +# include common/basic libraries from MdePkg.
> +!include MdePkg/MdeLibs.dsc.inc
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +
> +[PcdsFixedAtBuild.common]
> + # GIC Base Addresses
> + gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
> + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x30100000
> + gArmSgiTokenSpaceGuid.PcdGicSize|0x200000
> +
> + # ARM Cores and Clusters
> + gArmPlatformTokenSpaceGuid.PcdCoreCount|1
> + gArmPlatformTokenSpaceGuid.PcdClusterCount|8
> +
> +################################################################################
> +#
> +# Components Section - list of all EDK II Modules needed by this Platform
> +#
> +################################################################################
> +
> +[Components.common]
> + Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
> new file mode 100644
> index 000000000000..8c8ce462c9d3
> --- /dev/null
> +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
> @@ -0,0 +1,68 @@
> +## @file
> +# ACPI table data and ASL sources required to boot the platform.
> +#
> +# Copyright (c) 2021, Arm Ltd. All rights reserved.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = RdN2Cfg1AcpiTables
> + FILE_GUID = c712719a-0aaf-438c-9cdd-35ab4d60207d # gArmSgiAcpiTablesGuid
> + MODULE_TYPE = USER_DEFINED
> + VERSION_STRING = 1.0
> +
> +[Sources]
> + Dbg2.aslc
> + Fadt.aslc
> + Gtdt.aslc
> + Iort.aslc
> + Mcfg.aslc
> + RdN2Cfg1/Dsdt.asl
> + RdN2Cfg1/Madt.aslc
> + Spcr.aslc
> + Ssdt.asl
> + SsdtRos.asl
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> + Platform/ARM/SgiPkg/SgiPlatform.dec
> +
> +[FixedPcd]
> + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
> + gArmPlatformTokenSpaceGuid.PcdCoreCount
> + gArmPlatformTokenSpaceGuid.PcdClusterCount
> + gArmPlatformTokenSpaceGuid.PL011UartInterrupt
> +
> + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
> + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
> + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
> + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
> + gArmTokenSpaceGuid.PcdGicDistributorBase
> + gArmTokenSpaceGuid.PcdGicRedistributorsBase
> + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
> + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
> + gArmTokenSpaceGuid.PcdPciBusMin
> + gArmTokenSpaceGuid.PcdPciBusMax
> +
> + gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress
> + gArmSgiTokenSpaceGuid.PcdGpioController0Size
> + gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
[SAMI] PcdGpioControllerxxx does not appear to be used anywhere. Can you
check, please?
[/SAMI]
> + gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
> + gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
> + gArmSgiTokenSpaceGuid.PcdSmmuBase
> + gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
> + gArmSgiTokenSpaceGuid.PcdVirtioBlkSize
> + gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt
> + gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress
> + gArmSgiTokenSpaceGuid.PcdVirtioNetSize
> + gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt
> + gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv
> + gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv
> +
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
> new file mode 100644
> index 000000000000..d68523bc43ed
> --- /dev/null
> +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
> @@ -0,0 +1,110 @@
> +/** @file
> +* Differentiated System Description Table (DSDT) for RD-N2-Cfg1 platform
> +*
> +* This file describes the peripheral devices, system hardware features and the
> +* information about supported power events.
> +*
> +* Copyright (c) 2021, Arm Ltd. All rights reserved.
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +* @par Specification Reference:
> +* - ACPI 6.3, Chapter 5, Section 5.2.11.1, Differentiated System Description
> + Table (DSDT)
> +**/
> +
> +#include "SgiAcpiHeader.h"
> +#include "SgiPlatform.h"
> +
> +DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
> + EFI_ACPI_ARM_OEM_REVISION) {
> + Scope (_SB) {
> + Device (CL00) { // Cluster 0
> + Name (_HID, "ACPI0010")
> + Name (_UID, 0)
> +
> + Device (CP00) { // Neoverse N2 core 0
> + Name (_HID, "ACPI0007")
> + Name (_UID, 0)
> + Name (_STA, 0xF)
> + }
> + }
> +
> + Device (CL01) { // Cluster 1
> + Name (_HID, "ACPI0010")
> + Name (_UID, 1)
> +
> + Device (CP01) { // Neoverse N2 core 1
> + Name (_HID, "ACPI0007")
> + Name (_UID, 1)
> + Name (_STA, 0xF)
> + }
> + }
> +
> + Device (CL02) { // Cluster 2
> + Name (_HID, "ACPI0010")
> + Name (_UID, 2)
> +
> + Device (CP02) { // Neoverse N2 core 2
> + Name (_HID, "ACPI0007")
> + Name (_UID, 2)
> + Name (_STA, 0xF)
> + }
> + }
> +
> + Device (CL03) { // Cluster 3
> + Name (_HID, "ACPI0010")
> + Name (_UID, 3)
> +
> + Device (CP03) { // Neoverse N2 core 3
> + Name (_HID, "ACPI0007")
> + Name (_UID, 3)
> + Name (_STA, 0xF)
> + }
> + }
> +
> + Device (CL04) { // Cluster 4
> + Name (_HID, "ACPI0010")
> + Name (_UID, 4)
> +
> + Device (CP04) { // Neoverse N2 core 4
> + Name (_HID, "ACPI0007")
> + Name (_UID, 4)
> + Name (_STA, 0xF)
> + }
> + }
> +
> + Device (CL05) { // Cluster 5
> + Name (_HID, "ACPI0010")
> + Name (_UID, 5)
> +
> + Device (CP05) { // Neoverse N2 core 5
> + Name (_HID, "ACPI0007")
> + Name (_UID, 5)
> + Name (_STA, 0xF)
> + }
> + }
> +
> + Device (CL06) { // Cluster 6
> + Name (_HID, "ACPI0010")
> + Name (_UID, 6)
> +
> + Device (CP06) { // Neoverse N2 core 6
> + Name (_HID, "ACPI0007")
> + Name (_UID, 6)
> + Name (_STA, 0xF)
> + }
> + }
> +
> + Device (CL07) { // Cluster 7
> + Name (_HID, "ACPI0010")
> + Name (_UID, 7)
> +
> + Device (CP07) { // Neoverse N2 core 7
> + Name (_HID, "ACPI0007")
> + Name (_UID, 7)
> + Name (_STA, 0xF)
> + }
> + }
> + } // Scope(_SB)
> +}
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
> new file mode 100644
> index 000000000000..e28f6e41d10d
> --- /dev/null
> +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
> @@ -0,0 +1,109 @@
> +/** @file
> +* Multiple APIC Description Table (MADT) for RD-N2-Cfg1 platform
> +*
> +* This file lists all the processors available on the platform that the OSPM
> +* can enumerate and boot. It also lists all the interrupt controllers available
> +* in the system.
> +*
> +* Copyright (c) 2021, Arm Ltd. All rights reserved.
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +* @par Specification Reference:
> +* - ACPI 6.3, Chapter 5, Section 5.2.12, Multiple APIC Description Table
> +**/
> +
> +#include <Library/AcpiLib.h>
> +#include <Library/ArmLib.h>
> +#include <Library/PcdLib.h>
> +#include <IndustryStandard/Acpi.h>
> +
> +#include "SgiAcpiHeader.h"
> +#include "SgiPlatform.h"
> +
> +#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
> + FixedPcdGet32 (PcdCoreCount))
> +
> +// Multiple APIC Description Table
> +#pragma pack (1)
> +
> +typedef struct {
> + EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
> + EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT];
> + EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
> + EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
> + EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts[3];
> +} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
> +
> +#pragma pack ()
> +
> +STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
> + {
> + ARM_ACPI_HEADER (
> + EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
> + EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
> + EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
> + ),
> + // MADT specific fields
> + 0, // LocalApicAddress
> + 0 // Flags
> + },
> + {
> + // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
> + // PmuIrq, GicBase, GicVBase,
> + // GicHBase, GsivId, GicRBase,
> + // Efficiency)
> + // Note: The GIC Structure of the primary CPU must be the first entry
> + // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
> + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core0
> + 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
> + FixedPcdGet32 (PcdGicDistributorBase),
[SAMI] This should be the address of the GIC CPU Interface. The same PCD
is used to populate the base address of the GICD. Is something wrong here?
I see that this has been done for the other platforms in SgiPkg. Can you
check, please?
[/SAMI]
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core1
> + 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
> + FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core2
> + 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
> + FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core3
> + 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
> + FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core4
> + 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
> + FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core5
> + 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
> + FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core6
> + 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
> + FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core7
> + 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
> + FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + },
> + // GIC Distributor Entry
> + EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
> + 0, 3),
> + // GIC Redistributor
> + EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
> + SIZE_16MB),
> + // GIC ITS
> + {
> + EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000),
> + EFI_ACPI_6_2_GIC_ITS_INIT(1, 0x30080000),
> + EFI_ACPI_6_2_GIC_ITS_INIT(2, 0x300C0000),
> + },
> +};
> +
> +//
> +// Reference the table being generated to prevent the optimizer from removing
> +// the data structure from the executable
> +//
> +VOID* CONST ReferenceAcpiTable = &Madt;
> diff --git a/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc b/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc
> new file mode 100644
> index 000000000000..ef0c02afb4f4
> --- /dev/null
> +++ b/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc
> @@ -0,0 +1,12 @@
> +## @file
> +# Flash Description include file for RD-N2-Cfg1 platform.
> +#
> +# Copyright (c) 2021, Arm Limited. All rights reserved.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +##
> +
> +# Per-platform additional content of the DXE phase firmware volume
> +
> + # ACPI support
> + INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
^ permalink raw reply [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V1 2/6] Platform/Sgi: ACPI PPTT table for RD-N2-Cfg1 platform
2021-05-19 8:22 [edk2-platforms][PATCH V1 0/6] Platform/Sgi: Add initial support for RD-N2-Cfg1 platform Pranav Madhu
2021-05-19 8:22 ` [edk2-platforms][PATCH V1 1/6] " Pranav Madhu
@ 2021-05-19 8:22 ` Pranav Madhu
2021-05-24 14:13 ` Sami Mujawar
2021-05-19 8:22 ` [edk2-platforms][PATCH V1 3/6] Platform/Sgi: Low Power Idle states for RD-N2-Cfg1 Pranav Madhu
` (4 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Pranav Madhu @ 2021-05-19 8:22 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar
The RD-N2-Cfg1 platform includes eight single-thread CPUS. Each of the
CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2
cache. The platform also includes a system level cache of 8MB. Add PPTT
table for RD-N2-Cfg1 platform with this information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 1 +
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 166 ++++++++++++++++++++
2 files changed, 167 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
index 8c8ce462c9d3..59e9dfceec76 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
@@ -22,6 +22,7 @@
Mcfg.aslc
RdN2Cfg1/Dsdt.asl
RdN2Cfg1/Madt.aslc
+ RdN2Cfg1/Pptt.aslc
Spcr.aslc
Ssdt.asl
SsdtRos.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc
new file mode 100644
index 000000000000..5890544c0b92
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc
@@ -0,0 +1,166 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-N2-Cfg1 platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-N2-Cfg1 platform in the form as defined by ACPI PPTT table. The RD-N2-Cfg1
+* platform includes eight single-thread CPUS. Each of the CPUs include 64KB
+* L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also
+* includes system level cache of 8MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+
+/** Define helper macro for populating processor core information.
+
+ @param [in] PackageId Package instance number.
+ @param [in] ClusterId Cluster instance number.
+ @param [in] CpuId CPU instance number.
+**/
+#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId]), /* Parent */ \
+ ((PackageId << 4) | ClusterId), /* ACPI Id */ \
+ 2 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].DCache), \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].ICache) \
+ }, \
+ \
+ /* L1 data cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 instruction cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_1MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 8, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ }
+
+/** Define helper macro for populating processor container information.
+
+ @param [in] PackageId Package instance number.
+ @param [in] ClusterId Cluster instance number.
+**/
+#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package), /* Parent */ \
+ ((PackageId << 4) | ClusterId), /* ACPI Id */ \
+ 0 /* Num of private resource */ \
+ ), \
+ \
+ /* Initialize child core */ \
+ { \
+ PPTT_CORE_INIT (PackageId, ClusterId, 0) \
+ } \
+ }
+
+#pragma pack(1)
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RD_PPTT_SLC_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc),
+ PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1),
+
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ Package.Slc),
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
+ 0, /* Next level of cache */
+ SIZE_8MB, /* Size */
+ 8192, /* Num of sets */
+ 16, /* Associativity */
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
+ 64 /* Line size */
+ ),
+
+ {
+ PPTT_CLUSTER_INIT (0, 0),
+ PPTT_CLUSTER_INIT (0, 1),
+ PPTT_CLUSTER_INIT (0, 2),
+ PPTT_CLUSTER_INIT (0, 3),
+ PPTT_CLUSTER_INIT (0, 4),
+ PPTT_CLUSTER_INIT (0, 5),
+ PPTT_CLUSTER_INIT (0, 6),
+ PPTT_CLUSTER_INIT (0, 7),
+ }
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [edk2-platforms][PATCH V1 2/6] Platform/Sgi: ACPI PPTT table for RD-N2-Cfg1 platform
2021-05-19 8:22 ` [edk2-platforms][PATCH V1 2/6] Platform/Sgi: ACPI PPTT table " Pranav Madhu
@ 2021-05-24 14:13 ` Sami Mujawar
0 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-05-24 14:13 UTC (permalink / raw)
To: Pranav Madhu, devel; +Cc: Ard Biesheuvel, nd
Hi Pranav,
This patch looks good to me.
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Regards,
Sami Mujawar
On 19/05/2021 09:22 AM, Pranav Madhu wrote:
> The RD-N2-Cfg1 platform includes eight single-thread CPUS. Each of the
> CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2
> cache. The platform also includes a system level cache of 8MB. Add PPTT
> table for RD-N2-Cfg1 platform with this information.
>
> Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
> ---
> Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 1 +
> Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 166 ++++++++++++++++++++
> 2 files changed, 167 insertions(+)
>
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
> index 8c8ce462c9d3..59e9dfceec76 100644
> --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
> +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
> @@ -22,6 +22,7 @@
> Mcfg.aslc
> RdN2Cfg1/Dsdt.asl
> RdN2Cfg1/Madt.aslc
> + RdN2Cfg1/Pptt.aslc
> Spcr.aslc
> Ssdt.asl
> SsdtRos.asl
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc
> new file mode 100644
> index 000000000000..5890544c0b92
> --- /dev/null
> +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc
> @@ -0,0 +1,166 @@
> +/** @file
> +* Processor Properties Topology Table (PPTT) for RD-N2-Cfg1 platform
> +*
> +* This file describes the topological structure of the processor block on the
> +* RD-N2-Cfg1 platform in the form as defined by ACPI PPTT table. The RD-N2-Cfg1
> +* platform includes eight single-thread CPUS. Each of the CPUs include 64KB
> +* L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also
> +* includes system level cache of 8MB.
> +*
> +* Copyright (c) 2021, ARM Limited. All rights reserved.
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +* @par Specification Reference:
> +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
> +**/
> +
> +#include <IndustryStandard/Acpi.h>
> +#include <Library/AcpiLib.h>
> +#include <Library/ArmLib.h>
> +#include <Library/PcdLib.h>
> +
> +#include "SgiAcpiHeader.h"
> +#include "SgiPlatform.h"
> +
> +/** Define helper macro for populating processor core information.
> +
> + @param [in] PackageId Package instance number.
> + @param [in] ClusterId Cluster instance number.
> + @param [in] CpuId CPU instance number.
> +**/
> +#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
> + { \
> + /* Parameters for CPU Core */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
> + OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
> + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[ClusterId]), /* Parent */ \
> + ((PackageId << 4) | ClusterId), /* ACPI Id */ \
> + 2 /* Num of private resource */ \
> + ), \
> + \
> + /* Offsets of the private resources */ \
> + { \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[ClusterId].Core[CpuId].DCache), \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[ClusterId].Core[CpuId].ICache) \
> + }, \
> + \
> + /* L1 data cache parameters */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
> + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
> + /* Next level of cache */ \
> + SIZE_64KB, /* Size */ \
> + 256, /* Num of sets */ \
> + 4, /* Associativity */ \
> + PPTT_DATA_CACHE_ATTR, /* Attributes */ \
> + 64 /* Line size */ \
> + ), \
> + \
> + /* L1 instruction cache parameters */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
> + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
> + /* Next level of cache */ \
> + SIZE_64KB, /* Size */ \
> + 256, /* Num of sets */ \
> + 4, /* Associativity */ \
> + PPTT_INST_CACHE_ATTR, /* Attributes */ \
> + 64 /* Line size */ \
> + ), \
> + \
> + /* L2 cache parameters */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
> + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
> + 0, /* Next level of cache */ \
> + SIZE_1MB, /* Size */ \
> + 2048, /* Num of sets */ \
> + 8, /* Associativity */ \
> + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
> + 64 /* Line size */ \
> + ), \
> + }
> +
> +/** Define helper macro for populating processor container information.
> +
> + @param [in] PackageId Package instance number.
> + @param [in] ClusterId Cluster instance number.
> +**/
> +#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
> + { \
> + /* Parameters for Cluster */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
> + OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \
> + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package), /* Parent */ \
> + ((PackageId << 4) | ClusterId), /* ACPI Id */ \
> + 0 /* Num of private resource */ \
> + ), \
> + \
> + /* Initialize child core */ \
> + { \
> + PPTT_CORE_INIT (PackageId, ClusterId, 0) \
> + } \
> + }
> +
> +#pragma pack(1)
> +/*
> + * Processor Properties Topology Table
> + */
> +typedef struct {
> + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
> + RD_PPTT_SLC_PACKAGE Package;
> +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
> +#pragma pack ()
> +
> +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
> + {
> + ARM_ACPI_HEADER (
> + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
> + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
> + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
> + )
> + },
> +
> + {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
> + OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc),
> + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1),
> +
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
> + Package.Slc),
> +
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
> + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
> + 0, /* Next level of cache */
> + SIZE_8MB, /* Size */
> + 8192, /* Num of sets */
> + 16, /* Associativity */
> + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
> + 64 /* Line size */
> + ),
> +
> + {
> + PPTT_CLUSTER_INIT (0, 0),
> + PPTT_CLUSTER_INIT (0, 1),
> + PPTT_CLUSTER_INIT (0, 2),
> + PPTT_CLUSTER_INIT (0, 3),
> + PPTT_CLUSTER_INIT (0, 4),
> + PPTT_CLUSTER_INIT (0, 5),
> + PPTT_CLUSTER_INIT (0, 6),
> + PPTT_CLUSTER_INIT (0, 7),
> + }
> + }
> +};
> +
> +/*
> + * Reference the table being generated to prevent the optimizer from removing
> + * the data structure from the executable
> + */
> +VOID* CONST ReferenceAcpiTable = &Pptt;
^ permalink raw reply [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V1 3/6] Platform/Sgi: Low Power Idle states for RD-N2-Cfg1
2021-05-19 8:22 [edk2-platforms][PATCH V1 0/6] Platform/Sgi: Add initial support for RD-N2-Cfg1 platform Pranav Madhu
2021-05-19 8:22 ` [edk2-platforms][PATCH V1 1/6] " Pranav Madhu
2021-05-19 8:22 ` [edk2-platforms][PATCH V1 2/6] Platform/Sgi: ACPI PPTT table " Pranav Madhu
@ 2021-05-19 8:22 ` Pranav Madhu
2021-05-24 14:13 ` Sami Mujawar
2021-05-19 8:22 ` [edk2-platforms][PATCH V1 4/6] Platform/Sgi: ACPI CPPC support " Pranav Madhu
` (3 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Pranav Madhu @ 2021-05-19 8:22 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar
RD-N2-Cfg1 platform supports 2 LPI states, LPI1 (Standby WFI) and LPI3
(Power-down) and the cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 158 ++++++++++++++++++++
1 file changed, 158 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
index d68523bc43ed..55f51cc26aff 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
@@ -19,91 +19,249 @@
DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
EFI_ACPI_ARM_OEM_REVISION) {
Scope (_SB) {
+ /* _OSC: Operating System Capabilities */
+ Method (_OSC, 4, Serialized) {
+ CreateDWordField (Arg3, 0x00, STS0)
+ CreateDWordField (Arg3, 0x04, CAP0)
+
+ /* Platform-wide Capabilities */
+ If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+ /* OSC rev 1 supported, for other version, return failure */
+ If (LEqual (Arg1, One)) {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+
+ If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+ /* OS initiated LPI not supported */
+ And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+ Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+ }
+ } Else {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+ Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
+ }
+ } Else {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+ Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
+ }
+
+ Return (Arg3)
+ }
+
+ Name (CLPI, Package () { /* LPI for Cluster, support 1 LPI state */
+ 0, // Version
+ 0, // Level Index
+ 1, // Count
+ Package () { // Power Gating state for Cluster
+ 2500, // Min residency (uS)
+ 1150, // Wake latency (uS)
+ 1, // Flags
+ 1, // Arch Context Flags
+ 100, // Residency Counter Frequency
+ 0, // No Parent State
+ 0x00000020, // Integer Entry method
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI2-Cluster"
+ },
+ })
+
+ Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
+ 0, // Version
+ 1, // Level Index
+ 2, // Count
+ Package () { // WFI for CPU
+ 1, // Min residency (uS)
+ 1, // Wake latency (uS)
+ 1, // Flags
+ 0, // Arch Context lost Flags (no loss)
+ 100, // Residency Counter Frequency
+ 0, // No parent state
+ ResourceTemplate () { // Register Entry method
+ Register (FFixedHW,
+ 32, // Bit Width
+ 0, // Bit Offset
+ 0xFFFFFFFF, // Address
+ 3, // Access Size
+ )
+ },
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI1-Core"
+ },
+ Package () { // Power Gating state for CPU
+ 150, // Min residency (uS)
+ 350, // Wake latency (uS)
+ 1, // Flags
+ 1, // Arch Context lost Flags (Core context lost)
+ 100, // Residency Counter Frequency
+ 1, // Parent node can be in any shallower state
+ ResourceTemplate () { // Register Entry method
+ Register (FFixedHW,
+ 32, // Bit Width
+ 0, // Bit Offset
+ 0x40000002, // Address (PwrLvl:core, StateTyp:PwrDn)
+ 3, // Access Size
+ )
+ },
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI3-Core"
+ },
+ })
+
Device (CL00) { // Cluster 0
Name (_HID, "ACPI0010")
Name (_UID, 0)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP00) { // Neoverse N2 core 0
Name (_HID, "ACPI0007")
Name (_UID, 0)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL01) { // Cluster 1
Name (_HID, "ACPI0010")
Name (_UID, 1)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP01) { // Neoverse N2 core 1
Name (_HID, "ACPI0007")
Name (_UID, 1)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL02) { // Cluster 2
Name (_HID, "ACPI0010")
Name (_UID, 2)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP02) { // Neoverse N2 core 2
Name (_HID, "ACPI0007")
Name (_UID, 2)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL03) { // Cluster 3
Name (_HID, "ACPI0010")
Name (_UID, 3)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP03) { // Neoverse N2 core 3
Name (_HID, "ACPI0007")
Name (_UID, 3)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL04) { // Cluster 4
Name (_HID, "ACPI0010")
Name (_UID, 4)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP04) { // Neoverse N2 core 4
Name (_HID, "ACPI0007")
Name (_UID, 4)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL05) { // Cluster 5
Name (_HID, "ACPI0010")
Name (_UID, 5)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP05) { // Neoverse N2 core 5
Name (_HID, "ACPI0007")
Name (_UID, 5)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL06) { // Cluster 6
Name (_HID, "ACPI0010")
Name (_UID, 6)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP06) { // Neoverse N2 core 6
Name (_HID, "ACPI0007")
Name (_UID, 6)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL07) { // Cluster 7
Name (_HID, "ACPI0010")
Name (_UID, 7)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP07) { // Neoverse N2 core 7
Name (_HID, "ACPI0007")
Name (_UID, 7)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
} // Scope(_SB)
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [edk2-platforms][PATCH V1 3/6] Platform/Sgi: Low Power Idle states for RD-N2-Cfg1
2021-05-19 8:22 ` [edk2-platforms][PATCH V1 3/6] Platform/Sgi: Low Power Idle states for RD-N2-Cfg1 Pranav Madhu
@ 2021-05-24 14:13 ` Sami Mujawar
0 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-05-24 14:13 UTC (permalink / raw)
To: Pranav Madhu, devel; +Cc: Ard Biesheuvel, nd
[-- Attachment #1: Type: text/plain, Size: 8846 bytes --]
Hi Pranav,
This patch looks good to me.
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Regards,
Sami Mujawar
On 19/05/2021 09:22 AM, Pranav Madhu wrote:
> RD-N2-Cfg1 platform supports 2 LPI states, LPI1 (Standby WFI) and LPI3
> (Power-down) and the cluster supports LPI2 (Power-down) state. The LPI
> implementation also supports combined power state for core and cluster.
>
> Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
> ---
> Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 158 ++++++++++++++++++++
> 1 file changed, 158 insertions(+)
>
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
> index d68523bc43ed..55f51cc26aff 100644
> --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
> +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
> @@ -19,91 +19,249 @@
> DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
> EFI_ACPI_ARM_OEM_REVISION) {
> Scope (_SB) {
> + /* _OSC: Operating System Capabilities */
> + Method (_OSC, 4, Serialized) {
> + CreateDWordField (Arg3, 0x00, STS0)
> + CreateDWordField (Arg3, 0x04, CAP0)
> +
> + /* Platform-wide Capabilities */
> + If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
> + /* OSC rev 1 supported, for other version, return failure */
> + If (LEqual (Arg1, One)) {
> + And (STS0, Not (OSC_STS_MASK), STS0)
> +
> + If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
> + /* OS initiated LPI not supported */
> + And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
> + Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
> + }
> + } Else {
> + And (STS0, Not (OSC_STS_MASK), STS0)
> + Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
> + }
> + } Else {
> + And (STS0, Not (OSC_STS_MASK), STS0)
> + Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
> + }
> +
> + Return (Arg3)
> + }
> +
> + Name (CLPI, Package () { /* LPI for Cluster, support 1 LPI state */
> + 0, // Version
> + 0, // Level Index
> + 1, // Count
> + Package () { // Power Gating state for Cluster
> + 2500, // Min residency (uS)
> + 1150, // Wake latency (uS)
> + 1, // Flags
> + 1, // Arch Context Flags
> + 100, // Residency Counter Frequency
> + 0, // No Parent State
> + 0x00000020, // Integer Entry method
> + ResourceTemplate () { // Null Residency Counter
> + Register (SystemMemory, 0, 0, 0, 0)
> + },
> + ResourceTemplate () { // Null Usage Counter
> + Register (SystemMemory, 0, 0, 0, 0)
> + },
> + "LPI2-Cluster"
> + },
> + })
> +
> + Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
> + 0, // Version
> + 1, // Level Index
> + 2, // Count
> + Package () { // WFI for CPU
> + 1, // Min residency (uS)
> + 1, // Wake latency (uS)
> + 1, // Flags
> + 0, // Arch Context lost Flags (no loss)
> + 100, // Residency Counter Frequency
> + 0, // No parent state
> + ResourceTemplate () { // Register Entry method
> + Register (FFixedHW,
> + 32, // Bit Width
> + 0, // Bit Offset
> + 0xFFFFFFFF, // Address
> + 3, // Access Size
> + )
> + },
> + ResourceTemplate () { // Null Residency Counter
> + Register (SystemMemory, 0, 0, 0, 0)
> + },
> + ResourceTemplate () { // Null Usage Counter
> + Register (SystemMemory, 0, 0, 0, 0)
> + },
> + "LPI1-Core"
> + },
> + Package () { // Power Gating state for CPU
> + 150, // Min residency (uS)
> + 350, // Wake latency (uS)
> + 1, // Flags
> + 1, // Arch Context lost Flags (Core context lost)
> + 100, // Residency Counter Frequency
> + 1, // Parent node can be in any shallower state
> + ResourceTemplate () { // Register Entry method
> + Register (FFixedHW,
> + 32, // Bit Width
> + 0, // Bit Offset
> + 0x40000002, // Address (PwrLvl:core, StateTyp:PwrDn)
> + 3, // Access Size
> + )
> + },
> + ResourceTemplate () { // Null Residency Counter
> + Register (SystemMemory, 0, 0, 0, 0)
> + },
> + ResourceTemplate () { // Null Usage Counter
> + Register (SystemMemory, 0, 0, 0, 0)
> + },
> + "LPI3-Core"
> + },
> + })
> +
> Device (CL00) { // Cluster 0
> Name (_HID, "ACPI0010")
> Name (_UID, 0)
> + Method (_LPI, 0, NotSerialized) {
> + Return (\_SB.CLPI)
> + }
>
> Device (CP00) { // Neoverse N2 core 0
> Name (_HID, "ACPI0007")
> Name (_UID, 0)
> Name (_STA, 0xF)
> +
> + Method (_LPI, 0, NotSerialized) {
> + Return (\_SB.PLPI)
> + }
> }
> }
>
> Device (CL01) { // Cluster 1
> Name (_HID, "ACPI0010")
> Name (_UID, 1)
> + Method (_LPI, 0, NotSerialized) {
> + Return (\_SB.CLPI)
> + }
>
> Device (CP01) { // Neoverse N2 core 1
> Name (_HID, "ACPI0007")
> Name (_UID, 1)
> Name (_STA, 0xF)
> +
> + Method (_LPI, 0, NotSerialized) {
> + Return (\_SB.PLPI)
> + }
> }
> }
>
> Device (CL02) { // Cluster 2
> Name (_HID, "ACPI0010")
> Name (_UID, 2)
> + Method (_LPI, 0, NotSerialized) {
> + Return (\_SB.CLPI)
> + }
>
> Device (CP02) { // Neoverse N2 core 2
> Name (_HID, "ACPI0007")
> Name (_UID, 2)
> Name (_STA, 0xF)
> +
> + Method (_LPI, 0, NotSerialized) {
> + Return (\_SB.PLPI)
> + }
> }
> }
>
> Device (CL03) { // Cluster 3
> Name (_HID, "ACPI0010")
> Name (_UID, 3)
> + Method (_LPI, 0, NotSerialized) {
> + Return (\_SB.CLPI)
> + }
>
> Device (CP03) { // Neoverse N2 core 3
> Name (_HID, "ACPI0007")
> Name (_UID, 3)
> Name (_STA, 0xF)
> +
> + Method (_LPI, 0, NotSerialized) {
> + Return (\_SB.PLPI)
> + }
> }
> }
>
> Device (CL04) { // Cluster 4
> Name (_HID, "ACPI0010")
> Name (_UID, 4)
> + Method (_LPI, 0, NotSerialized) {
> + Return (\_SB.CLPI)
> + }
>
> Device (CP04) { // Neoverse N2 core 4
> Name (_HID, "ACPI0007")
> Name (_UID, 4)
> Name (_STA, 0xF)
> +
> + Method (_LPI, 0, NotSerialized) {
> + Return (\_SB.PLPI)
> + }
> }
> }
>
> Device (CL05) { // Cluster 5
> Name (_HID, "ACPI0010")
> Name (_UID, 5)
> + Method (_LPI, 0, NotSerialized) {
> + Return (\_SB.CLPI)
> + }
>
> Device (CP05) { // Neoverse N2 core 5
> Name (_HID, "ACPI0007")
> Name (_UID, 5)
> Name (_STA, 0xF)
> +
> + Method (_LPI, 0, NotSerialized) {
> + Return (\_SB.PLPI)
> + }
> }
> }
>
> Device (CL06) { // Cluster 6
> Name (_HID, "ACPI0010")
> Name (_UID, 6)
> + Method (_LPI, 0, NotSerialized) {
> + Return (\_SB.CLPI)
> + }
>
> Device (CP06) { // Neoverse N2 core 6
> Name (_HID, "ACPI0007")
> Name (_UID, 6)
> Name (_STA, 0xF)
> +
> + Method (_LPI, 0, NotSerialized) {
> + Return (\_SB.PLPI)
> + }
> }
> }
>
> Device (CL07) { // Cluster 7
> Name (_HID, "ACPI0010")
> Name (_UID, 7)
> + Method (_LPI, 0, NotSerialized) {
> + Return (\_SB.CLPI)
> + }
>
> Device (CP07) { // Neoverse N2 core 7
> Name (_HID, "ACPI0007")
> Name (_UID, 7)
> Name (_STA, 0xF)
> +
> + Method (_LPI, 0, NotSerialized) {
> + Return (\_SB.PLPI)
> + }
> }
> }
> } // Scope(_SB)
[-- Attachment #2: Type: text/html, Size: 9096 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V1 4/6] Platform/Sgi: ACPI CPPC support for RD-N2-Cfg1
2021-05-19 8:22 [edk2-platforms][PATCH V1 0/6] Platform/Sgi: Add initial support for RD-N2-Cfg1 platform Pranav Madhu
` (2 preceding siblings ...)
2021-05-19 8:22 ` [edk2-platforms][PATCH V1 3/6] Platform/Sgi: Low Power Idle states for RD-N2-Cfg1 Pranav Madhu
@ 2021-05-19 8:22 ` Pranav Madhu
2021-05-24 14:14 ` Sami Mujawar
2021-05-19 8:22 ` [edk2-platforms][PATCH V1 5/6] Platform/Sgi: Define RD-N2-Cfg1 platform id values Pranav Madhu
` (2 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Pranav Madhu @ 2021-05-19 8:22 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar
Enable ACPI CPPC mechanism for RD-N2-Cfg1 as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with SCP to set
the desired performance. RD-N2-Cfg1 platform does not support CPPC
revision 1 and below. So update the _OSC method to let OSPM know about
this fact.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 78 ++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
index 55f51cc26aff..411eff84334a 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
@@ -35,6 +35,12 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
}
+
+ If (And (CAP0, OSC_CAP_CPPC_SUPPORT)) {
+ /* CPPC revision 1 and below not supported */
+ And (CAP0, Not (OSC_CAP_CPPC_SUPPORT), CAP0)
+ Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+ }
} Else {
And (STS0, Not (OSC_STS_MASK), STS0)
Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
@@ -133,6 +139,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 0)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000500, 0x06000504, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (0)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -151,6 +166,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 1)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000518, 0x0600051C, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (1)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -169,6 +193,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 2)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000530, 0x06000534, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (2)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -187,6 +220,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 3)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000548, 0x0600054C, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (3)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -205,6 +247,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 4)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000560, 0x06000564, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (4)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -223,6 +274,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 5)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000578, 0x0600057C, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (5)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -241,6 +301,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 6)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000590, 0x06000594, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (6)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -259,6 +328,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 7)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x060005A8, 0x060005AC, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (7)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [edk2-platforms][PATCH V1 4/6] Platform/Sgi: ACPI CPPC support for RD-N2-Cfg1
2021-05-19 8:22 ` [edk2-platforms][PATCH V1 4/6] Platform/Sgi: ACPI CPPC support " Pranav Madhu
@ 2021-05-24 14:14 ` Sami Mujawar
0 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-05-24 14:14 UTC (permalink / raw)
To: Pranav Madhu, devel; +Cc: Ard Biesheuvel, nd
[-- Attachment #1: Type: text/plain, Size: 5517 bytes --]
Hi Pranav,
This patch looks good to me.
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Regards,
Sami Mujawar
On 19/05/2021 09:22 AM, Pranav Madhu wrote:
> Enable ACPI CPPC mechanism for RD-N2-Cfg1 as defined by the ACPI
> specification. The implementation uses AMU registers accessible as
> Fixed-feature Hardware (FFixedHW) for monitoring the performance.
> Non-secure SCMI fastchannels are used to communicate with SCP to set
> the desired performance. RD-N2-Cfg1 platform does not support CPPC
> revision 1 and below. So update the _OSC method to let OSPM know about
> this fact.
>
> Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
> ---
> Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 78 ++++++++++++++++++++
> 1 file changed, 78 insertions(+)
>
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
> index 55f51cc26aff..411eff84334a 100644
> --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
> +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
> @@ -35,6 +35,12 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
> And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
> Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
> }
> +
> + If (And (CAP0, OSC_CAP_CPPC_SUPPORT)) {
> + /* CPPC revision 1 and below not supported */
> + And (CAP0, Not (OSC_CAP_CPPC_SUPPORT), CAP0)
> + Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
> + }
> } Else {
> And (STS0, Not (OSC_STS_MASK), STS0)
> Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
> @@ -133,6 +139,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
> Name (_UID, 0)
> Name (_STA, 0xF)
>
> + Name (_CPC, Package()
> + CPPC_PACKAGE_INIT (0x06000500, 0x06000504, 20, 160, 160, 115, 115, 5)
> + )
> +
> + Name (_PSD, Package () {
> + Package ()
> + PSD_INIT (0)
> + })
> +
> Method (_LPI, 0, NotSerialized) {
> Return (\_SB.PLPI)
> }
> @@ -151,6 +166,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
> Name (_UID, 1)
> Name (_STA, 0xF)
>
> + Name (_CPC, Package()
> + CPPC_PACKAGE_INIT (0x06000518, 0x0600051C, 20, 160, 160, 115, 115, 5)
> + )
> +
> + Name (_PSD, Package () {
> + Package ()
> + PSD_INIT (1)
> + })
> +
> Method (_LPI, 0, NotSerialized) {
> Return (\_SB.PLPI)
> }
> @@ -169,6 +193,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
> Name (_UID, 2)
> Name (_STA, 0xF)
>
> + Name (_CPC, Package()
> + CPPC_PACKAGE_INIT (0x06000530, 0x06000534, 20, 160, 160, 115, 115, 5)
> + )
> +
> + Name (_PSD, Package () {
> + Package ()
> + PSD_INIT (2)
> + })
> +
> Method (_LPI, 0, NotSerialized) {
> Return (\_SB.PLPI)
> }
> @@ -187,6 +220,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
> Name (_UID, 3)
> Name (_STA, 0xF)
>
> + Name (_CPC, Package()
> + CPPC_PACKAGE_INIT (0x06000548, 0x0600054C, 20, 160, 160, 115, 115, 5)
> + )
> +
> + Name (_PSD, Package () {
> + Package ()
> + PSD_INIT (3)
> + })
> +
> Method (_LPI, 0, NotSerialized) {
> Return (\_SB.PLPI)
> }
> @@ -205,6 +247,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
> Name (_UID, 4)
> Name (_STA, 0xF)
>
> + Name (_CPC, Package()
> + CPPC_PACKAGE_INIT (0x06000560, 0x06000564, 20, 160, 160, 115, 115, 5)
> + )
> +
> + Name (_PSD, Package () {
> + Package ()
> + PSD_INIT (4)
> + })
> +
> Method (_LPI, 0, NotSerialized) {
> Return (\_SB.PLPI)
> }
> @@ -223,6 +274,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
> Name (_UID, 5)
> Name (_STA, 0xF)
>
> + Name (_CPC, Package()
> + CPPC_PACKAGE_INIT (0x06000578, 0x0600057C, 20, 160, 160, 115, 115, 5)
> + )
> +
> + Name (_PSD, Package () {
> + Package ()
> + PSD_INIT (5)
> + })
> +
> Method (_LPI, 0, NotSerialized) {
> Return (\_SB.PLPI)
> }
> @@ -241,6 +301,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
> Name (_UID, 6)
> Name (_STA, 0xF)
>
> + Name (_CPC, Package()
> + CPPC_PACKAGE_INIT (0x06000590, 0x06000594, 20, 160, 160, 115, 115, 5)
> + )
> +
> + Name (_PSD, Package () {
> + Package ()
> + PSD_INIT (6)
> + })
> +
> Method (_LPI, 0, NotSerialized) {
> Return (\_SB.PLPI)
> }
> @@ -259,6 +328,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
> Name (_UID, 7)
> Name (_STA, 0xF)
>
> + Name (_CPC, Package()
> + CPPC_PACKAGE_INIT (0x060005A8, 0x060005AC, 20, 160, 160, 115, 115, 5)
> + )
> +
> + Name (_PSD, Package () {
> + Package ()
> + PSD_INIT (7)
> + })
> +
> Method (_LPI, 0, NotSerialized) {
> Return (\_SB.PLPI)
> }
[-- Attachment #2: Type: text/html, Size: 6134 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V1 5/6] Platform/Sgi: Define RD-N2-Cfg1 platform id values
2021-05-19 8:22 [edk2-platforms][PATCH V1 0/6] Platform/Sgi: Add initial support for RD-N2-Cfg1 platform Pranav Madhu
` (3 preceding siblings ...)
2021-05-19 8:22 ` [edk2-platforms][PATCH V1 4/6] Platform/Sgi: ACPI CPPC support " Pranav Madhu
@ 2021-05-19 8:22 ` Pranav Madhu
2021-05-24 14:14 ` Sami Mujawar
2021-05-19 8:22 ` [edk2-platforms][PATCH V1 6/6] Platform/Sgi: Extend SMBIOS support for RD-N2-Cfg1 Pranav Madhu
2021-05-19 11:42 ` [edk2-devel] [edk2-platforms][PATCH V1 0/6] Platform/Sgi: Add initial support for RD-N2-Cfg1 platform Thomas Abraham
6 siblings, 1 reply; 14+ messages in thread
From: Pranav Madhu @ 2021-05-19 8:22 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar
Add the RD-N2-Cfg1 platform identification values including the part
number and configuration number. This information will be used in
populating the SMBIOS tables.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/Include/SgiPlatform.h | 7 ++++++-
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 8 +++++++-
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index 4999c9870b49..dddb58832d73 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -39,6 +39,10 @@
#define RD_V1_CONF_ID 0x1
#define RD_V1_MC_CONF_ID 0x2
+// RD-N2-Cfg1 Platform Identification values
+#define RD_N2_CFG1_PART_NUM 0x7B6
+#define RD_N2_CFG1_CONF_ID 0x1
+
// RD-N2 Platform Identification values
#define RD_N2_PART_NUM 0x7B7
#define RD_N2_CONF_ID 0x1
@@ -77,7 +81,8 @@ typedef enum {
RdE1Edge,
RdV1,
RdV1Mc,
- RdN2
+ RdN2,
+ RdN2Cfg1
} ARM_RD_PRODUCT_ID;
// Arm ProductId look-up table
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
index f27c949dbc24..a982e3d403fa 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
@@ -66,7 +66,13 @@ STATIC CONST SGI_PRODUCT_ID_LOOKUP SgiProductIdLookup[] = {
RD_N2_PART_NUM,
RD_N2_CONF_ID,
0
- }
+ },
+ {
+ RdN2Cfg1,
+ RD_N2_CFG1_PART_NUM,
+ RD_N2_CFG1_CONF_ID,
+ 0
+ },
};
EFI_BOOT_MODE
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [edk2-platforms][PATCH V1 5/6] Platform/Sgi: Define RD-N2-Cfg1 platform id values
2021-05-19 8:22 ` [edk2-platforms][PATCH V1 5/6] Platform/Sgi: Define RD-N2-Cfg1 platform id values Pranav Madhu
@ 2021-05-24 14:14 ` Sami Mujawar
0 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-05-24 14:14 UTC (permalink / raw)
To: Pranav Madhu, devel; +Cc: Ard Biesheuvel, nd
[-- Attachment #1: Type: text/plain, Size: 2053 bytes --]
Hi Pranav,
This patch looks good to me.
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Regards,
Sami Mujawar
On 19/05/2021 09:22 AM, Pranav Madhu wrote:
> Add the RD-N2-Cfg1 platform identification values including the part
> number and configuration number. This information will be used in
> populating the SMBIOS tables.
>
> Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
> ---
> Platform/ARM/SgiPkg/Include/SgiPlatform.h | 7 ++++++-
> Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 8 +++++++-
> 2 files changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
> index 4999c9870b49..dddb58832d73 100644
> --- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
> +++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
> @@ -39,6 +39,10 @@
> #define RD_V1_CONF_ID 0x1
> #define RD_V1_MC_CONF_ID 0x2
>
> +// RD-N2-Cfg1 Platform Identification values
> +#define RD_N2_CFG1_PART_NUM 0x7B6
> +#define RD_N2_CFG1_CONF_ID 0x1
> +
> // RD-N2 Platform Identification values
> #define RD_N2_PART_NUM 0x7B7
> #define RD_N2_CONF_ID 0x1
> @@ -77,7 +81,8 @@ typedef enum {
> RdE1Edge,
> RdV1,
> RdV1Mc,
> - RdN2
> + RdN2,
> + RdN2Cfg1
> } ARM_RD_PRODUCT_ID;
>
> // Arm ProductId look-up table
> diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
> index f27c949dbc24..a982e3d403fa 100644
> --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
> +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
> @@ -66,7 +66,13 @@ STATIC CONST SGI_PRODUCT_ID_LOOKUP SgiProductIdLookup[] = {
> RD_N2_PART_NUM,
> RD_N2_CONF_ID,
> 0
> - }
> + },
> + {
> + RdN2Cfg1,
> + RD_N2_CFG1_PART_NUM,
> + RD_N2_CFG1_CONF_ID,
> + 0
> + },
> };
>
> EFI_BOOT_MODE
[-- Attachment #2: Type: text/html, Size: 2553 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V1 6/6] Platform/Sgi: Extend SMBIOS support for RD-N2-Cfg1
2021-05-19 8:22 [edk2-platforms][PATCH V1 0/6] Platform/Sgi: Add initial support for RD-N2-Cfg1 platform Pranav Madhu
` (4 preceding siblings ...)
2021-05-19 8:22 ` [edk2-platforms][PATCH V1 5/6] Platform/Sgi: Define RD-N2-Cfg1 platform id values Pranav Madhu
@ 2021-05-19 8:22 ` Pranav Madhu
2021-05-24 14:15 ` Sami Mujawar
2021-05-19 11:42 ` [edk2-devel] [edk2-platforms][PATCH V1 0/6] Platform/Sgi: Add initial support for RD-N2-Cfg1 platform Thomas Abraham
6 siblings, 1 reply; 14+ messages in thread
From: Pranav Madhu @ 2021-05-19 8:22 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar
Extend the SMBIOS support for RD-N2-Cfg1 platform. RD-N2-Cfg1 platform
is a derivative of the RD-N2 platform and so most of the table values
for RD-N2 platform is reused.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c | 7 +++++--
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c | 7 +++++--
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c | 18 ++++++++++++++++++
3 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
index 367587c07673..e8326cc6ef14 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
@@ -31,7 +31,8 @@
"RdE1Edge\0" \
"RdV1\0" \
"RdV1Mc\0" \
- "RdN2\0"
+ "RdN2\0" \
+ "RdN2Cfg1\0"
typedef enum {
ManufacturerName = 1,
@@ -64,7 +65,9 @@ STATIC GUID mSmbiosUid[] = {
/* Rd-V1Mc */
{0x1f3a0806, 0x18b5, 0x4eca, {0xad, 0xcd, 0xba, 0x9b, 0x07, 0xb1, 0x0a, 0xcf}},
/* Rd-N2 */
- {0xf2cded73, 0x37f9, 0x4ec9, {0xd9, 0xf9, 0x89, 0x9b, 0x74, 0x91, 0x20, 0x49}}
+ {0xf2cded73, 0x37f9, 0x4ec9, {0xd9, 0xf9, 0x89, 0x9b, 0x74, 0x91, 0x20, 0x49}},
+ /* Rd-N2-Cfg1 */
+ {0xa4941d3d, 0xfac3, 0x4ace, {0x9a, 0x7e, 0xce, 0x26, 0x76, 0x64, 0x5e, 0xda}},
};
/* System information */
diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
index 9ecaea3603de..b554ee6dea58 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
@@ -27,7 +27,7 @@
#define SOCKET_TYPE_BASE 3
#define SOCKET_TYPE_NUM 1
#define PROCESSOR_VERSION_BASE (SOCKET_TYPE_BASE + SOCKET_TYPE_NUM)
-#define PROCESSOR_VERSION_NUM 8
+#define PROCESSOR_VERSION_NUM 9
#define SERIAL_NUMBER_BASE (PROCESSOR_VERSION_BASE + PROCESSOR_VERSION_NUM)
#define TYPE4_STRINGS \
"0x000\0" /* Part Number */ \
@@ -41,6 +41,7 @@
"Neoverse-V1\0" \
"Neoverse-V1\0" \
"Neoverse-N2\0" \
+ "Neoverse-N2\0" \
"000-0\0" /* Serial number */ \
"783-3\0" \
"786-1\0" \
@@ -48,7 +49,8 @@
"786-2\0" \
"78A-1\0" \
"78A-2\0" \
- "7B7-1\0"
+ "7B7-1\0" \
+ "7B6-1\0"
typedef enum {
PartNumber = 1,
@@ -173,6 +175,7 @@ InstallType4ProcessorInformation (
mArmRdSmbiosType4.Base.ThreadCount = CoreCount;
break;
case RdN2:
+ case RdN2Cfg1:
mArmRdSmbiosType4.Base.CoreCount = CoreCount;
mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount;
mArmRdSmbiosType4.Base.ThreadCount = CoreCount;
diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
index 6be62900bd71..aec7c1b585fc 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
@@ -315,6 +315,24 @@ InstallType7CacheInformation (
mArmRdSmbiosType7[4].Base.InstalledSize2 = 32768; // 32MB SLC
mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
break;
+ case RdN2Cfg1:
+ /* L1 instruction cache */
+ mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64; // 64KB
+ mArmRdSmbiosType7[0].Base.InstalledSize2 = 64; // 64KB
+ mArmRdSmbiosType7[0].Base.Associativity = CacheAssociativity4Way;
+ /* L1 data cache */
+ mArmRdSmbiosType7[1].Base.MaximumCacheSize2 = 64; // 64KB
+ mArmRdSmbiosType7[1].Base.InstalledSize2 = 64; // 64KB
+ mArmRdSmbiosType7[1].Base.Associativity = CacheAssociativity4Way;
+ /* L2 cache */
+ mArmRdSmbiosType7[2].Base.MaximumCacheSize2 = 1024; // 1MB
+ mArmRdSmbiosType7[2].Base.InstalledSize2 = 1024; // 1MB
+ mArmRdSmbiosType7[2].Base.Associativity = CacheAssociativity8Way;
+ /* System level cache */
+ mArmRdSmbiosType7[4].Base.MaximumCacheSize2 = 8192; // 8MB SLC
+ mArmRdSmbiosType7[4].Base.InstalledSize2 = 8192; // 8MB SLC
+ mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
+ break;
}
/* Install valid cache information tables */
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [edk2-platforms][PATCH V1 6/6] Platform/Sgi: Extend SMBIOS support for RD-N2-Cfg1
2021-05-19 8:22 ` [edk2-platforms][PATCH V1 6/6] Platform/Sgi: Extend SMBIOS support for RD-N2-Cfg1 Pranav Madhu
@ 2021-05-24 14:15 ` Sami Mujawar
0 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-05-24 14:15 UTC (permalink / raw)
To: Pranav Madhu, devel; +Cc: Ard Biesheuvel, nd
[-- Attachment #1: Type: text/plain, Size: 5538 bytes --]
Hi Pranav,
This patch looks good to me.
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Regards,
Sami Mujawar
On 19/05/2021 09:22 AM, Pranav Madhu wrote:
> Extend the SMBIOS support for RD-N2-Cfg1 platform. RD-N2-Cfg1 platform
> is a derivative of the RD-N2 platform and so most of the table values
> for RD-N2 platform is reused.
>
> Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
> ---
> Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c | 7 +++++--
> Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c | 7 +++++--
> Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c | 18 ++++++++++++++++++
> 3 files changed, 28 insertions(+), 4 deletions(-)
>
> diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
> index 367587c07673..e8326cc6ef14 100644
> --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
> +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
> @@ -31,7 +31,8 @@
> "RdE1Edge\0" \
> "RdV1\0" \
> "RdV1Mc\0" \
> - "RdN2\0"
> + "RdN2\0" \
> + "RdN2Cfg1\0"
>
> typedef enum {
> ManufacturerName = 1,
> @@ -64,7 +65,9 @@ STATIC GUID mSmbiosUid[] = {
> /* Rd-V1Mc */
> {0x1f3a0806, 0x18b5, 0x4eca, {0xad, 0xcd, 0xba, 0x9b, 0x07, 0xb1, 0x0a, 0xcf}},
> /* Rd-N2 */
> - {0xf2cded73, 0x37f9, 0x4ec9, {0xd9, 0xf9, 0x89, 0x9b, 0x74, 0x91, 0x20, 0x49}}
> + {0xf2cded73, 0x37f9, 0x4ec9, {0xd9, 0xf9, 0x89, 0x9b, 0x74, 0x91, 0x20, 0x49}},
> + /* Rd-N2-Cfg1 */
> + {0xa4941d3d, 0xfac3, 0x4ace, {0x9a, 0x7e, 0xce, 0x26, 0x76, 0x64, 0x5e, 0xda}},
> };
>
> /* System information */
> diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
> index 9ecaea3603de..b554ee6dea58 100644
> --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
> +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
> @@ -27,7 +27,7 @@
> #define SOCKET_TYPE_BASE 3
> #define SOCKET_TYPE_NUM 1
> #define PROCESSOR_VERSION_BASE (SOCKET_TYPE_BASE + SOCKET_TYPE_NUM)
> -#define PROCESSOR_VERSION_NUM 8
> +#define PROCESSOR_VERSION_NUM 9
> #define SERIAL_NUMBER_BASE (PROCESSOR_VERSION_BASE + PROCESSOR_VERSION_NUM)
> #define TYPE4_STRINGS \
> "0x000\0" /* Part Number */ \
> @@ -41,6 +41,7 @@
> "Neoverse-V1\0" \
> "Neoverse-V1\0" \
> "Neoverse-N2\0" \
> + "Neoverse-N2\0" \
> "000-0\0" /* Serial number */ \
> "783-3\0" \
> "786-1\0" \
> @@ -48,7 +49,8 @@
> "786-2\0" \
> "78A-1\0" \
> "78A-2\0" \
> - "7B7-1\0"
> + "7B7-1\0" \
> + "7B6-1\0"
>
> typedef enum {
> PartNumber = 1,
> @@ -173,6 +175,7 @@ InstallType4ProcessorInformation (
> mArmRdSmbiosType4.Base.ThreadCount = CoreCount;
> break;
> case RdN2:
> + case RdN2Cfg1:
> mArmRdSmbiosType4.Base.CoreCount = CoreCount;
> mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount;
> mArmRdSmbiosType4.Base.ThreadCount = CoreCount;
> diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
> index 6be62900bd71..aec7c1b585fc 100644
> --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
> +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
> @@ -315,6 +315,24 @@ InstallType7CacheInformation (
> mArmRdSmbiosType7[4].Base.InstalledSize2 = 32768; // 32MB SLC
> mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
> break;
> + case RdN2Cfg1:
> + /* L1 instruction cache */
> + mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64; // 64KB
> + mArmRdSmbiosType7[0].Base.InstalledSize2 = 64; // 64KB
> + mArmRdSmbiosType7[0].Base.Associativity = CacheAssociativity4Way;
> + /* L1 data cache */
> + mArmRdSmbiosType7[1].Base.MaximumCacheSize2 = 64; // 64KB
> + mArmRdSmbiosType7[1].Base.InstalledSize2 = 64; // 64KB
> + mArmRdSmbiosType7[1].Base.Associativity = CacheAssociativity4Way;
> + /* L2 cache */
> + mArmRdSmbiosType7[2].Base.MaximumCacheSize2 = 1024; // 1MB
> + mArmRdSmbiosType7[2].Base.InstalledSize2 = 1024; // 1MB
> + mArmRdSmbiosType7[2].Base.Associativity = CacheAssociativity8Way;
> + /* System level cache */
> + mArmRdSmbiosType7[4].Base.MaximumCacheSize2 = 8192; // 8MB SLC
> + mArmRdSmbiosType7[4].Base.InstalledSize2 = 8192; // 8MB SLC
> + mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
> + break;
> }
>
> /* Install valid cache information tables */
[-- Attachment #2: Type: text/html, Size: 6113 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [edk2-devel] [edk2-platforms][PATCH V1 0/6] Platform/Sgi: Add initial support for RD-N2-Cfg1 platform
2021-05-19 8:22 [edk2-platforms][PATCH V1 0/6] Platform/Sgi: Add initial support for RD-N2-Cfg1 platform Pranav Madhu
` (5 preceding siblings ...)
2021-05-19 8:22 ` [edk2-platforms][PATCH V1 6/6] Platform/Sgi: Extend SMBIOS support for RD-N2-Cfg1 Pranav Madhu
@ 2021-05-19 11:42 ` Thomas Abraham
6 siblings, 0 replies; 14+ messages in thread
From: Thomas Abraham @ 2021-05-19 11:42 UTC (permalink / raw)
To: devel@edk2.groups.io, Pranav Madhu; +Cc: Ard Biesheuvel, Sami Mujawar, nd
On 5/19/21 1:52 PM, Pranav Madhu via groups.io wrote:
> RD-N2-Cfg1 platform is a variant of the RD-N2 platform. The platform
> is based on 8xMP1 Neoverse N2 CPUs, CMN-700 interconnect 3x3 mesh,
> multiple AXI expansion ports for I/O Coherent PCIe, Ethernet, offload
> and Arm Cortex-M7 for System Control Processor (SCP) and Manageability
> Control Processor (MCP).
>
> The first patch in this series add Edk2 build system files and minimum
> acpi changes required to boot the platform. The second patch add ACPI
> PPTT table to describe the CPU and cache topology. The third patch in
> this series enable idle state support (ACPI LPI) and the fourth patch
> enables ACPI CPPC support to support the OS to scale CPU performance.
> The last patch in this series adds SMBIOS support.
>
> This patch series should be applied on top of the patch series
> https://edk2.groups.io/g/devel/message/75277
>
> Link to github branch with the patches in this series -
> https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rdn2cfg1-initial-
> support
>
> Aditya Angadi (1):
> Platform/Sgi: Add initial support for RD-N2-Cfg1 platform
>
> Pranav Madhu (5):
> Platform/Sgi: ACPI PPTT table for RD-N2-Cfg1 platform
> Platform/Sgi: Low Power Idle states for RD-N2-Cfg1
> Platform/Sgi: ACPI CPPC support for RD-N2-Cfg1
> Platform/Sgi: Define RD-N2-Cfg1 platform id values
> Platform/Sgi: Extend SMBIOS support for RD-N2-Cfg1
For this series:
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
[...]
^ permalink raw reply [flat|nested] 14+ messages in thread