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From: "Zhiguang Liu" <zhiguang.liu@intel.com>
To: devel@edk2.groups.io
Cc: Michael D Kinney <michael.d.kinney@intel.com>,
	Liming Gao <gaoliming@byosoft.com.cn>
Subject: [PATCH 2/9] MdePkg: Add new structure for the PCI Root Bridge Info Hob
Date: Mon, 24 May 2021 15:12:27 +0800	[thread overview]
Message-ID: <20210524071234.1056-3-zhiguang.liu@intel.com> (raw)
In-Reply-To: <20210524071234.1056-1-zhiguang.liu@intel.com>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
 MdePkg/Include/UniversalPayload/PciRootBridges.h | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 MdePkg/MdePkg.dec                                |  6 ++++++
 2 files changed, 95 insertions(+)

diff --git a/MdePkg/Include/UniversalPayload/PciRootBridges.h b/MdePkg/Include/UniversalPayload/PciRootBridges.h
new file mode 100644
index 0000000000..72e8331ede
--- /dev/null
+++ b/MdePkg/Include/UniversalPayload/PciRootBridges.h
@@ -0,0 +1,89 @@
+/** @file
+  This file defines the structure for the PCI Root Bridges.
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PLD_PCI_ROOT_BRIDGES_H__
+#define __PLD_PCI_ROOT_BRIDGES_H__
+
+#include <UniversalPayload/UniversalPayload.h>
+
+#pragma pack(1)
+
+//
+// (Base > Limit) indicates an aperture is not available.
+//
+typedef struct {
+  //
+  // Base and Limit are the device address instead of host address when
+  // Translation is not zero
+  //
+  UINT64 Base;
+  UINT64 Limit;
+  //
+  // According to UEFI 2.7, Device Address = Host Address + Translation,
+  // so Translation = Device Address - Host Address.
+  // On platforms where Translation is not zero, the subtraction is probably to
+  // be performed with UINT64 wrap-around semantics, for we may translate an
+  // above-4G host address into a below-4G device address for legacy PCIe device
+  // compatibility.
+  //
+  // NOTE: The alignment of Translation is required to be larger than any BAR
+  // alignment in the same root bridge, so that the same alignment can be
+  // applied to both device address and host address, which simplifies the
+  // situation and makes the current resource allocation code in generic PCI
+  // host bridge driver still work.
+  //
+  UINT64 Translation;
+} PLD_PCI_ROOT_BRIDGE_APERTURE;
+
+///
+/// Payload PCI Root Bridge Information HOB
+///
+typedef struct {
+  UINT32                       Segment;               ///< Segment number.
+  UINT64                       Supports;              ///< Supported attributes.
+                                                      ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()
+                                                      ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+  UINT64                       Attributes;            ///< Initial attributes.
+                                                      ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()
+                                                      ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+  BOOLEAN                      DmaAbove4G;            ///< DMA above 4GB memory.
+                                                      ///< Set to TRUE when root bridge supports DMA above 4GB memory.
+  BOOLEAN                      NoExtendedConfigSpace; ///< When FALSE, the root bridge supports
+                                                      ///< Extended (4096-byte) Configuration Space.
+                                                      ///< When TRUE, the root bridge supports
+                                                      ///< 256-byte Configuration Space only.
+  UINT64                       AllocationAttributes;  ///< Allocation attributes.
+                                                      ///< Refer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and
+                                                      ///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes()
+                                                      ///< in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
+  PLD_PCI_ROOT_BRIDGE_APERTURE Bus;                   ///< Bus aperture which can be used by the root bridge.
+  PLD_PCI_ROOT_BRIDGE_APERTURE Io;                    ///< IO aperture which can be used by the root bridge.
+  PLD_PCI_ROOT_BRIDGE_APERTURE Mem;                   ///< MMIO aperture below 4GB which can be used by the root bridge.
+  PLD_PCI_ROOT_BRIDGE_APERTURE MemAbove4G;            ///< MMIO aperture above 4GB which can be used by the root bridge.
+  PLD_PCI_ROOT_BRIDGE_APERTURE PMem;                  ///< Prefetchable MMIO aperture below 4GB which can be used by the root bridge.
+  PLD_PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;           ///< Prefetchable MMIO aperture above 4GB which can be used by the root bridge.
+  UINT32                       HID;                   ///< PnP hardware ID of the root bridge. This value must match the corresponding
+                                                      ///< _HID in the ACPI name space.
+  UINT32                       UID;                   ///< Unique ID that is required by ACPI if two devices have the same _HID.
+                                                      ///< This value must also match the corresponding _UID/_HID pair in the ACPI name space.
+} PLD_PCI_ROOT_BRIDGE;
+
+typedef struct {
+  PLD_GENERIC_HEADER   PldHeader;
+  BOOLEAN              ResourceAssigned;
+  UINT8                Count;
+  PLD_PCI_ROOT_BRIDGE  RootBridge[0];
+} PLD_PCI_ROOT_BRIDGES;
+
+#pragma pack()
+
+#define PLD_PCI_ROOT_BRIDGES_REVISION 1
+
+extern GUID gPldPciRootBridgeInfoGuid;
+
+#endif // __PLD_PCI_ROOT_BRIDGES_H__
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index b49f88d8e1..3cf509728b 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -818,6 +818,12 @@
   #
   gTianoCustomDecompressGuid     = { 0xA31280AD, 0x481E, 0x41B6, { 0x95, 0xE8, 0x12, 0x7F, 0x4C, 0x98, 0x47, 0x79 }}
 
+  #
+  # GUID defined in UniversalPayload
+  #
+  ## Include/UniversalPayload/PciRootBridges.h
+  gPldPciRootBridgeInfoGuid = { 0xec4ebacb, 0x2638, 0x416e, { 0xbe, 0x80, 0xe5, 0xfa, 0x4b, 0x51, 0x19, 0x01 }}
+
 [Guids.IA32, Guids.X64]
   ## Include/Guid/Cper.h
   gEfiIa32X64ErrorTypeCacheCheckGuid = { 0xA55701F5, 0xE3EF, 0x43de, { 0xAC, 0x72, 0x24, 0x9B, 0x57, 0x3F, 0xAD, 0x2C }}
-- 
2.30.0.windows.2


  parent reply	other threads:[~2021-05-24  7:13 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-24  7:12 [PATCH 0/9] Create multiple Hobs for Universal Payload Zhiguang Liu
2021-05-24  7:12 ` [PATCH 1/9] MdePkg: Add Universal Payload general defination header file Zhiguang Liu
2021-05-24  7:12 ` Zhiguang Liu [this message]
2021-05-24  7:12 ` [PATCH 3/9] UefiPayloadPkg: UefiPayload retrieve PCI root bridge from Guid Hob Zhiguang Liu
2021-05-24  7:12 ` [PATCH 4/9] MdePkg: Add new structure for the Universal Payload SMBios Table Info Hob Zhiguang Liu
2021-05-24  7:12 ` [PATCH 5/9] MdeModulePkg/Universal/SmbiosDxe: Scan for existing tables Zhiguang Liu
2021-05-26  6:15   ` Wu, Hao A
2021-05-26  6:32     ` [edk2-devel] " Wu, Hao A
2021-05-26  8:56       ` Zhiguang Liu
2021-05-26 13:04   ` Patrick Rudolph
2021-05-24  7:12 ` [PATCH 6/9] UefiPayloadPkg: Creat gPldSmbiosTableGuid Hob Zhiguang Liu
2021-06-02  3:39   ` Guo Dong
2021-05-24  7:12 ` [PATCH 7/9] MdePkg: Add new structure for the Universal Payload ACPI Table Info Hob Zhiguang Liu
2021-05-24  7:12 ` [PATCH 8/9] MdeModulePkg/ACPI: Install ACPI table from HOB Zhiguang Liu
2021-05-27  0:42   ` Wu, Hao A
2021-05-24  7:12 ` [PATCH 9/9] UefiPayloadPkg: Creat gPldAcpiTableGuid Hob Zhiguang Liu
2021-05-26 13:50   ` [edk2-devel] " Patrick Rudolph
2021-06-02  3:47     ` Guo Dong
2021-05-28  3:00 ` 回复: [edk2-devel] [PATCH 0/9] Create multiple Hobs for Universal Payload gaoliming

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