From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga07.intel.com (mga07.intel.com []) by mx.groups.io with SMTP id smtpd.web11.19984.1621840379860146758 for ; Mon, 24 May 2021 00:13:00 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: zhiguang.liu@intel.com) IronPort-SDR: C2NIgiXpkyRaKYkTM9qa2r6/1AvcJD373yopU0GqDzYL0eJzs/Ks6n9IFb0y5A9NxViZFjJr6E kq6dnoIDkIeQ== X-IronPort-AV: E=McAfee;i="6200,9189,9993"; a="265769820" X-IronPort-AV: E=Sophos;i="5.82,319,1613462400"; d="scan'208";a="265769820" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2021 00:12:59 -0700 IronPort-SDR: WR+8Mj+x5hojbQisBWBjPKLlf2DIbhsbI+cuhS3RdDxRRGv5EnEYOJKrSo8mK+lzimgY/84Yn0 z058nM13Ir2g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,319,1613462400"; d="scan'208";a="413477705" Received: from fieedk002.ccr.corp.intel.com ([10.239.158.144]) by orsmga002.jf.intel.com with ESMTP; 24 May 2021 00:12:56 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao Subject: [PATCH 2/9] MdePkg: Add new structure for the PCI Root Bridge Info Hob Date: Mon, 24 May 2021 15:12:27 +0800 Message-Id: <20210524071234.1056-3-zhiguang.liu@intel.com> X-Mailer: git-send-email 2.30.0.windows.2 In-Reply-To: <20210524071234.1056-1-zhiguang.liu@intel.com> References: <20210524071234.1056-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Cc: Michael D Kinney Cc: Liming Gao Signed-off-by: Zhiguang Liu --- MdePkg/Include/UniversalPayload/PciRootBridges.h | 89 ++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ MdePkg/MdePkg.dec | 6 ++++++ 2 files changed, 95 insertions(+) diff --git a/MdePkg/Include/UniversalPayload/PciRootBridges.h b/MdePkg/Incl= ude/UniversalPayload/PciRootBridges.h new file mode 100644 index 0000000000..72e8331ede --- /dev/null +++ b/MdePkg/Include/UniversalPayload/PciRootBridges.h @@ -0,0 +1,89 @@ +/** @file=0D + This file defines the structure for the PCI Root Bridges.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef __PLD_PCI_ROOT_BRIDGES_H__=0D +#define __PLD_PCI_ROOT_BRIDGES_H__=0D +=0D +#include =0D +=0D +#pragma pack(1)=0D +=0D +//=0D +// (Base > Limit) indicates an aperture is not available.=0D +//=0D +typedef struct {=0D + //=0D + // Base and Limit are the device address instead of host address when=0D + // Translation is not zero=0D + //=0D + UINT64 Base;=0D + UINT64 Limit;=0D + //=0D + // According to UEFI 2.7, Device Address =3D Host Address + Translation,= =0D + // so Translation =3D Device Address - Host Address.=0D + // On platforms where Translation is not zero, the subtraction is probab= ly to=0D + // be performed with UINT64 wrap-around semantics, for we may translate = an=0D + // above-4G host address into a below-4G device address for legacy PCIe = device=0D + // compatibility.=0D + //=0D + // NOTE: The alignment of Translation is required to be larger than any = BAR=0D + // alignment in the same root bridge, so that the same alignment can be= =0D + // applied to both device address and host address, which simplifies the= =0D + // situation and makes the current resource allocation code in generic P= CI=0D + // host bridge driver still work.=0D + //=0D + UINT64 Translation;=0D +} PLD_PCI_ROOT_BRIDGE_APERTURE;=0D +=0D +///=0D +/// Payload PCI Root Bridge Information HOB=0D +///=0D +typedef struct {=0D + UINT32 Segment; ///< Segment number.= =0D + UINT64 Supports; ///< Supported attri= butes.=0D + ///< Refer to EFI_PC= I_ATTRIBUTE_xxx used by GetAttributes()=0D + ///< and SetAttribut= es() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.=0D + UINT64 Attributes; ///< Initial attribu= tes.=0D + ///< Refer to EFI_PC= I_ATTRIBUTE_xxx used by GetAttributes()=0D + ///< and SetAttribut= es() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.=0D + BOOLEAN DmaAbove4G; ///< DMA above 4GB m= emory.=0D + ///< Set to TRUE whe= n root bridge supports DMA above 4GB memory.=0D + BOOLEAN NoExtendedConfigSpace; ///< When FALSE, the= root bridge supports=0D + ///< Extended (4096-= byte) Configuration Space.=0D + ///< When TRUE, the = root bridge supports=0D + ///< 256-byte Config= uration Space only.=0D + UINT64 AllocationAttributes; ///< Allocation attr= ibutes.=0D + ///< Refer to EFI_PC= I_HOST_BRIDGE_COMBINE_MEM_PMEM and=0D + ///< EFI_PCI_HOST_BR= IDGE_MEM64_DECODE used by GetAllocAttributes()=0D + ///< in EFI_PCI_HOST= _BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.=0D + PLD_PCI_ROOT_BRIDGE_APERTURE Bus; ///< Bus aperture wh= ich can be used by the root bridge.=0D + PLD_PCI_ROOT_BRIDGE_APERTURE Io; ///< IO aperture whi= ch can be used by the root bridge.=0D + PLD_PCI_ROOT_BRIDGE_APERTURE Mem; ///< MMIO aperture b= elow 4GB which can be used by the root bridge.=0D + PLD_PCI_ROOT_BRIDGE_APERTURE MemAbove4G; ///< MMIO aperture a= bove 4GB which can be used by the root bridge.=0D + PLD_PCI_ROOT_BRIDGE_APERTURE PMem; ///< Prefetchable MM= IO aperture below 4GB which can be used by the root bridge.=0D + PLD_PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; ///< Prefetchable MM= IO aperture above 4GB which can be used by the root bridge.=0D + UINT32 HID; ///< PnP hardware ID= of the root bridge. This value must match the corresponding=0D + ///< _HID in the ACP= I name space.=0D + UINT32 UID; ///< Unique ID that = is required by ACPI if two devices have the same _HID.=0D + ///< This value must= also match the corresponding _UID/_HID pair in the ACPI name space.=0D +} PLD_PCI_ROOT_BRIDGE;=0D +=0D +typedef struct {=0D + PLD_GENERIC_HEADER PldHeader;=0D + BOOLEAN ResourceAssigned;=0D + UINT8 Count;=0D + PLD_PCI_ROOT_BRIDGE RootBridge[0];=0D +} PLD_PCI_ROOT_BRIDGES;=0D +=0D +#pragma pack()=0D +=0D +#define PLD_PCI_ROOT_BRIDGES_REVISION 1=0D +=0D +extern GUID gPldPciRootBridgeInfoGuid;=0D +=0D +#endif // __PLD_PCI_ROOT_BRIDGES_H__=0D diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index b49f88d8e1..3cf509728b 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -818,6 +818,12 @@ #=0D gTianoCustomDecompressGuid =3D { 0xA31280AD, 0x481E, 0x41B6, { 0x95,= 0xE8, 0x12, 0x7F, 0x4C, 0x98, 0x47, 0x79 }}=0D =0D + #=0D + # GUID defined in UniversalPayload=0D + #=0D + ## Include/UniversalPayload/PciRootBridges.h=0D + gPldPciRootBridgeInfoGuid =3D { 0xec4ebacb, 0x2638, 0x416e, { 0xbe, 0x80= , 0xe5, 0xfa, 0x4b, 0x51, 0x19, 0x01 }}=0D +=0D [Guids.IA32, Guids.X64]=0D ## Include/Guid/Cper.h=0D gEfiIa32X64ErrorTypeCacheCheckGuid =3D { 0xA55701F5, 0xE3EF, 0x43de, { 0= xAC, 0x72, 0x24, 0x9B, 0x57, 0x3F, 0xAD, 0x2C }}=0D --=20 2.30.0.windows.2