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charset=UTF-8 Content-Transfer-Encoding: quoted-printable From: Vu Nguyen This commit adds the support for Ampere=E2=80=99s Altra processor-based Mt.= Jade platform that provides up to 160 processor cores in a dual socket configuration. The essential modules are wired up enough to boot system to EDK2 UiApp. Cc: Thang Nguyen Cc: Chuong Tran Cc: Phong Vo Cc: Leif Lindholm Cc: Michael D Kinney Cc: Ard Biesheuvel Cc: Nate DeSimone Signed-off-by: Vu Nguyen --- Platform/Ampere/AmperePlatformPkg/AmperePlatformPkg.dec = | 28 + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec = | 42 ++ Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec = | 46 ++ Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc = | 674 +++++++++++++++++++ Platform/Ampere/JadePkg/Jade.dsc = | 100 +++ Platform/Ampere/JadePkg/Jade.fdf = | 225 +++++++ Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.inf = | 41 ++ Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInitPeim.inf = | 64 ++ Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.inf = | 44 ++ Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.inf = | 57 ++ Silicon/Ampere/AmpereAltraPkg/Library/MailboxInterfaceLib/MailboxInterface= Lib.inf | 37 + Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiLib.in= f | 63 ++ Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicationLi= b.inf | 35 + Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.inf = | 32 + Silicon/Ampere/AmpereAltraPkg/Library/PlatformPeiLib/PlatformPeiLib.inf = | 42 ++ Silicon/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.inf = | 29 + Silicon/Ampere/AmpereAltraPkg/Library/SystemFirmwareInterfaceLib/SystemFir= mwareInterfaceLib.inf | 30 + Silicon/Ampere/AmpereAltraPkg/Library/TrngLib/TrngLib.inf = | 29 + Silicon/Ampere/AmpereAltraPkg/Include/Guid/PlatformInfoHobGuid.h = | 17 + Silicon/Ampere/AmpereAltraPkg/Include/Library/AmpereCpuLib.h = | 282 ++++++++ Silicon/Ampere/AmpereAltraPkg/Include/Library/MailboxInterfaceLib.h = | 172 +++++ Silicon/Ampere/AmpereAltraPkg/Include/Library/MmCommunicationLib.h = | 19 + Silicon/Ampere/AmpereAltraPkg/Include/Library/NVParamLib.h = | 133 ++++ Silicon/Ampere/AmpereAltraPkg/Include/Library/SystemFirmwareInterfaceLib.h= | 282 ++++++++ Silicon/Ampere/AmpereAltraPkg/Include/Library/TrngLib.h = | 31 + Silicon/Ampere/AmpereAltraPkg/Include/MmLib.h = | 79 +++ Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h = | 515 ++++++++++++++ Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h = | 146 ++++ Silicon/Ampere/AmpereAltraPkg/Include/PlatformInfoHob.h = | 182 +++++ Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.c = | 52 ++ Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInitPeim.c = | 151 +++++ Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.c = | 706 ++++++++++++++++++++ Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c = | 169 +++++ Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLibMemory.= c | 399 +++++++++++ Silicon/Ampere/AmpereAltraPkg/Library/MailboxInterfaceLib/MailboxInterface= Lib.c | 282 ++++++++ Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiLib.c = | 93 +++ Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicationLi= b.c | 184 +++++ Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.c = | 202 ++++++ Silicon/Ampere/AmpereAltraPkg/Library/PlatformPeiLib/PlatformPeiLib.c = | 40 ++ Silicon/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.c = | 141 ++++ Silicon/Ampere/AmpereAltraPkg/Library/SystemFirmwareInterfaceLib/SystemFir= mwareInterfaceLib.c | 328 +++++++++ Silicon/Ampere/AmpereAltraPkg/Library/TrngLib/TrngLib.c = | 63 ++ Platform/Ampere/AmperePlatformPkg/FvRules.fdf.inc = | 176 +++++ Platform/Ampere/JadePkg/JadeBoardSetting.cfg = | 209 ++++++ Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformHelper.S = | 45 ++ Silicon/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.uni = | 13 + 46 files changed, 6729 insertions(+) diff --git a/Platform/Ampere/AmperePlatformPkg/AmperePlatformPkg.dec b/Plat= form/Ampere/AmperePlatformPkg/AmperePlatformPkg.dec new file mode 100755 index 000000000000..7c1d1f84f780 --- /dev/null +++ b/Platform/Ampere/AmperePlatformPkg/AmperePlatformPkg.dec @@ -0,0 +1,28 @@ +## @file +# +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION =3D 0x0001001B + PACKAGE_NAME =3D AmperePlatformPkg + PACKAGE_GUID =3D 7A78F1B2-E9BE-4F94-891C-385ED524036C + PACKAGE_VERSION =3D 0.1 + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_D= RIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +##########################################################################= ###### +[Includes] + +[LibraryClasses] + +[Guids] diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec b/Silicon/Amp= ere/AmpereAltraPkg/AmpereAltraPkg.dec new file mode 100644 index 000000000000..f0a5bd04ec22 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec @@ -0,0 +1,42 @@ +## @file +# +# Copyright (c) 2020-2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION =3D 0x0001001B + PACKAGE_NAME =3D AmpereAltraPkg + PACKAGE_GUID =3D 481F7D0D-7525-4B76-AF12-58E7B82C46C2 + PACKAGE_VERSION =3D 0.1 + +[Includes] + Include + +[LibraryClasses] + ## @libraryclass Defines a set of methods to retrieve CPU info. + AmpereCpuLib|Silicon/Ampere/AmpereAltraPkg/Include/Library/AmpereCpuLib.= h + + ## @libraryclass Defines a set of methods to get/set NVParam. + NVParamLib|Silicon/Ampere/AmpereAltraPkg/Include/Library/NVParamLib.h + + ## @libraryclass Defines a set of methods to access Mailbox interface. + MailboxInterfaceLib|Silicon/Ampere/AmpereAltraPkg/Include/Library/Mailbo= xInterfaceLib.h + + ## @libraryclass Defines a set of methods to communicate with SCP. + SystemFirmwareInterfaceLib|Silicon/Ampere/AmpereAltraPkg/Include/Library= /SystemFirmwareInterfaceLib.h + + ## @libraryclass Defines a set of methods to communicate with secure p= arition over MM interface. + MmCommunicationLib|Silicon/Ampere/AmpereAltraPkg/Include/Library/MmCommu= nicationLib.h + + ## @libraryclass Defines a set of methods to generate random numbers b= y using Hardware RNG. + TrngLib|Silicon/Ampere/AmpereAltraPkg/Include/Library/TrngLib.h + +[Guids] + ## NVParam MM GUID + gNVParamMmGuid =3D { 0xE4AC5024, 0x29BE, 0x4ADC, { 0x93, 0= x36, 0x87, 0xB5, 0xA0, 0x76, 0x23, 0x2D } } + + ## Include/Guid/PlatformInfoHobGuid.h + gPlatformHobGuid =3D { 0x7f73e372, 0x7183, 0x4022, { 0xb3, 0= x76, 0x78, 0x30, 0x32, 0x6d, 0x79, 0xb4 } } diff --git a/Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec b/Silicon= /Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec new file mode 100755 index 000000000000..6ebdf7db0a57 --- /dev/null +++ b/Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec @@ -0,0 +1,46 @@ +## @file +# +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION =3D 0x0001001B + PACKAGE_NAME =3D AmpereSiliconPkg + PACKAGE_GUID =3D F9EB69A8-7569-4C0E-87D1-3CC9EB7CBF09 + PACKAGE_VERSION =3D 0.1 + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_D= RIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +##########################################################################= ###### +[Includes.common] + +[LibraryClasses] + +[Guids] + gAmpereTokenSpaceGuid =3D { 0xdbd4436e, 0x89cb, 0x44dc, { 0xb5, 0xc0, 0x= 49, 0xc3, 0x91, 0x35, 0xbf, 0xdf } } + +[Ppis] + +[PcdsFixedAtBuild] + # + # SMpro PMpro Pcds + # + gAmpereTokenSpaceGuid.PcdSmproDbBaseReg|0x100000540000|UINT64|0x00000001 + gAmpereTokenSpaceGuid.PcdSmproEfuseShadow0|0x10000054a000|UINT64|0x00000= 002 + gAmpereTokenSpaceGuid.PcdSmproNsMailboxIndex|0x1|UINT32|0x00000003 + gAmpereTokenSpaceGuid.PcdPmproDbBaseReg|0x100001540000|UINT64|0x00000004 + +[PcdsFixedAtBuild, PcdsDynamic, PcdsDynamicEx] + # + # Firmware Volume Pcds + # + gAmpereTokenSpaceGuid.PcdFvBlockSize|0|UINT32|0xB0000001 diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon= /Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc new file mode 100755 index 000000000000..af66c27822a3 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc @@ -0,0 +1,674 @@ +## @file +# +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,B= uildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICA= TION] + GCC:*_*_AARCH64_DLINK_FLAGS =3D -z common-page-size=3D0x1000 + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC:*_*_AARCH64_DLINK_FLAGS =3D -z common-page-size=3D0x10000 + +[BuildOptions] + GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG + +[LibraryClasses.common] +!if $(TARGET) =3D=3D RELEASE + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.in= f +!endif + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf + + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibN= ull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableL= ib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServic= esLib.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + + # + # Allow dynamic PCDs + # + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + + # + # Random Generator Library + # + TrngLib|Silicon/Ampere/AmpereAltraPkg/Library/TrngLib/TrngLib.inf + RngLib|Silicon/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.inf + + # + # ARM Architectural Libraries + # + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMainte= nanceLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/Def= aultExceptionHandlerLib.inf + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.in= f + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.= inf + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatfo= rmStackLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/Ar= mGenericTimerPhyCounterLib.inf + ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSy= stemLib.inf + + # + # Ampere Altra specific Libraries + # + ArmPlatformLib|Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmP= latformLib.inf + PlatformPeiLib|Silicon/Ampere/AmpereAltraPkg/Library/PlatformPeiLib/Plat= formPeiLib.inf + NVParamLib|Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.i= nf + MailboxInterfaceLib|Silicon/Ampere/AmpereAltraPkg/Library/MailboxInterfa= ceLib/MailboxInterfaceLib.inf + SystemFirmwareInterfaceLib|Silicon/Ampere/AmpereAltraPkg/Library/SystemF= irmwareInterfaceLib/SystemFirmwareInterfaceLib.inf + AmpereCpuLib|Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCp= uLib.inf + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf + MmCommunicationLib|Silicon/Ampere/AmpereAltraPkg/Library/MmCommunication= Lib/MmCommunicationLib.inf + + # + # ARM PL011 UART Driver + # + PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf + SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortL= ib.inf + PL011UartClockLib|ArmPlatformPkg/Library/PL011UartClockLib/PL011UartCloc= kLib.inf + + # + # Timer Library + # + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + + # + # Uncomment (and comment out the next line) For RealView Debugger. The S= tandard IO window + # in the debugger will show load and unload commands for symbols. You ca= n cut and paste this + # into the command window to load symbols. We should be able to use a sc= ript to do this, but + # the version of RVD I have does not support scripts accessing system me= mory. + # + #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffEx= traActionLib.inf + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCof= fExtraActionLib.inf + #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePe= CoffExtraActionLibNull.inf + + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf + DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgent= TimerLibNull.inf + + SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf + + # + # BDS Libraries + # + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBoo= tManagerLib.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + + # + # UEFI Shell libraries + # + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib= /BaseOrderedCollectionRedBlackTreeLib.inf + + # + # Secure Boot dependencies + # +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure= mentLib.inf + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + + # + # re-use the UserPhysicalPresent() dummy implementation from the ovmf tr= ee + # + PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.in= f +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLib= Null.inf +!endif + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ib.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Var= iablePolicyHelperLib.inf + + # + # Networking Requirements + # +!if $(NETWORK_TLS_ENABLE) =3D=3D TRUE + TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf +!endif + + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf + + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + +[LibraryClasses.common.SEC] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsB= aseLib.inf + +!ifdef $(EDK2_SKIP_PEICORE) + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib= /PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCusto= mDecompressLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMe= moryAllocationLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/Pre= PiHobListPointerLib.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.= inf +!endif + + ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf + +[LibraryClasses.common.PEI_CORE] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.= inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExt= ractGuidedSectionLib.inf + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + +[LibraryClasses.common.PEIM] + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.= inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiRe= sourcePublicationLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExt= ractGuidedSectionLib.inf + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + +[LibraryClasses.common.SEC, LibraryClasses.common.PEIM] + MemoryInitPeiLib|Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/= MemoryInitPeiLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + +[LibraryClasses.common.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC= oreMemoryAllocationLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerform= anceLib.inf + +[LibraryClasses.common.DXE_DRIVER] + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiTianoCust= omDecompressLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/R= untimeDxeReportStatusCodeLib.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf +!endif +!if $(TARGET) !=3D RELEASE + DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibS= erialPort.inf +!endif + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ibRuntimeDxe.inf + + EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSyste= mLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + +[LibraryClasses.ARM,LibraryClasses.AARCH64] + # + # It is not possible to prevent the ARM compiler for generic intrinsic f= unctions. + # This library provides the instrinsic functions generate by a given com= piler. + # [LibraryClasses.ARM] and NULL mean link this library into all ARM imag= es. + # + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + + # + # Add support for GCC stack protector + # + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### + +[PcdsFeatureFlag.common] + gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|FALSE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|FALSE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE + + # + # Use the Vector Table location in CpuDxe. We will not copy the Vector T= able at PcdCpuVectorBaseAddress + # + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE + + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE + + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + + # + # If TRUE, Graphics Output Protocol will be installed on virtual handle + # created by ConsplitterDxe. It could be set FALSE to save size. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + +[PcdsFixedAtBuild.common] +!ifdef $(FIRMWARE_VER) + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER= )" +!endif + + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + + # DEBUG_ASSERT_ENABLED 0x01 + # DEBUG_PRINT_ENABLED 0x02 + # DEBUG_CODE_ENABLED 0x04 + # CLEAR_MEMORY_ENABLED 0x08 + # ASSERT_BREAKPOINT_ENABLED 0x10 + # ASSERT_DEADLOOP_ENABLED 0x20 +!if $(TARGET) =3D=3D RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F +!endif + + # + # SBSA Watchdog Count + # +!ifndef DISABLE_SBSA_WATCHDOG + gArmPlatformTokenSpaceGuid.PcdWatchdogCount|1 +!endif + + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free (pool) + # DEBUG_PAGE 0x00000020 // Alloc & Free (page) + # DEBUG_INFO 0x00000040 // Informational debug messages + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNP Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // LoadFile + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may + # // significantly impact boot performance + # DEBUG_ERROR 0x80000000 // Error + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|$(DEBUG_PRINT_ERROR_LEV= EL) + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + + # + # Optional feature to help prevent EFI memory map fragments + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob + # Values are in EFI Pages (4K). DXE Core will make sure that + # at least this much of each type of memory can be allocated + # from a single memory range. This way you only end up with + # maximum of two fragements for each type in the memory map + # (the memory used, and the free memory that was prereserved + # but not used). + # + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|65 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 + + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + gArmTokenSpaceGuid.PcdArmPrimaryCore|0x0 + + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 + + # + # Stacks for MPCores in Normal World + # + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x91100000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x20000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000 + + # + # System Memory Base + # + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x90000000 + + # + # UEFI region size + # + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000 + + # + # Ampere Altra Core-Cluster profile + # + gArmPlatformTokenSpaceGuid.PcdCoreCount|80 + gArmPlatformTokenSpaceGuid.PcdClusterCount|40 + + # + # PL011 - Serial Terminal + # Ampere Altra UART0 + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x100002600000 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|32 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 + + gArmPlatformTokenSpaceGuid.PL011UartClkInHz|1843200 + gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x62 + + # + # PL011 - Serial Debug UART + # Ampere Altra UART2 + # + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x100002620000 + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|115200 + + # + # We want to use the Shell Libraries but don't want it to initialise + # automatically. We initialise the libraries when the command is called = by the + # Shell. + # + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE + + # + # ARM SBSA Watchdog + # + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x1000027c0000 + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x1000027d0000 + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|92 + + # + # ARM Generic Interrupt Controller + # + gArmTokenSpaceGuid.PcdGicDistributorBase|0x100100000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x100100140000 + + # + # ARM Architectural Timer Frequency + # + # Set it to 0 so that the code will read frequence from register + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0 + gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000 + + # + # use the TTY terminal type + # + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 + + # + # GUID of the UI app + # + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + + # + # Enable strict image permissions for all images. (This applies + # only to images that were built with >=3D 4 KB section alignment.) + # + gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3 + + # + # Enable NX memory protection for all non-code regions, including OEM an= d OS + # reserved ones, with the exception of LoaderData regions, of which OS l= oaders + # (i.e., GRUB) may assume that its contents are executable. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC0000000= 00007FD1 + + # + # Enable the non-executable DXE stack. (This gets set up by DxeIpl) + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE + + # + # MmCommunication + # + gArmTokenSpaceGuid.PcdMmBufferBase|0x88300000 + gArmTokenSpaceGuid.PcdMmBufferSize|0x100000 + +[PcdsDynamicHii.common.DEFAULT] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|10 + +[PcdsDynamicDefault.common] + # + # Fist DRAM Memory region under 4GB address range + # + gArmTokenSpaceGuid.PcdSystemMemorySize|0x70000000 + + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0 + +##########################################################################= ###### +# +# Component Section - list of all EDK II Component Entries defined by this= Platform +# +##########################################################################= ###### + +[Components.common] + # + # PEI Phase modules + # + ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + ArmPlatformPkg/PlatformPei/PlatformPeim.inf + Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.inf + Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInitPeim.inf + ArmPkg/Drivers/CpuPei/CpuPei.inf + UefiCpuPkg/CpuIoPei/CpuIoPei.inf + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompre= ssLib.inf + } + MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouter= Pei.inf + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf + + # + # DXE Phase modules + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32Gu= idedSectionExtractLib.inf + } + MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCod= eRouterRuntimeDxe.inf + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRun= timeDxe.inf + + # + # PCD + # + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificatio= nLib.inf +!endif + } + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx= e.inf +!endif + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + # + # Environment Variables Protocol + # + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE + + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeas= urementLibNull.inf + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + } + + # + # Timer + # + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + + # + # ARM GIC Dxe + # + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + + # + # Uefi Cpu + # + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + + # + # Console + # + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # + # Simple TextIn/TextOut for UEFI Terminal + # + EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + + # + # Hii Database + # + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # Semi-hosting filesystem + # + ArmPkg/Filesystem/SemihostFs/SemihostFs.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } + + # + # Networking stack + # +!include NetworkPkg/Network.dsc.inc + + # + # UEFI application (Shell Embedded Boot Loader) + # + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewC= ommandLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePar= singLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcf= gCommandLib.inf + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } +!ifdef $(INCLUDE_TFTP_COMMAND) + ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf +!endif #$(INCLUDE_TFTP_COMMAND) diff --git a/Platform/Ampere/JadePkg/Jade.dsc b/Platform/Ampere/JadePkg/Jad= e.dsc new file mode 100755 index 000000000000..f68af24a0d78 --- /dev/null +++ b/Platform/Ampere/JadePkg/Jade.dsc @@ -0,0 +1,100 @@ +## @file +# +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile= . +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D Jade + PLATFORM_GUID =3D 7BDD00C0-68F3-4CC1-8775-F0F00572019F + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001001B + OUTPUT_DIRECTORY =3D Build/Jade + SUPPORTED_ARCHITECTURES =3D AARCH64 + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Platform/Ampere/JadePkg/Jade.fdf + + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=3DVALUE + # + + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free (pool) + # DEBUG_PAGE 0x00000020 // Alloc & Free (page) + # DEBUG_INFO 0x00000040 // Informational debug messages + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNP Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // LoadFile + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may + # // significantly impact boot performance + # DEBUG_ERROR 0x80000000 // Error + DEFINE DEBUG_PRINT_ERROR_LEVEL =3D 0x8000000F + DEFINE FIRMWARE_VER =3D 0.01.001 + DEFINE EDK2_SKIP_PEICORE =3D TRUE + DEFINE SECURE_BOOT_ENABLE =3D FALSE + DEFINE INCLUDE_TFTP_COMMAND =3D TRUE + + # + # Network definition + # + DEFINE NETWORK_IP6_ENABLE =3D FALSE + DEFINE NETWORK_HTTP_BOOT_ENABLE =3D TRUE + DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS =3D TRUE + DEFINE NETWORK_TLS_ENABLE =3D FALSE + +# Include default Ampere Platform DSC file +!include Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc + +##########################################################################= ###### +# +# Specific Platform Library +# +##########################################################################= ###### +[LibraryClasses] + # + # RTC Library: Common RTC + # + RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualReal= TimeClockLib.inf + +##########################################################################= ###### +# +# Specific Platform Pcds +# +##########################################################################= ###### +[PcdsFeatureFlag.common] +[PcdsFixedAtBuild.common] + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + # Override the default values from SecurityPkg to ensure images + # from all sources are verified in secure boot + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0= x04 +!endif + + +##########################################################################= ###### +# +# Specific Platform Component +# +##########################################################################= ###### +[Components.common] diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jad= e.fdf new file mode 100755 index 000000000000..8ed6df381aed --- /dev/null +++ b/Platform/Ampere/JadePkg/Jade.fdf @@ -0,0 +1,225 @@ +## @file +# +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +##########################################################################= ###### + +[FD.BL33_JADE_UEFI] +BaseAddress =3D 0x92000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The ba= se address of the Firmware in NOR Flash. +Size =3D 0x007C0000|gArmTokenSpaceGuid.PcdFdSize # The si= ze in bytes of the FLASH Device +ErasePolarity =3D 1 + +# This one is tricky, it must be: BlockSize * NumBlocks =3D Size +BlockSize =3D 0x10000 +NumBlocks =3D 0x7C + +##########################################################################= ###### +# +# Following are lists of FD Region layout which correspond to the location= s of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" requir= ed) followed by +# the pipe "|" character, followed by the size of the region, also in hex = with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +##########################################################################= ###### + +# +# FV MAIN +# Offset: 0x00000000 +# Size: 0x00740000 +# +0x00000000|0x00740000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV =3D FVMAIN_COMPACT + +# +# NV Variables +# T.B.D +# + +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a flash +# device file. This section also defines order the components and modules= are positioned +# within the image. The [FV] section consists of define statements, set s= tatements and +# module statements. +# +##########################################################################= ###### + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 61C0F511-A691-4F54-974F-B9A42172CE53 + +APRIORI PEI { + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRo= uterPei.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.in= f +} + + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInitPeim.= inf + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRo= uterPei.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.in= f + + # + # Print platform information before passing control into the Driver Exec= ution Environment (DXE) phase + # + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + + FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FVMAIN + } + } + +[FV.FvMain] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 5C60F367-A505-419A-859E-2A4FF6CA6FE5 + +APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatu= sCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandle= rRuntimeDxe.inf +} + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatu= sCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandle= rRuntimeDxe.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConf= igDxe.inf +!endif + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu= ntimeDxe.inf + INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # Environment Variables Protocol + # + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe= .inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # + # Timer + # + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + + # + # ARM GIC Dxe + # + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + + INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf + + # + # UEFI application (Shell Embedded Boot Loader) + # + INF ShellPkg/Application/Shell/Shell.inf +!if $(INCLUDE_TFTP_COMMAND) =3D=3D TRUE + INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf +!endif + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe= .inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + + # + # Networking stack + # +!include NetworkPkg/Network.fdf.inc + +!include Platform/Ampere/AmperePlatformPkg/FvRules.fdf.inc diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.inf= b/Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.inf new file mode 100644 index 000000000000..c1bcdbad9392 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.inf @@ -0,0 +1,41 @@ +## @file +# +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D ATFHobPeim + FILE_GUID =3D B1975734-77C2-4827-9617-914883F3B578 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializeATFHobPeim + +[Sources] + ATFHobPeim.c + +[FixedPcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + HobLib + PcdLib + PeiServicesLib + PeimEntryPoint + +[Guids] + gPlatformHobGuid + +[Depex] + TRUE diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryIni= tPeim.inf b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInit= Peim.inf new file mode 100755 index 000000000000..8d857b9612b4 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInitPeim.i= nf @@ -0,0 +1,64 @@ +## @file +# +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D MemoryInit + FILE_GUID =3D AC939A4D-D185-463F-A0CE-4120BF0ACF79 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializeMemory + +[Sources] + MemoryInitPeim.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec + +[LibraryClasses] + ArmLib + ArmPlatformLib + DebugLib + HobLib + MemoryInitPeiLib + PeimEntryPoint + +[Guids] + gEfiMemoryTypeInformationGuid + gPlatformHobGuid + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob + +[FixedPcd] + gArmTokenSpaceGuid.PcdFdBaseAddress + gArmTokenSpaceGuid.PcdFdSize + + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize + + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData + +[Pcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + +[Depex] + TRUE diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLi= b.inf b/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.inf new file mode 100644 index 000000000000..cb2eeddbb669 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.inf @@ -0,0 +1,44 @@ +## @file +# +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D AmpereCpuLib + FILE_GUID =3D 4ACE898C-4DDC-4EF7-BB6C-91549BDF5B9C + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D CpuLib + +[Sources] + AmpereCpuLib.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec + Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec + +[LibraryClasses] + ArmLib + BaseLib + HobLib + IoLib + NVParamLib + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmPlatformTokenSpaceGuid.PcdClusterCount + + gAmpereTokenSpaceGuid.PcdSmproEfuseShadow0 + + gArmTokenSpaceGuid.PcdSystemMemoryBase + +[Guids] + gPlatformHobGuid diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatfo= rmLib.inf b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatfor= mLib.inf new file mode 100755 index 000000000000..a4d29379198d --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.i= nf @@ -0,0 +1,57 @@ +## @file +# +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D ArmPlatformLib + FILE_GUID =3D 7F829BB1-5092-4D8E-8FB7-2B2C2A80D783 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Sources] + ArmPlatformHelper.S + ArmPlatformLib.c + ArmPlatformLibMemory.c + +[LibraryClasses] + AmpereCpuLib + ArmLib + ArmSmcLib + HobLib + IoLib + MemoryAllocationLib + PL011UartLib + PcdLib + SerialPortLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec + Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec + +[Pcd] + gArmTokenSpaceGuid.PcdMmBufferBase + gArmTokenSpaceGuid.PcdMmBufferSize + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdClusterCount + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmPlatformTokenSpaceGuid.PL011UartClkInHz + + gArmTokenSpaceGuid.PcdArmPrimaryCore + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/MailboxInterfaceLib/Mail= boxInterfaceLib.inf b/Silicon/Ampere/AmpereAltraPkg/Library/MailboxInterfac= eLib/MailboxInterfaceLib.inf new file mode 100644 index 000000000000..de07a573b62b --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/MailboxInterfaceLib/MailboxInte= rfaceLib.inf @@ -0,0 +1,37 @@ +## @file +# The library implements the hardware Mailbox (Doorbell) interface for co= mmunication +# between the Application Processor (ARMv8) and the System Control Proces= sors (SMpro/PMpro). +# +# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D MailboxInterface + FILE_GUID =3D EE482BD0-A91A-45BE-83B1-2157A0FB94C3 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D MailboxInterfaceLib + +[Sources] + MailboxInterfaceLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec + Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec + +[LibraryClasses] + AmpereCpuLib + BaseLib + BaseMemoryLib + DebugLib + IoLib + TimerLib + +[FixedPcd] + gAmpereTokenSpaceGuid.PcdSmproDbBaseReg + gAmpereTokenSpaceGuid.PcdPmproDbBaseReg diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryI= nitPeiLib.inf b/Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/Memo= ryInitPeiLib.inf new file mode 100755 index 000000000000..b6dc7d2ec04a --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiL= ib.inf @@ -0,0 +1,63 @@ +## @file +# +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D ArmMemoryInitPeiLib + FILE_GUID =3D 55DDB6E0-70B5-11E0-B33E-0002A5D5C51B + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D MemoryInitPeiLib + +[Sources] + MemoryInitPeiLib.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec + Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec + +[LibraryClasses] + ArmLib + ArmMmuLib + ArmPlatformLib + DebugLib + HobLib + +[Guids] + gEfiMemoryTypeInformationGuid + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob + +[FixedPcd] + gArmTokenSpaceGuid.PcdFdBaseAddress + gArmTokenSpaceGuid.PcdFdSize + + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize + + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData + +[Pcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + +[Depex] + TRUE diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCom= municationLib.inf b/Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLi= b/MmCommunicationLib.inf new file mode 100755 index 000000000000..1693fa7e8050 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicat= ionLib.inf @@ -0,0 +1,35 @@ +## @file +# +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D MmCommunicationLib + FILE_GUID =3D 106099B8-0051-4B35-9578-EFB1045D2FA8 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D MmCommunicationLib + CONSTRUCTOR =3D MmCommunicationLibConstructor + +[Sources] + MmCommunicationLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec + +[LibraryClasses] + ArmLib + ArmSmcLib + BaseMemoryLib + DebugLib + PcdLib + +[Pcd] + gArmTokenSpaceGuid.PcdMmBufferBase + gArmTokenSpaceGuid.PcdMmBufferSize diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.in= f b/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.inf new file mode 100755 index 000000000000..2d506913f733 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.inf @@ -0,0 +1,32 @@ +## @file +# +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D NVParamLib + FILE_GUID =3D 8512FF56-11DF-4A16-A0CF-81B27DBD23FB + MODULE_TYPE =3D BASE + VERSION_STRING =3D 0.1 + LIBRARY_CLASS =3D NVParamLib + +[Sources.common] + NVParamLib.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + MmCommunicationLib + +[Guids] + gNVParamMmGuid diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/PlatformPeiLib/PlatformP= eiLib.inf b/Silicon/Ampere/AmpereAltraPkg/Library/PlatformPeiLib/PlatformPe= iLib.inf new file mode 100644 index 000000000000..524b3fe777b8 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/PlatformPeiLib/PlatformPeiLib.i= nf @@ -0,0 +1,42 @@ +## @file +# +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D ArmPlatformPeiLib + FILE_GUID =3D 49D37060-70B5-11E0-AA2D-0002A5D5C51B + MODULE_TYPE =3D SEC + VERSION_STRING =3D 0.1 + LIBRARY_CLASS =3D PlatformPeiLib + +[Sources] + PlatformPeiLib.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec + Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec + +[LibraryClasses] + ArmLib + ArmPlatformLib + ArmSmcLib + DebugLib + HobLib + PcdLib + PeiServicesLib + +[FixedPcd] + gArmTokenSpaceGuid.PcdFvBaseAddress + gArmTokenSpaceGuid.PcdFvSize + +[Depex] + TRUE diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.inf b/Sili= con/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.inf new file mode 100644 index 000000000000..5b25a64d5451 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.inf @@ -0,0 +1,29 @@ +## @file +# Instance of RNG (Random Number Generator) Library. +# +# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D RngLib + MODULE_UNI_FILE =3D RngLib.uni + FILE_GUID =3D 9CC35499-5CC8-49A2-8C27-AE7B3B83D149 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RngLib + +[Sources] + RngLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + TrngLib diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/SystemFirmwareInterfaceL= ib/SystemFirmwareInterfaceLib.inf b/Silicon/Ampere/AmpereAltraPkg/Library/S= ystemFirmwareInterfaceLib/SystemFirmwareInterfaceLib.inf new file mode 100644 index 000000000000..f11291003dde --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/SystemFirmwareInterfaceLib/Syst= emFirmwareInterfaceLib.inf @@ -0,0 +1,30 @@ +## @file +# Provides functions for communication with System Firmware (SMpro/PMpro) +# via interfaces like Mailbox. +# +# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D SystemFirmwareInterface + FILE_GUID =3D 8574F1CC-BF8C-46FD-9276-5B202E2A425C + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SystemFirmwareInterfaceLib + +[Sources] + SystemFirmwareInterfaceLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + MailboxInterfaceLib diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/TrngLib/TrngLib.inf b/Si= licon/Ampere/AmpereAltraPkg/Library/TrngLib/TrngLib.inf new file mode 100644 index 000000000000..aac835ed46ed --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/TrngLib/TrngLib.inf @@ -0,0 +1,29 @@ +## @file +# Instance of RNG (Random Number Generator) Library. +# +# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D Trng + FILE_GUID =3D 30200949-29CF-4BDB-8300-EFFC44D03603 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D TrngLib + +[Sources] + TrngLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + SystemFirmwareInterfaceLib diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/PlatformInfoHobGuid= .h b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/PlatformInfoHobGuid.h new file mode 100755 index 000000000000..5b199bf2b4e8 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/PlatformInfoHobGuid.h @@ -0,0 +1,17 @@ +/** @file + + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PLATFORM_INFO_HOB_GUID_H_ +#define PLATFORM_INFO_HOB_GUID_H_ + +#define PLATFORM_INFO_HOB_GUID \ + { 0x7f73e372, 0x7183, 0x4022, { 0xb3, 0x76, 0x78, 0x30, 0x32, 0x6d, 0x79= , 0xb4 } } + +extern EFI_GUID gPlatformHobGuid; + +#endif /* PLATFORM_INFO_HOB_GUID_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/AmpereCpuLib.h b= /Silicon/Ampere/AmpereAltraPkg/Include/Library/AmpereCpuLib.h new file mode 100644 index 000000000000..de576474fb48 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/AmpereCpuLib.h @@ -0,0 +1,282 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef AMPERE_CPU_LIB_H_ +#define AMPERE_CPU_LIB_H_ + +/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n =3D 1 to 7 */ +#define CLIDR_CTYPE_SHIFT(Level) (3 * (Level - 1)) +#define CLIDR_CTYPE_MASK(Level) (7 << CLIDR_CTYPE_SHIFT(Level)) +#define CLIDR_CTYPE(Clidr, Level) \ + (((Clidr) & CLIDR_CTYPE_MASK(Level)) >> CLIDR_CTYPE_SHIFT(Level)) + +#define CCSIDR_NUMSETS_SHIFT 13 +#define CCSIDR_NUMSETS_MASK 0xFFFE000 +#define CCSIDR_NUMSETS(Ccsidr) \ + (((Ccsidr) & CCSIDR_NUMSETS_MASK) >> CCSIDR_NUMSETS_SHIFT) +#define CCSIDR_ASSOCIATIVITY_SHIFT 3 +#define CCSIDR_ASSOCIATIVITY_MASK 0x1FF8 +#define CCSIDR_ASSOCIATIVITY(Ccsidr) \ + (((Ccsidr) & CCSIDR_ASSOCIATIVITY_MASK) >> CCSIDR_ASSOCIATIVITY_SHIFT) +#define CCSIDR_LINE_SIZE_SHIFT 0 +#define CCSIDR_LINE_SIZE_MASK 0x7 +#define CCSIDR_LINE_SIZE(Ccsidr) \ + (((Ccsidr) & CCSIDR_LINE_SIZE_MASK) >> CCSIDR_LINE_SIZE_SHIFT) + +#define SUBNUMA_MODE_MONOLITHIC 0 +#define SUBNUMA_MODE_HEMISPHERE 1 +#define SUBNUMA_MODE_QUADRANT 2 + +#define MONOLITIC_NUM_OF_REGION 1 +#define HEMISPHERE_NUM_OF_REGION 2 +#define QUADRANT_NUM_OF_REGION 4 +#define SUBNUMA_CPM_REGION_SIZE 4 +#define NUM_OF_CPM_PER_MESH_ROW 8 + +#define CPM_PER_ROW_OFFSET(CpmId) ((CpmId) % NUM_OF_CPM_PER_MESH_ROW) +#define CPM_ROW_NUMBER(CpmId) ((CpmId) / NUM_OF_CPM_PER_MESH_ROW) + +#define SOCKET_ID(CpuId) ((CpuId) / (PLATFORM_CPU_MAX_CPM * = PLATFORM_CPU_NUM_CORES_PER_CPM)) +#define CLUSTER_ID(CpuId) (((CpuId) / PLATFORM_CPU_NUM_CORES_= PER_CPM) % PLATFORM_CPU_MAX_CPM) + + +/** + Get the SubNUMA mode. + + @return UINT8 The SubNUMA mode. + +**/ +UINT8 +EFIAPI +CpuGetSubNumaMode ( + VOID + ); + +/** + Get the number of SubNUMA region. + + @return UINT8 The number of SubNUMA region. + +**/ +UINT8 +EFIAPI +CpuGetNumberOfSubNumaRegion ( + VOID + ); + +/** + Get the SubNUMA node of a CPM. + + @param SocketId Socket index. + @param Cpm CPM index. + @return UINT8 The SubNUMA node of a CPM. + +**/ +UINT8 +EFIAPI +CpuGetSubNumNode ( + UINT8 Socket, + UINT16 Cpm + ); + +/** + Get the associativity of cache. + + @param Level Cache level. + @return UINT32 Associativity of cache. + +**/ +UINT32 +EFIAPI +CpuGetAssociativity ( + UINT32 Level + ); + +/** + Get the cache size. + + @param Level Cache level. + @return UINT32 Cache size. + +**/ +UINT32 +EFIAPI +CpuGetCacheSize ( + UINT32 Level + ); + +/** + Get the number of supported socket. + + @return UINT8 Number of supported socket. + +**/ +UINT8 +EFIAPI +GetNumberOfSupportedSockets ( + VOID + ); + +/** + Get the number of active socket. + + @return UINT8 Number of active socket. + +**/ +UINT8 +EFIAPI +GetNumberOfActiveSockets ( + VOID + ); + +/** + Get the number of active CPM per socket. + + @param SocketId Socket index. + @return UINT16 Number of CPM. + +**/ +UINT16 +EFIAPI +GetNumberOfActiveCPMsPerSocket ( + UINT8 SocketId + ); + +/** + Get the number of configured CPM per socket. + + @param SocketId Socket index. + @return UINT16 Number of configured CPM. + +**/ +UINT16 +EFIAPI +GetNumberOfConfiguredCPMs ( + UINT8 SocketId + ); + +/** + Set the number of configured CPM per socket. + + @param SocketId Socket index. + @param NumberOfCPMs Number of CPM to be configured. + @return EFI_SUCCESS Operation succeeded. + @return Others An error has occurred. + +**/ +EFI_STATUS +EFIAPI +SetNumberOfConfiguredCPMs ( + UINT8 SocketId, + UINT16 NumberOfCPMs + ); + +/** + Get the maximum number of core per socket. This number + should be the same for all sockets. + + @return UINT16 Maximum number of core. + +**/ +UINT16 +EFIAPI +GetMaximumNumberOfCores ( + VOID + ); + +/** + Get the maximum number of CPM per socket. This number + should be the same for all sockets. + + @return UINT32 Maximum number of CPM. + +**/ +UINT16 +EFIAPI +GetMaximumNumberOfCPMs ( + VOID + ); + +/** + Get the number of active cores of a sockets. + + @return UINT16 Number of active core. + +**/ +UINT16 +EFIAPI +GetNumberOfActiveCoresPerSocket ( + UINT8 SocketId + ); + +/** + Get the number of active cores of all socket. + + @return UINT16 Number of active core. + +**/ +UINT16 +EFIAPI +GetNumberOfActiveCores ( + VOID + ); + +/** + Check if the logical CPU is enabled or not. + + @param CpuId The logical Cpu ID. Started from 0. + @return BOOLEAN TRUE if the Cpu enabled + FALSE if the Cpu disabled. + +**/ +BOOLEAN +EFIAPI +IsCpuEnabled ( + UINT16 CpuId + ); + + +/** + Check if the slave socket is present + + @return BOOLEAN TRUE if the Slave Cpu is present + FALSE if the Slave Cpu is not present + +**/ +BOOLEAN +EFIAPI +IsSlaveSocketPresent ( + VOID + ); + +/** + Check if the slave socket is active + + @return BOOLEAN TRUE if the Slave CPU Socket is active. + FALSE if the Slave CPU Socket is not active. + +**/ +BOOLEAN +EFIAPI +IsSlaveSocketActive ( + VOID + ); + +/** + Check if the CPU product ID is Ac01 + @return BOOLEAN TRUE if the Product ID is Ac01 + FALSE otherwise. + +**/ +BOOLEAN +EFIAPI +IsAc01Processor ( + VOID + ); + +#endif /* AMPERE_CPU_LIB_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/MailboxInterface= Lib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/MailboxInterfaceLib.h new file mode 100644 index 000000000000..2750487f3e96 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/MailboxInterfaceLib.h @@ -0,0 +1,172 @@ +/** @file + The library implements the hardware Mailbox (Doorbell) interface for com= munication + between the Application Processor (ARMv8) and the System Control Process= ors (SMpro/PMpro). + + A transfer to SMpro/PMpro is performed on a doorbell channel which is im= plemented through + hardware doorbell registers. Each transfer can be up to 12 bytes long, i= ncluding 4 bytes + for the message and two 4 bytes for additional data. + + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef MAILBOX_INTERFACE_LIB_H_ +#define MAILBOX_INTERFACE_LIB_H_ + +#define SMPRO_DB_MAX 8 +#define PMPRO_DB_MAX 8 +#define NUMBER_OF_DOORBELLS_PER_SOCKET (SMPRO_DB_MAX + PMPRO_DB_MAX) + +// +// General address offset of Doorbell registers +// +#define DB_IN_REG_OFST 0x00000000 // Doorbell In +#define DB_DIN0_REG_OFST 0x00000004 // Doorbell In Data +#define DB_DIN1_REG_OFST 0x00000008 // Doorbell In Data +#define DB_OUT_REG_OFST 0x00000010 // Doorbell Out +#define DB_DOUT0_REG_OFST 0x00000014 // Doorbell Out Data +#define DB_DOUT1_REG_OFST 0x00000018 // Doorbell Out Data +#define DB_STATUS_REG_OFST 0x00000020 // Doorbell Interrupt Status +#define DB_STATUS_MASK_REG_OFST 0x00000024 // Doorbell Interrupt Status = Mask + +// +// List of supported doorbells +// +typedef enum { + // + // PMpro Doorbells + // + PMproDoorbellChannel0 =3D 0, + PMproDoorbellChannel1, + PMproDoorbellChannel2, + PMproDoorbellChannel3, + PMproDoorbellChannel4, + PMproDoorbellChannel5, + PMproDoorbellChannel6, + PMproDoorbellChannel7, + // + // SMpro Doorbells + // + SMproDoorbellChannel0 =3D PMPRO_DB_MAX, + SMproDoorbellChannel1, + SMproDoorbellChannel2, + SMproDoorbellChannel3, + SMproDoorbellChannel4, + SMproDoorbellChannel5, + SMproDoorbellChannel6, + SMproDoorbellChannel7 +} DOORBELL_CHANNELS; + +#pragma pack(1) +// +// Mailbox Message Data +// +// A mailbox transaction supports up to 12 bytes long, +// including 4 bytes for message and two 4 bytes for extended data. +// +typedef struct { + UINT32 Data; + UINT32 ExtendedData[2]; +} MAILBOX_MESSAGE_DATA; + +#pragma pack() + +// +// Timeout configuration when waiting for an doorbell interrupt status +// +#define MAILBOX_POLL_TIMEOUT_US 10000000 +#define MAILBOX_POLL_INTERVAL_US 1000 +#define MAILBOX_POLL_COUNT (MAILBOX_POLL_TIMEOUT_US / MAILBOX_POLL_I= NTERVAL_US) + +/** + Get the base address of a doorbell. + + @param[in] Socket Active socket index. + @param[in] Doorbell Doorbell channel for communication with th= e SMpro/PMpro. + + @retval UINT32 The base address of the doorbell. + The returned value is 0 indicate that the = input parameters are invalid. + +**/ +UINTN +EFIAPI +MailboxGetDoorbellAddress ( + IN UINT8 Socket, + IN DOORBELL_CHANNELS Doorbell + ); + +/** + Get the interrupt number of a doorbell. + + @param[in] Socket Active socket index. + @param[in] Doorbell Doorbell channel for communication with th= e SMpro/PMpro. + + @retval UINT32 The interrupt number. + The returned value is 0 indicate that the = input parameters are invalid. + +**/ +UINT32 +EFIAPI +MailboxGetDoorbellInterruptNumber ( + IN UINT8 Socket, + IN DOORBELL_CHANNELS Doorbell + ); + +/** + Read a message via the hardware Doorbell interface. + + @param[in] Socket Active socket index. + @param[in] Doorbell Doorbell channel for communication with th= e SMpro/PMpro. + @param[out] Message Pointer to the Mailbox message. + + @retval EFI_SUCCESS Read the message successfully. + @retval EFI_TIMEOUT Timeout occurred when waiting for availabl= e message in the mailbox. + @retval EFI_INVALID_PARAMETER A parameter is invalid. +**/ +EFI_STATUS +EFIAPI +MailboxRead ( + IN UINT8 Socket, + IN DOORBELL_CHANNELS Doorbell, + OUT MAILBOX_MESSAGE_DATA *Message + ); + +/** + Write a message via the hardware Doorbell interface. + + @param[in] Socket Active socket index. + @param[in] Doorbell Doorbel channel for communication with the= SMpro/PMpro. + @param[in] Message Pointer to the Mailbox message. + + @retval EFI_SUCCESS Write the message successfully. + @retval EFI_TIMEOUT Timeout occurred when waiting for acknowle= dge signal from the mailbox. + @retval EFI_INVALID_PARAMETER A parameter is invalid. +**/ +EFI_STATUS +EFIAPI +MailboxWrite ( + IN UINT8 Socket, + IN DOORBELL_CHANNELS Doorbell, + IN MAILBOX_MESSAGE_DATA *Message + ); + +/** + Unmask the Doorbell interrupt status. + + @param Socket Active socket index. + @param Doorbell Doorbel channel for communication with the SMpro/PMpro= . + + @retval EFI_SUCCESS Unmask the Doorbell interrupt successfull= y. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + +**/ +EFI_STATUS +EFIAPI +MailboxUnmaskInterrupt ( + IN UINT8 Socket, + IN UINT16 Doorbell + ); + +#endif /* MAILBOX_INTERFACE_LIB_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/MmCommunicationL= ib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/MmCommunicationLib.h new file mode 100644 index 000000000000..9bae501b3382 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/MmCommunicationLib.h @@ -0,0 +1,19 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef MM_COMMUNICATION_LIB_H_ +#define MM_COMMUNICATION_LIB_H_ + +EFI_STATUS +EFIAPI +MmCommunicationCommunicate ( + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommSize OPTIONAL + ); + +#endif /* MM_COMMUNICATION_LIB_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/NVParamLib.h b/S= ilicon/Ampere/AmpereAltraPkg/Include/Library/NVParamLib.h new file mode 100644 index 000000000000..d0c2a6e3bffa --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/NVParamLib.h @@ -0,0 +1,133 @@ +/** @file + + The non-volatile parameter layout in SPI-NOR is shown below. There is + two copies. The master copy is changeable by the user. The Last Known + copy is handled by the fail safe future. It is a last know bootable copy= . + + --------------------------- + | Master Copy | 16KB + | Pre-boot parameters | + --------------------------- + | Master Copy | 16KB + | Pre-boot parameters | + | w/o failsafe support | + --------------------------- + | Master Copy | + | Manufactory & | 32KB + | Users parameters | + --------------------------- + | Last Known Copy | 16KB + | Pre-boot parameters | + --------------------------- + | | 16KB + --------------------------- + | Last Known Copy | + | Manufactory & | 32KB + | Users parameters | + --------------------------- + + As each non-volatile parameter requires 8 bytes, there is a total of 8K + parameters. + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef NV_PARAM_LIB_H_ +#define NV_PARAM_LIB_H_ + +#define NV_PARAM_MAX_SIZE (64 * 1024) +#define NV_PARAM_ENTRYSIZE 8 + +#define NV_PERM_ALL 0xFFFF /* Allowed for all */ +#define NV_PERM_ATF 0x0001 /* Allowed for EL3 code */ +#define NV_PERM_OPTEE 0x0004 /* Allowed for secure El1 */ +#define NV_PERM_BIOS 0x0008 /* Allowed for EL2 non-secure */ +#define NV_PERM_MANU 0x0010 /* Allowed for manufactory interface */ +#define NV_PERM_BMC 0x0020 /* Allowed for BMC interface */ + +#define NVPARAM_SIZE 0x8 + +/* + * Retrieve a non-volatile parameter + * + * @param: Parameter ID to retrieve + * @acl_rd: Permission for read operation. See NV_PERM_XXX. + * @val: Pointer to an UINT32 to store the value + * @return: EFI_INVALID_PARAMETER if parameter is invalid + * EFI_NOT_FOUND if value is not set + * EFI_UNSUPPORTED if service unavailable + * EFI_ACCESS_DENIED if permission not allowed + * Otherwise, 0 for success + * + * NOTE: If you need a signed value, cast it. It is expected that the + * caller will carry the correct permission over various call sequences. + * + */ +EFI_STATUS +NVParamGet ( + IN UINT32 Param, + IN UINT16 ACLRd, + OUT UINT32 *Val + ); + +/* + * Set a non-volatile parameter + * + * @param: Parameter ID to set + * @acl_rd: Permission for read operation + * @acl_wr: Permission for write operation + * @val: Unsigned int value to set. + * @return: EFI_INVALID_PARAMETER if parameter is invalid + * EFI_UNSUPPORTED if service unavailable + * EFI_ACCESS_DENIED if permission not allowed + * Otherwise, 0 for success + * + * NOTE: If you have a signed value, cast to unsigned. If the parameter ha= s + * not being created before, the provied permission is used to create the + * parameter. Otherwise, it is checked for access. It is expected that the + * caller will carry the correct permission over various call sequences. + * + */ +EFI_STATUS +NVParamSet ( + IN UINT32 Param, + IN UINT16 ACLRd, + IN UINT16 ACLWr, + IN UINT32 Val + ); + +/* + * Clear a non-volatile parameter + * + * @param: Parameter ID to set + * @acl_wr: Permission for write operation + * @return: EFI_INVALID_PARAMETER if parameter is invalid + * EFI_UNSUPPORTED if service unavailable + * EFI_ACCESS_DENIED if permission not allowed + * Otherwise, 0 for success + * + * NOTE: It is expected that the caller will carry the correct permission + * over various call sequences. + * + */ +EFI_STATUS +NVParamClr ( + IN UINT32 Param, + IN UINT16 ACLWr + ); + +/* + * Clear all non-volatile parameters + * + * @return: EFI_UNSUPPORTED if service unavailable + * Otherwise, 0 for success + */ +EFI_STATUS +NVParamClrAll ( + VOID + ); + +#endif /* NV_PARAM_LIB_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/SystemFirmwareIn= terfaceLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/SystemFirmware= InterfaceLib.h new file mode 100644 index 000000000000..ce96c2a6b4b6 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/SystemFirmwareInterface= Lib.h @@ -0,0 +1,282 @@ +/** @file + Provides functions for communication with System Firmware (SMpro/PMpro) + via interfaces like Mailbox. + + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SYSTEM_FIRMWARE_INTERFACE_LIB_H_ +#define SYSTEM_FIRMWARE_INTERFACE_LIB_H_ + +// +// Common mailbox message format +// Bit 31:28 - Message type +// Bit 27:24 - Message subtype +// Bit 23:16 - Message control byte +// Bit 15:0 - Message data specific +// +#define MAILBOX_MESSAGE_TYPE_SHIFT 28 +#define MAILBOX_MESSAGE_SUBTYPE_SHIFT 24 +#define MAILBOX_MESSAGE_CONTROL_BYTE_SHIFT 16 + +#define COMMON_MESSAGE_ENCODE(Type,Subtype,Control) \ + ( \ + ((Type) << MAILBOX_MESSAGE_TYPE_SHIFT) | \ + ((Subtype) << MAILBOX_MESSAGE_SUBTYPE_SHIFT) | \ + ((Control) << MAILBOX_MESSAGE_CONTROL_BYTE_SHIFT) \ + ) + +#define MAILBOX_MESSAGE_CONTROL_URGENT BIT7 +#define MAILBOX_MESSAGE_CONTROL_TYPICAL 0 + +// +// Mailbox Message Types +// +#define MAILBOX_MESSAGE_TYPE_DEBUG 0x00 +#define MAILBOX_MESSAGE_TYPE_ADDRESS 0x05 +#define MAILBOX_MESSAGE_TYPE_USER 0x06 + +// +// Mailbox Message Type 0x00 - Debug message +// +#define MAILBOX_DEBUG_MESSAGE_SUBTYPE_REGISTER_READ 0x01 +#define MAILBOX_DEBUG_MESSAGE_SUBTYPE_REGISTER_WRITE 0x02 + +// +// Debug message data format +// Bit 31:16 - Refer to definition of COMMON_MESSAGE_ENCODE +// Bit 15:0 - Store lower 16-bit of the upper 64-bit address +// +#define MAILBOX_DEBUG_MESSAGE_ENCODE(Subtype,Address) \ + ( \ + (COMMON_MESSAGE_ENCODE ( \ + MAILBOX_MESSAGE_TYPE_DEBUG, \ + (Subtype), \ + MAILBOX_MESSAGE_CONTROL_TYPICAL)) | \ + ((Address) & 0xFFFF) \ + ) + +// +// Mailbox Message Type 0x05 - Address message +// +#define MAILBOX_ADDRESS_MESSAGE_SUBTYPE_PCC 0x03 + +// +// Address message data format +// Bit 31:16 - Refer to definition of COMMON_MESSAGE_ENCODE +// Bit 15:8 - Message Parameter +// Bit 7:4 - Address message control bit +// 0x4: 256 alignment +// 0x0: No alignment +// Bit 3:0 - Unused +// +#define MAILBOX_ADDRESS_MESSAGE_ENCODE(Subtype,Param,Align) \ + ( \ + (COMMON_MESSAGE_ENCODE ( \ + MAILBOX_MESSAGE_TYPE_ADDRESS, \ + (Subtype), \ + MAILBOX_MESSAGE_CONTROL_TYPICAL)) | \ + ((Param) << 8) | \ + ((Align) << 4) \ + ) + +#define MAILBOX_ADDRESS_URGENT_MESSAGE_ENCODE(Subtype,Param,Align) \ + ( \ + (COMMON_MESSAGE_ENCODE ( \ + MAILBOX_MESSAGE_TYPE_ADDRESS, \ + (Subtype), \ + MAILBOX_MESSAGE_CONTROL_URGENT)) | \ + ((Param) << 8) | \ + ((Align) << 4) \ + ) + +#define MAILBOX_ADDRESS_256_ALIGNMENT 0x4 +#define MAILBOX_ADDRESS_NO_ALIGNMENT 0x0 + +#define MAILBOX_ADDRESS_MESSAGE_PARAM_CPPC 0x01 + +#define MAILBOX_URGENT_CPPC_MESSAGE \ + ( \ + MAILBOX_ADDRESS_URGENT_MESSAGE_ENCODE ( \ + MAILBOX_ADDRESS_MESSAGE_SUBTYPE_PCC, \ + MAILBOX_ADDRESS_MESSAGE_PARAM_CPPC, \ + MAILBOX_ADDRESS_256_ALIGNMENT) \ + ) + +#define MAILBOX_TYPICAL_PCC_MESSAGE \ + ( \ + MAILBOX_ADDRESS_MESSAGE_ENCODE ( \ + MAILBOX_ADDRESS_MESSAGE_SUBTYPE_PCC, \ + 0, \ + MAILBOX_ADDRESS_256_ALIGNMENT) \ + ) + +// +// Mailbox Message Type 0x06 - User message +// +#define MAILBOX_USER_MESSAGE_SUBTYPE_SET_CONFIGURATION 0x02 +#define MAILBOX_USER_MESSAGE_SUBTYPE_BOOT_PROGRESS 0x06 +#define MAILBOX_USER_MESSAGE_SUBTYPE_TRNG_PROXY 0x07 + +// +// User message data format +// Bit 31:16 - Refer to definition of COMMON_MESSAGE_ENCODE +// Bit 15:8 - Message Parameter 0 +// Bit 7:0 - Message Parameter 1 +// +#define MAILBOX_USER_MESSAGE_ENCODE(Subtype,Param0,Param1) \ + ( \ + (COMMON_MESSAGE_ENCODE ( \ + MAILBOX_MESSAGE_TYPE_USER, \ + (Subtype), \ + MAILBOX_MESSAGE_CONTROL_TYPICAL)) | \ + ((Param0) << 8) | \ + (Param1) \ + ) + +// +// Parameters for True RNG Proxy Message +// Param0: 1 - Get a random number +// Param1: Unused +// +#define MAILBOX_TRNG_PROXY_GET_RANDOM_NUMBER 1 + +// +// Parameters for Boot Progress +// Param0: 1 - Set boot state +// Param1: Boot stage value +// 0x08: BL33/UEFI Stage +// +#define MAILBOX_BOOT_PROGRESS_COMMAND_SET 1 +#define MAILBOX_BOOT_PROGRESS_STAGE_UEFI 8 + +// +// Parameters for Set Configuration +// Param0: Configuration type +// 20: Turbo configuration +// Param1: Unused +// +#define MAILBOX_SET_CONFIGURATION_TURBO 20 + +/** + Read a register which is not accessible from the non-secure world + by sending a mailbox message to the SMpro processor. + + Note that not all addresses are allowed. + + @param[in] Socket Active socket index. + @param[in] Address A 64-bit register address to be read. + @param[out] Value A pointer to the read value. + + @retval EFI_SUCCESS Read the register successfully. + @retval EFI_UNSUPPORTED The register is not allowed. + @retval Otherwise Errors returned from MailboxWrite/MailboxR= ead() functions. +**/ +EFI_STATUS +EFIAPI +MailboxMsgRegisterRead ( + IN UINT8 Socket, + IN UINTN Address, + OUT UINT32 *Value + ); + +/** + Write a value to a register which is not accessible from the non-secure = world + by sending a mailbox message to the SMpro processor. + + Note that not all addresses are allowed. + + @param[in] Socket Active socket index. + @param[in] Address A 64-bit register address to be written. + @param[in] Value The value to be written to the register. + + @retval EFI_SUCCESS Write the register successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval Otherwise Errors returned from the MailboxWrite() functio= n. +**/ +EFI_STATUS +EFIAPI +MailboxMsgRegisterWrite ( + IN UINT8 Socket, + IN UINTN Address, + IN UINT32 Value + ); + +/** + Set the PCC shared Memory Address to service handlers in the System Cont= rol Processors, + using for communication between the System Firmware and OSPM. + + @param[in] Socket Active socket index. + @param[in] Doorbell Doorbell index which is numbered like DOORB= ELL_CHANNELS. + @param[in] AddressAlign256 Enable/Disable 256 alignment. + @param[in] Address The shared memory address. + + @retval EFI_SUCCESS Set the shared memory address successfully= . + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval Otherwise Errors returned from the MailboxWrite() fu= nctions. +**/ +EFI_STATUS +EFIAPI +MailboxMsgSetPccSharedMem ( + IN UINT8 Socket, + IN UINT8 Doorbell, + IN BOOLEAN AddressAlign256, + IN UINTN Address + ); + +/** + The True RNG is provided by the SMpro processor. This function is to sen= d a mailbox + message to the SMpro to request a 64-bit random number. + + @param[out] Buffer A pointer to the read 64-bit random number= . + + @retval EFI_SUCCESS The operation succeeds. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval Otherwise Errors returned from the MailboxWrite/Mail= boxRead() functions. +**/ +EFI_STATUS +EFIAPI +MailboxMsgGetRandomNumber64 ( + OUT UINT8 *Buffer + ); + +/** + Report the UEFI boot progress to the SMpro. + + @param[in] Socket Active socket index. + @param[in] BootStatus The status of the UEFI boot. + @param[in] Checkpoint The UEFI Checkpoint value. + + @retval EFI_SUCCESS Set the boot progress successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval Otherwise Errors returned from the MailboxWrite() fu= nctions. +**/ +EFI_STATUS +EFIAPI +MailboxMsgSetBootProgress ( + IN UINT8 Socket, + IN UINT8 BootStatus, + IN UINT32 Checkpoint + ); + +/** + Configure the Turbo (Max Performance) mode. + + @param[in] Socket Active socket index. + @param[in] Enable Enable/Disable the Turbo (Max performance) = mode. + + @retval EFI_SUCCESS Configure the Turbo successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval Otherwise Errors returned from the MailboxWrite() fu= nctions. +**/ +EFI_STATUS +EFIAPI +MailboxMsgTurboConfig ( + IN UINT8 Socket, + IN BOOLEAN Enable + ); + +#endif /* SYSTEM_FIRMWARE_INTERFACE_LIB_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/TrngLib.h b/Sili= con/Ampere/AmpereAltraPkg/Include/Library/TrngLib.h new file mode 100644 index 000000000000..b478986cb032 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/TrngLib.h @@ -0,0 +1,31 @@ +/** @file + RNG (Random Number Generator) Library that uses Hardware RNG in SMpro. + + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef TRNG_LIB_H_ +#define TRNG_LIB_H_ + +/** + Generates a random number by using Hardware RNG in SMpro. + + @param[out] Buffer Buffer to receive the random number. + @param[in] BufferSize Number of bytes in Buffer. + + @retval EFI_SUCCESS The random value was returned successfully= . + @retval EFI_DEVICE_ERROR A random value could not be retrieved + due to a hardware or firmware error. + @retval EFI_INVALID_PARAMETER Buffer is NULL or BufferSize is zero. +**/ +EFI_STATUS +EFIAPI +GenerateRandomNumbers ( + OUT UINT8 *Buffer, + IN UINTN BufferSize + ); + +#endif /* TRNG_LIB_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/MmLib.h b/Silicon/Ampere= /AmpereAltraPkg/Include/MmLib.h new file mode 100644 index 000000000000..e348b71b5e58 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/MmLib.h @@ -0,0 +1,79 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef MM_LIB_H_ +#define MM_LIB_H_ + +enum { + MM_SPINOR_FUNC_GET_INFO, + MM_SPINOR_FUNC_READ, + MM_SPINOR_FUNC_WRITE, + MM_SPINOR_FUNC_ERASE, + MM_SPINOR_FUNC_GET_NVRAM_INFO, + MM_SPINOR_FUNC_GET_NVRAM2_INFO, + MM_SPINOR_FUNC_GET_FAILSAFE_INFO +}; + +enum { + MM_NVPARAM_FUNC_READ =3D 1, + MM_NVPARAM_FUNC_WRITE, + MM_NVPARAM_FUNC_CLEAR, + MM_NVPARAM_FUNC_CLEAR_ALL +}; + +#define MM_SPINOR_RES_SUCCESS 0xAABBCC00 +#define MM_SPINOR_RES_FAIL 0xAABBCCFF + +#define MM_NVPARAM_RES_SUCCESS 0xAABBCC00 +#define MM_NVPARAM_RES_NOT_SET 0xAABBCC01 +#define MM_NVPARAM_RES_NO_PERM 0xAABBCC02 +#define MM_NVPARAM_RES_FAIL 0xAABBCCFF + +#define EFI_MM_MAX_PAYLOAD_U64_E 10 +#define EFI_MM_MAX_PAYLOAD_SIZE (EFI_MM_MAX_PAYLOAD_U64_E * sizeof(UINT6= 4)) +#define EFI_MM_MAX_TMP_BUF_SIZE 0x1000000 + +typedef struct { + /* Allows for disambiguation of the message format */ + EFI_GUID HeaderGuid; + /* + * Describes the size of Data (in bytes) and does not include the size + * of the header + */ + UINTN MsgLength; +} EFI_MM_COMM_HEADER_NOPAYLOAD; + +typedef struct { + UINT64 Data[EFI_MM_MAX_PAYLOAD_U64_E]; +} EFI_MM_COMM_PAYLOAD; + +typedef struct { + EFI_MM_COMM_HEADER_NOPAYLOAD EfiMmHdr; + EFI_MM_COMM_PAYLOAD PayLoad; +} EFI_MM_COMM_REQUEST; + +typedef struct { + UINT64 Status; + UINT64 DeviceBase; + UINT64 PageSize; + UINT64 SectorSize; + UINT64 DeviceSize; +} EFI_MM_COMMUNICATE_SPINOR_RES; + +typedef struct { + UINT64 Status; + UINT64 NVBase; + UINT64 NVSize; +} EFI_MM_COMMUNICATE_SPINOR_NVINFO_RES; + +typedef struct { + UINT64 Status; + UINT64 Value; +} EFI_MM_COMMUNICATE_NVPARAM_RES; + +#endif /* MM_LIB_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h b/Silicon/A= mpere/AmpereAltraPkg/Include/NVParamDef.h new file mode 100644 index 000000000000..1891d055fd9e --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h @@ -0,0 +1,515 @@ +/** @file + + The non-volatile parameter layout in SPI-NOR is shown below. There is + two copies. The master copy is changeable by the user. The Last Known + copy is handled by the fail safe future. It is a last know bootable copy= . + + --------------------------- + | Master Copy | 16KB + | Pre-boot parameters | + --------------------------- + | Master Copy | 16KB + | Pre-boot parameters | + | w/o failsafe support | + --------------------------- + | Master Copy | + | Manufactory & | 32KB + | Users parameters | + --------------------------- + | Last Known Copy | 16KB + | Pre-boot parameters | + --------------------------- + | | 16KB + --------------------------- + | Last Known Copy | + | Manufactory & | 32KB + | Users parameters | + --------------------------- + + As each non-volatile parameter requires 8 bytes, there is a total of 8K + parameters. + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef NVPARAMDEF_H_ +#define NVPARAMDEF_H_ + +typedef enum { + /* + * SoC validation pre-boot non-volatile setting + * + * These parameters will reset to default value on failsafe. + * They are not used in production life cycle. + */ + NV_PREBOOT_PARAM_START =3D 0x000000, + NV_SI_PCP_VDMC =3D (1 * 8) + NV_PREBOOT_PARAM= _START, + NV_SI_FAILSAFE_RETRY =3D (2 * 8) + NV_PREBOOT_PARAM= _START, + NV_SI_DDR_PPR_EN =3D (3 * 8) + NV_PREBOOT_PARAM= _START, + NV_SI_DDR_RESERVED0 =3D (4 * 8) + NV_PREBOOT_PARAM= _START, + NV_SI_DDR_RESERVED1 =3D (5 * 8) + NV_PREBOOT_PARAM= _START, + NV_SI_DDR_LOG_LEVEL =3D (6 * 8) + NV_PREBOOT_PARAM= _START, + NV_SI_DDR_RESERVED2 =3D (7 * 8) + NV_PREBOOT_PARAM= _START, + NV_SI_DDR_RD_DBI_EN =3D (8 * 8) + NV_PREBOOT_PARAM= _START, + NV_SI_DDR_WR_DBI_EN =3D (9 * 8) + NV_PREBOOT_PARAM= _START, + NV_SI_DDR_RETRY_EN =3D (10 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_BANK_HASH_EN =3D (11 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_RESERVED3 =3D (12 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_RCD_PARITY_EN =3D (13 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_WRPATH_CLK_GATE_EN =3D (14 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_IOCAL_MARGIN =3D (15 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_RTR_S_MARGIN =3D (16 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_RTR_L_MARGIN =3D (17 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_RTR_CS_MARGIN =3D (18 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_WTW_S_MARGIN =3D (19 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_WTW_L_MARGIN =3D (20 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_WTW_CS_MARGIN =3D (21 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_RTW_S_MARGIN =3D (22 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_RTW_L_MARGIN =3D (23 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_RTW_CS_MARGIN =3D (24 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_WTR_S_MARGIN =3D (25 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_WTR_L_MARGIN =3D (26 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_WTR_CS_MARGIN =3D (27 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_PARITY_EN =3D (28 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_SLC_DISABLE =3D (29 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_SLC_SIZE =3D (30 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_SLC_SCRUB =3D (31 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_CCIX_DISABLE =3D (32 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_ESM_SPEED =3D (33 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_PHY_CAL_MODE =3D (34 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_RAS_TEST_EN =3D (35 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_EYE_SCREEN_TEST_EN =3D (36 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_EYE_MASK_RD_MARGIN =3D (37 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_EYE_MASK_WR_MARGIN =3D (38 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_RDODT_ON_MARGIN =3D (39 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_RDODT_OFF_MARGIN =3D (40 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_WRODT_ON_MARGIN =3D (41 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_WRODT_OFF_MARGIN =3D (42 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_SLC_OCM_EN =3D (43 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_ESM_WIDTH =3D (44 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_TM2_DISABLE =3D (45 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_CPUPLL_FREQ_MHZ =3D (46 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_ERR_INJECT_MASK_SK0 =3D (47 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_ERR_INJECT_MASK_SK1 =3D (48 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_CXG_DISABLE_EARLY_COMPACK =3D (49 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_CXG_ENABLE_SAME_ADDR_COMP_ORDER =3D (50 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_TURNAROUND_CONTROL =3D (51 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_HIT_TURNAROUND_CONTROL =3D (52 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_QOS_CLASS_CONTROL =3D (53 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_ESCALATION_CONTROL =3D (54 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_QV_CONTROL_31_00 =3D (55 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_QV_CONTROL_63_32 =3D (56 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_CREDIT_CONTROL =3D (57 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_WRITE_PRIORITY_CONTROL_31_00 =3D (58 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_WRITE_PRIORITY_CONTROL_63_32 =3D (59 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_QUEUE_THRESHOLD_CONTROL_31_00 =3D (60 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_QUEUE_THRESHOLD_CONTROL_63_32 =3D (61 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_ATF_FAILURE_FAILSAFE =3D (62 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_UEFI_FAILURE_FAILSAFE =3D (63 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_STRIPE_DECODE =3D (64 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_DEBUG_CTRL =3D (65 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_CXG_RA_DEVNR_ORD_WFC_DIS =3D (66 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_PHY_DLL_TRACK_UPD_THRESHOLD =3D (67 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_PHY_DLL_TRACK_UPD_THRESHOLD_AC =3D (68 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_PHY_INIT_UPDATE_CONFIG =3D (69 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_PHY_UPDATE_CONTROL =3D (70 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_PROFILE_EN =3D (71 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_PCIE_PHY_SETTING =3D (72 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_PHY_CAL_THRESHOLD =3D (73 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_PHY_CAL_INTERVAL_CNT =3D (74 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_RESERVED =3D (75 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_S0_RHS_RCA_EN =3D (76 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_S1_RHS_RCA_EN =3D (77 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_2P_DPLL =3D (78 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_2P_ALI_CFG =3D (79 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_2P_ALI_CFG_LINK_RETRAIN =3D (80 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_2P_ALI_CFG_CRC =3D (81 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_RT_CONTROL_31_00 =3D (82 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_RT_CONTROL_63_32 =3D (83 * 8) + NV_PREBOOT_PARA= M_START, + NV_SI_DDR_TIMEOUT_CONTROL =3D (84 * 8) + NV_PREBOOT_PARA= M_START, + NV_PMPRO_REGION1_LOAD_START =3D NV_SI_SLC_DISABLE, + NV_PMPRO_REGION1_LOAD_END =3D NV_SI_2P_ALI_CFG_CRC, + /* NOTE: Add before NV_PREBOOT_PARAM_MAX and increase its value */ + NV_PREBOOT_PARAM_MAX =3D (84 * 8) + NV_PREBOOT_PARA= M_START, + + /* + * Manufactory non-volatile memory + * + * These parameters will reset to default value on failsafe. + */ + NV_MANU_PARAM_START =3D 0x004000, + NV_SI_DDR_VMARGIN =3D (0 * 8) + NV_MANU_PARAM_ST= ART, + NV_PMPRO_REGION2_LOAD_START =3D NV_SI_DDR_VMARGIN, + NV_SI_SOC_VMARGIN =3D (1 * 8) + NV_MANU_PARAM_ST= ART, + NV_SI_AVS_VMARGIN =3D (2 * 8) + NV_MANU_PARAM_ST= ART, + NV_SI_TPC_TM1_MARGIN =3D (3 * 8) + NV_MANU_PARAM_ST= ART, + NV_SI_TPC_TM2_MARGIN =3D (4 * 8) + NV_MANU_PARAM_ST= ART, + NV_SI_TPC_FREQ_THROTTLE =3D (5 * 8) + NV_MANU_PARAM_ST= ART, + NV_SI_T_LTLM_EN =3D (6 * 8) + NV_MANU_PARAM_ST= ART, + NV_SI_T_LTLM_THRSHLD =3D (7 * 8) + NV_MANU_PARAM_ST= ART, + NV_SI_T_GTLM_THRSHLD =3D (8 * 8) + NV_MANU_PARAM_ST= ART, + NV_SI_P_LM_EN =3D (9 * 8) + NV_MANU_PARAM_ST= ART, + NV_SI_P_LM_THRSHLD =3D (10 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_TPC_OVERTEMP_ISR_DISABLE =3D (11 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_VPP_VMARGIN =3D (12 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PMPRO_FAILURE_FAILSAFE =3D (13 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_FAILSAFE_DISABLE =3D (14 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLIMIT_APM_DS_PERCENTAGE =3D (15 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLIMIT_APM_EP_MS =3D (16 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLIMIT_APM_PM1_PERCENTAGE_TDP =3D (17 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_CPU_LPI_FREQ_DISABLE =3D (18 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_CPU_LPI_FREQ_ENERGY_THRSHLD =3D (19 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_CCIX_OPT_CONFIG =3D (20 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_MESH_FREQ_MARGIN =3D (21 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_MESH_TURBO_EN =3D (22 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PWR_HEADROOM_WATT =3D (23 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_EXTRA_PCP_VOLT_MV =3D (24 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_CPU_LPI_HYST_CNT =3D (25 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_DVFS_VOLT_INC_STEP_MV =3D (26 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_DVFS_VOLT_DEC_STEP_MV =3D (27 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLIMIT_APM_TEMP_THLD =3D (28 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLIMIT_APM_EN =3D (29 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_VDM_EN =3D (30 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_VDM_VMARGIN_MV =3D (31 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLT_EN =3D (32 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLT_SOCKET =3D (33 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLT_MCU_MASK =3D (34 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLT_RANK_MASK =3D (35 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLT_SLICE_MASK =3D (36 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLT_BIT_MASK =3D (37 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLT_X_PARAM =3D (38 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLT_Y_PARAM =3D (39 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLT_X_LEFT =3D (40 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLT_X_RIGHT =3D (41 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLT_X_STEP =3D (42 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLT_Y_BOTTOM =3D (43 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLT_Y_TOP =3D (44 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLT_Y_STEP =3D (45 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLT_START_ADDR_LO =3D (46 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLT_START_ADDR_UP =3D (47 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLT_SIZE =3D (48 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLT_THREAD_CNT =3D (49 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLT_SCREEN =3D (50 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_PLT_RSVD =3D (51 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_DVFS_VOLT_CHANGE_BY_STEP_EN =3D (52 * 8) + NV_MANU_PARAM_S= TART, + NS_SI_DVFS_TCAL_F_LIMIT =3D (53 * 8) + NV_MANU_PARAM_S= TART, + NS_SI_DVFS_TCAL_T_LIMIT =3D (54 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_CCIX_DIAG_CTRL1 =3D (55 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_CCIX_DIAG_CTRL2 =3D (56 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_DDR_TCAL_EN =3D (57 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_DDR_TCAL_DIMM_LOW_TEMP_THRESHOLD =3D (58 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_DDR_TCAL_DIMM_HIGH_TEMP_THRESHOLD =3D (59 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_DDR_TCAL_MCU_LOW_TEMP_THRESHOLD =3D (60 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_DDR_TCAL_MCU_HIGH_TEMP_THRESHOLD =3D (61 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_DDR_TCAL_LOW_TEMP_VOLT_OFF_MV =3D (62 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_DDR_TCAL_PERIOD_SEC =3D (63 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_DDR_TCAL_SOC_VOLT_CAP_MV =3D (64 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_ALTRAMAX_ICCMAX_EN =3D (65 * 8) + NV_MANU_PARAM_S= TART, + NV_SI_MESH_TURBO_ACTIVITY_THRESHOLD =3D (66 * 8) + NV_MANU_PARAM_S= TART, + NV_PMPRO_REGION2_LOAD_END =3D NV_SI_MESH_TURBO_ACTIVITY_= THRESHOLD, + /* NOTE: Add before NV_MANU_PARAM_MAX and increase its value */ + NV_MANU_PARAM_MAX =3D (66 * 8) + NV_MANU_PARAM_S= TART, + + /* + * User non-volatile memory + * + * These parameters will reset to default value on failsafe. + */ + NV_USER_PARAM_START =3D 0x008000, + NV_SI_S0_PCP_ACTIVECPM_0_31 =3D (0 * 8) + NV_USER_PARAM_ST= ART, + NV_SI_S0_PCP_ACTIVECPM_32_63 =3D (1 * 8) + NV_USER_PARAM_ST= ART, + NV_SI_S1_PCP_ACTIVECPM_0_31 =3D (2 * 8) + NV_USER_PARAM_ST= ART, + NV_SI_S1_PCP_ACTIVECPM_32_63 =3D (3 * 8) + NV_USER_PARAM_ST= ART, + NV_SI_WDT_BIOS_EXP_MINS =3D (4 * 8) + NV_USER_PARAM_ST= ART, + NV_SI_DDR_CE_RAS_THRESHOLD =3D (5 * 8) + NV_USER_PARAM_ST= ART, + NV_SI_DDR_CE_RAS_INTERVAL =3D (6 * 8) + NV_USER_PARAM_ST= ART, + NV_SI_DDR_SPEED =3D (7 * 8) + NV_USER_PARAM_ST= ART, + NV_SI_DDR_SCRUB_EN =3D (8 * 8) + NV_USER_PARAM_ST= ART, + NV_SI_DDR_ECC_MODE =3D (9 * 8) + NV_USER_PARAM_ST= ART, + NV_SI_S0_RCA_PCI_DEVMAP =3D (10 * 8) + NV_USER_PARAM_S= TART, + NV_SI_S0_RCB_PCI_DEVMAP =3D (11 * 8) + NV_USER_PARAM_S= TART, + NV_SI_S1_RCA_PCI_DEVMAP =3D (12 * 8) + NV_USER_PARAM_S= TART, + NV_SI_S1_RCB_PCI_DEVMAP =3D (13 * 8) + NV_USER_PARAM_S= TART, + NV_SI_DDR_ERRCTRL =3D (14 * 8) + NV_USER_PARAM_S= TART, + NV_SI_DDR_REFRESH_GRANULARITY =3D (15 * 8) + NV_USER_PARAM_S= TART, + NV_SI_SUBNUMA_MODE =3D (16 * 8) + NV_USER_PARAM_S= TART, + NV_SI_ERRATUM_1542419_WA =3D (17 * 8) + NV_USER_PARAM_S= TART, + NV_SI_NEAR_ATOMIC_DISABLE =3D (18 * 8) + NV_USER_PARAM_S= TART, + NV_SI_DDR_SLAVE_32BIT_MEM_EN =3D (19 * 8) + NV_USER_PARAM_S= TART, + NV_SI_CPUECTLR_EL1_0_31 =3D (20 * 8) + NV_USER_PARAM_S= TART, + NV_SI_CPUECTLR_EL1_32_63 =3D (21 * 8) + NV_USER_PARAM_S= TART, + NV_SI_HARDWARE_EINJ =3D (22 * 8) + NV_USER_PARAM_S= TART, + NV_SI_2P_CE_RAS_THRESHOLD =3D (23 * 8) + NV_USER_PARAM_S= TART, + NV_SI_2P_CE_RAS_INTERVAL =3D (24 * 8) + NV_USER_PARAM_S= TART, + NV_SI_RAS_BERT_ENABLED =3D (25 * 8) + NV_USER_PARAM_S= TART, + NV_SI_HNF_AUX_CTL_0_31 =3D (26 * 8) + NV_USER_PARAM_S= TART, + NV_SI_HNF_AUX_CTL_32_63 =3D (27 * 8) + NV_USER_PARAM_S= TART, + NV_SI_CPM_CE_RAS_THRESHOLD =3D (28 * 8) + NV_USER_PARAM_S= TART, + NV_SI_CPM_CE_RAS_INTERVAL =3D (29 * 8) + NV_USER_PARAM_S= TART, + NV_SI_HNF_AUX_CTL_0_31_WR_EN_MASK =3D (30 * 8) + NV_USER_PARAM_S= TART, + NV_SI_HNF_AUX_CTL_32_63_WR_EN_MASK =3D (31 * 8) + NV_USER_PARAM_S= TART, + NV_SI_DDR_WR_BACK_EN =3D (32 * 8) + NV_USER_PARAM_S= TART, + NV_SI_CPUECTLR_EL1_0_31_WR_EN_MASK =3D (33 * 8) + NV_USER_PARAM_S= TART, + NV_SI_CPUECTLR_EL1_32_63_WR_EN_MASK =3D (34 * 8) + NV_USER_PARAM_S= TART, + NV_SI_LINK_ERR_THRESHOLD =3D (35 * 8) + NV_USER_PARAM_S= TART, + NV_SI_SEC_WDT_BIOS_EXP_MINS =3D (36 * 8) + NV_USER_PARAM_S= TART, + NV_SI_NVDIMM_MODE =3D (37 * 8) + NV_USER_PARAM_S= TART, + NV_SI_RAS_SDEI_ENABLED =3D (38 * 8) + NV_USER_PARAM_S= TART, + NV_SI_NVDIMM_PROV_MASK_S0 =3D (39 * 8) + NV_USER_PARAM_S= TART, + NV_SI_NVDIMM_PROV_MASK_S1 =3D (40 * 8) + NV_USER_PARAM_S= TART, + NV_SI_DDR_ZQCS_EN =3D (41 * 8) + NV_USER_PARAM_S= TART, + NV_SI_DDR_CRC_MODE =3D (42 * 8) + NV_USER_PARAM_S= TART, + NV_SI_CXG_RA_AUX_CTL_0_31 =3D (43 * 8) + NV_USER_PARAM_S= TART, + NV_SI_CXG_RA_AUX_CTL_32_63 =3D (44 * 8) + NV_USER_PARAM_S= TART, + NV_SI_CXG_RA_AUX_CTL_0_31_WR_EN_MASK =3D (45 * 8) + NV_USER_PARAM_S= TART, + NV_SI_CXG_RA_AUX_CTL_32_63_WR_EN_MASK =3D (46 * 8) + NV_USER_PARAM_S= TART, + NV_SI_CXLA_AUX_CTL_0_31 =3D (47 * 8) + NV_USER_PARAM_S= TART, + NV_SI_CXLA_AUX_CTL_32_63 =3D (48 * 8) + NV_USER_PARAM_S= TART, + NV_SI_CXLA_AUX_CTL_0_31_WR_EN_MASK =3D (49 * 8) + NV_USER_PARAM_S= TART, + NV_SI_CXLA_AUX_CTL_32_63_WR_EN_MASK =3D (50 * 8) + NV_USER_PARAM_S= TART, + NV_SI_DDR_LOW_POWER_CFG =3D (51 * 8) + NV_USER_PARAM_S= TART, + NV_SI_ALERT_DIMM_SHUTDOWN_EN =3D (52 * 8) + NV_USER_PARAM_S= TART, + NV_SI_DFS_EN =3D (53 * 8) + NV_USER_PARAM_S= TART, + NV_SI_RAS_PCIE_AER_FW_FIRST =3D (54 * 8) + NV_USER_PARAM_S= TART, + NV_SI_RAS_DRAM_EINJ_NOTRIGGER =3D (55 * 8) + NV_USER_PARAM_S= TART, + NV_SI_RAS_AEST_PROC_EN =3D (56 * 8) + NV_USER_PARAM_S= TART, + NV_SI_MESH_S0_CXG_RC_STRONG_ORDERING_EN =3D (57 * 8) + NV_USER_PARAM_S= TART, + NV_SI_MESH_S1_CXG_RC_STRONG_ORDERING_EN =3D (58 * 8) + NV_USER_PARAM_S= TART, + NV_SI_2P_RESERVED0 =3D (59 * 8) + NV_USER_PARAM_S= TART, + NV_SI_2P_RESERVED1 =3D (60 * 8) + NV_USER_PARAM_S= TART, + NV_SI_2P_RESERVED2 =3D (61 * 8) + NV_USER_PARAM_S= TART, + NV_SI_HCR_EL2_CTL_LOW =3D (62 * 8) + NV_USER_PARAM_S= TART, + NV_SI_HCR_EL2_CTL_HIGH =3D (63 * 8) + NV_USER_PARAM_S= TART, + /* NOTE: Add before NV_USER_PARAM_MAX and increase its value */ + NV_USER_PARAM_MAX =3D (63 * 8) + NV_USER_PARAM_S= TART, + NV_PMPRO_REGION3_LOAD_START =3D NV_USER_PARAM_START, + NV_PMPRO_REGION3_LOAD_END =3D NV_USER_PARAM_MAX, + + /* + * Non-volatile board read-only setting + * + * These parameters do not support failsafe and will always read + * from its location. Please note that the physical base address + * location for board setting is not the same as above region. This + * allows packaging these board setting along with the firmware + * image itself. See SPI-NOR flash layout design for more info. + * + * Please note that script will parse these and generate + * board setting. The keyword "Default: " is used to provide + * the default value. + */ + NV_BOARD_PARAM_START =3D 0x00C000, + NV_SI_RO_BOARD_VENDOR =3D (0 * 8) + NV_BOARD_PARAM_S= TART, /* Default: 0x0000CD3A - Follow BMC FRU format */ + NV_PMPRO_REGION4_LOAD_START =3D NV_SI_RO_BOARD_VENDOR, + NV_SI_RO_BOARD_TYPE =3D (1 * 8) + NV_BOARD_PARAM_S= TART, /* Default: 0x00000000 - Follow BMC FRU format */ + NV_SI_RO_BOARD_REV =3D (2 * 8) + NV_BOARD_PARAM_S= TART, /* Default: 0x00000000 Follow BMC FRU format */ + NV_SI_RO_BOARD_CFG =3D (3 * 8) + NV_BOARD_PARAM_S= TART, /* Default: 0x00000000 Follow BMC FRU format */ + NV_SI_RO_BOARD_S0_DIMM_AVAIL =3D (4 * 8) + NV_BOARD_PARAM_S= TART, /* Default: 0x0000FFFF */ + NV_SI_RO_BOARD_S1_DIMM_AVAIL =3D (5 * 8) + NV_BOARD_PARAM_S= TART, /* Default: 0x0000FFFF */ + NV_SI_RO_BOARD_SPI0CS0_FREQ_KHZ =3D (6 * 8) + NV_BOARD_PARAM_S= TART, /* Default: 33000 */ + NV_SI_RO_BOARD_SPI0CS1_FREQ_KHZ =3D (7 * 8) + NV_BOARD_PARAM_S= TART, /* Default: 33000 */ + NV_SI_RO_BOARD_SPI1CS0_FREQ_KHZ =3D (8 * 8) + NV_BOARD_PARAM_S= TART, /* Default: 10000 */ + NV_SI_RO_BOARD_SPI1CS1_FREQ_KHZ =3D (9 * 8) + NV_BOARD_PARAM_S= TART, /* Default: 10000 */ + NV_SI_RO_BOARD_TPM_LOC =3D (10 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_I2C0_FREQ_KHZ =3D (11 * 8) + NV_BOARD_PARAM_= START, /* Default: 400 */ + NV_SI_RO_BOARD_I2C1_FREQ_KHZ =3D (12 * 8) + NV_BOARD_PARAM_= START, /* Default: 400 */ + NV_SI_RO_BOARD_I2C2_10_FREQ_KHZ =3D (13 * 8) + NV_BOARD_PARAM_= START, /* Default: 400 */ + NV_SI_RO_BOARD_I2C3_FREQ_KHZ =3D (14 * 8) + NV_BOARD_PARAM_= START, /* Default: 400 */ + NV_SI_RO_BOARD_I2C9_FREQ_KHZ =3D (15 * 8) + NV_BOARD_PARAM_= START, /* Default: 400 */ + NV_SI_RO_BOARD_2P_CFG =3D (16 * 8) + NV_BOARD_PARAM_= START, /* Default: 0xFFFFFF01 */ + NV_SI_RO_BOARD_S0_RCA0_CFG =3D (17 * 8) + NV_BOARD_PARAM_= START, + NV_SI_RO_BOARD_S0_RCA1_CFG =3D (18 * 8) + NV_BOARD_PARAM_= START, + NV_SI_RO_BOARD_S0_RCA2_CFG =3D (19 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00000004 */ + NV_SI_RO_BOARD_S0_RCA3_CFG =3D (20 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00000004 */ + NV_SI_RO_BOARD_S0_RCB0_LO_CFG =3D (21 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S0_RCB0_HI_CFG =3D (22 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S0_RCB1_LO_CFG =3D (23 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S0_RCB1_HI_CFG =3D (24 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S0_RCB2_LO_CFG =3D (25 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S0_RCB2_HI_CFG =3D (26 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00000003 */ + NV_SI_RO_BOARD_S0_RCB3_LO_CFG =3D (27 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00000003 */ + NV_SI_RO_BOARD_S0_RCB3_HI_CFG =3D (28 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S1_RCA0_CFG =3D (29 * 8) + NV_BOARD_PARAM_= START, + NV_SI_RO_BOARD_S1_RCA1_CFG =3D (30 * 8) + NV_BOARD_PARAM_= START, + NV_SI_RO_BOARD_S1_RCA2_CFG =3D (31 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x02020202 */ + NV_SI_RO_BOARD_S1_RCA3_CFG =3D (32 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00030003 */ + NV_SI_RO_BOARD_S1_RCB0_LO_CFG =3D (33 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00000003 */ + NV_SI_RO_BOARD_S1_RCB0_HI_CFG =3D (34 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S1_RCB1_LO_CFG =3D (35 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S1_RCB1_HI_CFG =3D (36 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00000003 */ + NV_SI_RO_BOARD_S1_RCB2_LO_CFG =3D (37 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S1_RCB2_HI_CFG =3D (38 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S1_RCB3_LO_CFG =3D (39 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S1_RCB3_HI_CFG =3D (40 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_T_LTLM_DELTA_P0 =3D (41 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00000001 */ + NV_SI_RO_BOARD_T_LTLM_DELTA_P1 =3D (42 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00000002 */ + NV_SI_RO_BOARD_T_LTLM_DELTA_P2 =3D (43 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00000003 */ + NV_SI_RO_BOARD_T_LTLM_DELTA_P3 =3D (44 * 8) + NV_BOARD_PARAM_= START, /* Default: 0x00000004 */ + NV_SI_RO_BOARD_T_LTLM_DELTA_M1 =3D (45 * 8) + NV_BOARD_PARAM_= START, /* Default: 0xFFFFFFFF */ + NV_SI_RO_BOARD_T_LTLM_DELTA_M2 =3D (46 * 8) + NV_BOARD_PARAM_= START, /* Default: 0xFFFFFFFE */ + NV_SI_RO_BOARD_T_LTLM_DELTA_M3 =3D (47 * 8) + NV_BOARD_PARAM_= START, /* Default: 0xFFFFFFFD */ + NV_SI_RO_BOARD_P_LM_PID_P =3D (48 * 8) + NV_BOARD_PARAM_= START, + NV_SI_RO_BOARD_P_LM_PID_I =3D (49 * 8) + NV_BOARD_PARAM_= START, + NV_SI_RO_BOARD_P_LM_PID_I_L_THOLD =3D (50 * 8) + NV_BOARD_PARAM_= START, + NV_SI_RO_BOARD_P_LM_PID_I_H_THOLD =3D (51 * 8) + NV_BOARD_PARAM_= START, + NV_SI_RO_BOARD_P_LM_PID_D =3D (52 * 8) + NV_BOARD_PARAM_= START, + NV_SI_RO_BOARD_P_LM_EXP_SMOOTH_CONST =3D (53 * 8) + NV_BOARD_PARAM_= START, + /* + * NV_SI_RO_BOARD_TPM_ALG_ID: 0=3DDefault to SHA256, 1=3DSHA1, 2=3DSHA25= 6 + * Any other value will lead to default digest. + */ + NV_SI_RO_BOARD_TPM_ALG_ID =3D (54 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x00000002 */ + NV_SI_RO_BOARD_DDR_SPEED_GRADE =3D (55 * 8) + NV_BOAR= D_PARAM_START, /* Default: 3200 */ + NV_SI_RO_BOARD_DDR_S0_RTT_WR =3D (56 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x00020000 */ + NV_SI_RO_BOARD_DDR_S1_RTT_WR =3D (57 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x00020000 */ + NV_SI_RO_BOARD_DDR_S0_RTT_NOM =3D (58 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0xFF060177 */ + NV_SI_RO_BOARD_DDR_S1_RTT_NOM =3D (59 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0xFF060177 */ + NV_SI_RO_BOARD_DDR_S0_RTT_PARK =3D (60 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x00060070 */ + NV_SI_RO_BOARD_DDR_S1_RTT_PARK =3D (61 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x00060070 */ + NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_1DPC =3D (62 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x000000 */ + NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_1DPC =3D (63 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x000000 */ + NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_1DPC =3D (64 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x000000 */ + NV_SI_RO_BOARD_DDR_CS3_RDODT_MASK_1DPC =3D (65 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x000000 */ + NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_2DPC =3D (66 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x0C0CCC */ + NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_2DPC =3D (67 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x0C0CCC */ + NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_2DPC =3D (68 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x030333 */ + NV_SI_RO_BOARD_DDR_CS3_RDODT_MASK_2DPC =3D (69 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x030333 */ + NV_SI_RO_BOARD_DDR_CS0_WRODT_MASK_1DPC =3D (70 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x030333 */ + NV_SI_RO_BOARD_DDR_CS1_WRODT_MASK_1DPC =3D (71 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x030333 */ + NV_SI_RO_BOARD_DDR_CS2_WRODT_MASK_1DPC =3D (72 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x030333 */ + NV_SI_RO_BOARD_DDR_CS3_WRODT_MASK_1DPC =3D (73 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x030333 */ + NV_SI_RO_BOARD_DDR_CS0_WRODT_MASK_2DPC =3D (74 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x0EDEED */ + NV_SI_RO_BOARD_DDR_CS1_WRODT_MASK_2DPC =3D (75 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x0DEDDE */ + NV_SI_RO_BOARD_DDR_CS2_WRODT_MASK_2DPC =3D (76 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x0B7BB7 */ + NV_SI_RO_BOARD_DDR_CS3_WRODT_MASK_2DPC =3D (77 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x07B77B */ + NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_CTRL_1DPC =3D (78 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x5 */ + NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_VAL_1DPC =3D (79 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x90DD90 */ + NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_CTRL_1DPC =3D (80 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x5 */ + NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_VAL_1DPC =3D (81 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x90DD90 */ + NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_CTRL_2DPC =3D (82 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x5 */ + NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_VAL_2DPC =3D (83 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x90DD90 */ + NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_CTRL_2DPC =3D (84 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x5 */ + NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_VAL_2DPC =3D (85 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x90DD90 */ + NV_SI_RO_BOARD_DDR_PHY_VREFDQ_RANGE_VAL_1DPC =3D (86 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x24 */ + NV_SI_RO_BOARD_DDR_DRAM_VREFDQ_RANGE_VAL_1DPC =3D (87 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x1A */ + NV_SI_RO_BOARD_DDR_PHY_VREFDQ_RANGE_VAL_2DPC =3D (88 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x50 */ + NV_SI_RO_BOARD_DDR_DRAM_VREFDQ_RANGE_VAL_2DPC =3D (89 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x20 */ + NV_SI_RO_BOARD_DDR_CLK_WRDQ_DLY_DEFAULT =3D (90 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x02800280 */ + NV_SI_RO_BOARD_DDR_RDDQS_DQ_DLY_DEFAULT =3D (91 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x90909090 */ + NV_SI_RO_BOARD_DDR_WRDQS_SHIFT_DEFAULT =3D (92 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_DDR_ADCMD_DLY_DEFAULT =3D (93 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x00C000C0 */ + NV_SI_RO_BOARD_DDR_CLK_WRDQ_DLY_ADJ =3D (94 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_DDR_RDDQS_DQ_DLY_ADJ =3D (95 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_DDR_PHY_VREF_ADJ =3D (96 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_DDR_DRAM_VREF_ADJ =3D (97 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_DDR_WR_PREAMBLE_CYCLE =3D (98 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x02010201 */ + NV_SI_RO_BOARD_DDR_ADCMD_2T_MODE =3D (99 * 8) + NV_BOAR= D_PARAM_START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_I2C_VRD_CONFIG_INFO =3D (100 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_DDR_PHY_FEATURE_CTRL =3D (101 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_ACCESS =3D (102 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x01050106 */ + NV_SI_RO_BOARD_DIMM_TEMP_THRESHOLD =3D (103 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x554 */ + NV_SI_RO_BOARD_DIMM_SPD_COMPARE_DISABLE =3D (104 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x0 */ + NV_SI_RO_BOARD_S0_PCIE_CLK_CFG =3D (105 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S0_RCA4_CFG =3D (106 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x02020202 */ + NV_SI_RO_BOARD_S0_RCA5_CFG =3D (107 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x02020202 */ + NV_SI_RO_BOARD_S0_RCA6_CFG =3D (108 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x02020202 */ + NV_SI_RO_BOARD_S0_RCA7_CFG =3D (109 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x02020003 */ + NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET =3D (110 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S0_RCA1_TXRX_G3PRESET =3D (111 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S0_RCA2_TXRX_G3PRESET =3D (112 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S0_RCA3_TXRX_G3PRESET =3D (113 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S0_RCB0A_TXRX_G3PRESET =3D (114 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S0_RCB0B_TXRX_G3PRESET =3D (115 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S0_RCB1A_TXRX_G3PRESET =3D (116 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S0_RCB1B_TXRX_G3PRESET =3D (117 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S0_RCB2A_TXRX_G3PRESET =3D (118 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S0_RCB2B_TXRX_G3PRESET =3D (119 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S0_RCB3A_TXRX_G3PRESET =3D (120 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S0_RCB3B_TXRX_G3PRESET =3D (121 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S0_RCA4_TXRX_G3PRESET =3D (122 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S0_RCA5_TXRX_G3PRESET =3D (123 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S0_RCA6_TXRX_G3PRESET =3D (124 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S0_RCA7_TXRX_G3PRESET =3D (125 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S0_RCA0_TXRX_G4PRESET =3D (126 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCA1_TXRX_G4PRESET =3D (127 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCA2_TXRX_G4PRESET =3D (128 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCA3_TXRX_G4PRESET =3D (129 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCB0A_TXRX_G4PRESET =3D (130 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCB0B_TXRX_G4PRESET =3D (131 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCB1A_TXRX_G4PRESET =3D (132 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCB1B_TXRX_G4PRESET =3D (133 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCB2A_TXRX_G4PRESET =3D (134 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCB2B_TXRX_G4PRESET =3D (135 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCB3A_TXRX_G4PRESET =3D (136 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCB3B_TXRX_G4PRESET =3D (137 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCA4_TXRX_G4PRESET =3D (138 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCA5_TXRX_G4PRESET =3D (139 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCA6_TXRX_G4PRESET =3D (140 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCA7_TXRX_G4PRESET =3D (141 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_PCIE_CLK_CFG =3D (142 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S1_RCA4_CFG =3D (143 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x02020202 */ + NV_SI_RO_BOARD_S1_RCA5_CFG =3D (144 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x02020202 */ + NV_SI_RO_BOARD_S1_RCA6_CFG =3D (145 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x02020202 */ + NV_SI_RO_BOARD_S1_RCA7_CFG =3D (146 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x02020003 */ + NV_SI_RO_BOARD_S1_RCA2_TXRX_G3PRESET =3D (147 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S1_RCA3_TXRX_G3PRESET =3D (148 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S1_RCB0A_TXRX_G3PRESET =3D (149 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S1_RCB0B_TXRX_G3PRESET =3D (150 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S1_RCB1A_TXRX_G3PRESET =3D (151 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S1_RCB1B_TXRX_G3PRESET =3D (152 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S1_RCB2A_TXRX_G3PRESET =3D (153 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S1_RCB2B_TXRX_G3PRESET =3D (154 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S1_RCB3A_TXRX_G3PRESET =3D (155 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S1_RCB3B_TXRX_G3PRESET =3D (156 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S1_RCA4_TXRX_G3PRESET =3D (157 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S1_RCA5_TXRX_G3PRESET =3D (158 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S1_RCA6_TXRX_G3PRESET =3D (159 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S1_RCA7_TXRX_G3PRESET =3D (160 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_S1_RCA2_TXRX_G4PRESET =3D (161 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCA3_TXRX_G4PRESET =3D (162 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCB0A_TXRX_G4PRESET =3D (163 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCB0B_TXRX_G4PRESET =3D (164 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCB1A_TXRX_G4PRESET =3D (165 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCB1B_TXRX_G4PRESET =3D (166 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCB2A_TXRX_G4PRESET =3D (167 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCB2B_TXRX_G4PRESET =3D (168 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCB3A_TXRX_G4PRESET =3D (169 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCB3B_TXRX_G4PRESET =3D (170 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCA4_TXRX_G4PRESET =3D (171 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCA5_TXRX_G4PRESET =3D (172 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCA6_TXRX_G4PRESET =3D (173 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCA7_TXRX_G4PRESET =3D (174 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_2P_CE_MASK_THRESHOLD =3D (175 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x00000003 */ + NV_SI_RO_BOARD_2P_CE_MASK_INTERVAL =3D (176 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x000001A4 */ + NV_SI_RO_BOARD_SX_PHY_CFG_SETTING =3D (177 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_DDR_PHY_DC_CLK =3D (178 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x00018000 */ + NV_SI_RO_BOARD_DDR_PHY_DC_DATA =3D (179 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x80018000 */ + NV_SI_RO_BOARD_SX_RCA0_TXRX_20GPRESET =3D (180 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_SX_RCA1_TXRX_20GPRESET =3D (181 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_SX_RCA2_TXRX_20GPRESET =3D (182 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_SX_RCA3_TXRX_20GPRESET =3D (183 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_SX_RCA0_TXRX_25GPRESET =3D (184 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_SX_RCA1_TXRX_25GPRESET =3D (185 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_SX_RCA2_TXRX_25GPRESET =3D (186 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_SX_RCA3_TXRX_25GPRESET =3D (187 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_DDR_2X_REFRESH_TEMP_THRESHOLD =3D (188 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x00550055 */ + NV_SI_RO_BOARD_PCP_VRD_VOUT_WAIT_US =3D (189 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x00000064 */ + NV_SI_RO_BOARD_PCP_VRD_VOUT_RESOLUTION_MV =3D (190 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x00000005 */ + NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_EN =3D (191 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x00000001 */ + NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_TIME =3D (192 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x00000002 */ + NV_SI_RO_BOARD_DVFS_VOUT_20MV_RAMP_TIME_US =3D (193 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x00000005 */ + NV_SI_RO_BOARD_PCIE_AER_FW_FIRST =3D (194 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_RTC_GPI_LOCK_BYPASS =3D (195 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_TPM_DISABLE =3D (196 * 8) + NV_BOA= RD_PARAM_START, + NV_SI_RO_BOARD_MESH_S0_CXG_RC_STRONG_ORDERING_EN =3D (197 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_MESH_S1_CXG_RC_STRONG_ORDERING_EN =3D (198 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_GPIO_SW_WATCHDOG_EN =3D (199 * 8) + NV_BOA= RD_PARAM_START, /* Default: 0x00000000 */ + NV_PMPRO_REGION4_LOAD_END =3D NV_SI_RO_BOARD_GPI= O_SW_WATCHDOG_EN, + /* NOTE: Add before NV_BOARD_PARAM_MAX and increase its value */ + NV_BOARD_PARAM_MAX =3D (199 * 8) + NV_BOA= RD_PARAM_START, +} NVPARAM; + +#endif /* NVPARAMDEF_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h b/Silico= n/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h new file mode 100644 index 000000000000..9b0b2e2f50d5 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h @@ -0,0 +1,146 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PLATFORM_AC01_H_ +#define PLATFORM_AC01_H_ + +/* Number of supported sockets in the platform */ +#define PLATFORM_CPU_MAX_SOCKET 2 + +/* Maximum number of CPMs in the chip. */ +#define PLATFORM_CPU_MAX_CPM (FixedPcdGet32 (PcdClusterCoun= t)) + +/* Number of cores per CPM. */ +#define PLATFORM_CPU_NUM_CORES_PER_CPM (FixedPcdGet32 (PcdCoreCount) = / PLATFORM_CPU_MAX_CPM) + +/* Socket bit offset of core UID. */ +#define PLATFORM_SOCKET_UID_BIT_OFFSET 16 + +/* CPM bit offset of core UID. */ +#define PLATFORM_CPM_UID_BIT_OFFSET 8 + +/* Maximum number of cores supported. */ +#define PLATFORM_CPU_MAX_NUM_CORES (PLATFORM_CPU_MAX_SOCKET * PLATFORM_CP= U_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM) + +/* Maximum number of memory region */ +#define PLATFORM_DRAM_INFO_MAX_REGION 16 + +/* Maximum number of DDR slots supported */ +#define PLATFORM_DIMM_INFO_MAX_SLOT 32 + +/* Maximum number of memory supported. */ +#define PLATFORM_MAX_MEMORY_REGION 4 + +/* The Array of Soc Gpio Base Address */ +#define GPIO_DWAPB_BASE_ADDR 0x1000026f0000,0x1000026e0000,0x1000027b= 0000,0x1000026d0000,0x5000026f0000,0x5000026e0000,0x5000027b0000,0x5000026d= 0000 + +/* The Array of Soc Gpi Base Address */ +#define GPI_DWAPB_BASE_ADDR 0x1000026d0000,0x5000026d0000 + +/* Number of Pins Per Each Contoller */ +#define GPIO_DWAPB_PINS_PER_CONTROLLER 8 + +/* Number of Pins Each Socket */ +#define GPIO_DWAPB_PINS_PER_SOCKET 32 + +/* The maximum number of I2C bus */ +#define MAX_PLATFORM_I2C_BUS_NUM 2 + +/* The base address of DW I2C */ +#define PLATFORM_I2C_REGISTER_BASE 0x1000026B0000ULL, 0x10000275000= 0ULL + +/* Offset of failsafe testing feature */ +#define NV_UEFI_FAILURE_FAILSAFE_OFFSET 0x1F8 + +/* Maximum number of memory controller supports NVDIMM-N per socket */ +#define PLATFORM_NVDIMM_MCU_MAX_PER_SK 2 + +/* Maximum number of NVDIMM-N per memory controller */ +#define PLATFORM_NVDIMM_NUM_MAX_PER_MCU 1 + +/* Maximum number of NVDIMM region per socket */ +#define PLATFORM_NVDIMM_REGION_MAX_PER_SK 2 + +/* Socket 0 base address of NVDIMM non-hashed region 0 */ +#define PLATFORM_NVDIMM_SK0_NHASHED_REGION0 0x0B0000000000ULL + +/* Socket 0 base address of NVDIMM non-hashed region 1 */ +#define PLATFORM_NVDIMM_SK0_NHASHED_REGION1 0x0F0000000000ULL + +/* Socket 1 base address of NVDIMM non-hashed region 0 */ +#define PLATFORM_NVDIMM_SK1_NHASHED_REGION0 0x430000000000ULL + +/* Socket 1 base address of NVDIMM non-hashed region 1 */ +#define PLATFORM_NVDIMM_SK1_NHASHED_REGION1 0x470000000000ULL + +/* DIMM ID of NVDIMM-N device 1 */ +#define PLATFORM_NVDIMM_NVD1_DIMM_ID 6 + +/* DIMM ID of NVDIMM-N device 2 */ +#define PLATFORM_NVDIMM_NVD2_DIMM_ID 14 + +/* DIMM ID of NVDIMM-N device 3 */ +#define PLATFORM_NVDIMM_NVD3_DIMM_ID 22 + +/* DIMM ID of NVDIMM-N device 4 */ +#define PLATFORM_NVDIMM_NVD4_DIMM_ID 30 + +/* NFIT device handle of NVDIMM-N device 1 */ +#define PLATFORM_NVDIMM_NVD1_DEVICE_HANDLE 0x0330 + +/* NFIT device handle of NVDIMM-N device 2 */ +#define PLATFORM_NVDIMM_NVD2_DEVICE_HANDLE 0x0770 + +/* NFIT device handle of NVDIMM-N device 3 */ +#define PLATFORM_NVDIMM_NVD3_DEVICE_HANDLE 0x1330 + +/* NFIT device handle of NVDIMM-N device 4 */ +#define PLATFORM_NVDIMM_NVD4_DEVICE_HANDLE 0x1770 + +/* Interleave ways of non-hashed NVDIMM-N */ +#define PLATFORM_NVDIMM_NHASHED_INTERLEAVE_WAYS 1 + +/* Interleave ways of hashed NVDIMM-N */ +#define PLATFORM_NVDIMM_HASHED_INTERLEAVE_WAYS 2 + +/* Region offset of hashed NVDIMM-N */ +#define PLATFORM_NVDIMM_HASHED_REGION_OFFSET 512 + +/* The base address of master socket GIC redistributor registers */ +#define GICR_MASTER_BASE_REG 0x100100140000 + +/* The base address of GIC distributor registers */ +#define GICD_BASE_REG 0x100100000000 + +/* The base address of slave socket GIC redistributor registers */ +#define GICR_SLAVE_BASE_REG 0x500100140000 + +/* The base address of slave socket GIC distributor registers */ +#define GICD_SLAVE_BASE_REG 0x500100000000 + +/* Socket 0 first RC */ +#define SOCKET0_FIRST_RC 2 + +/* Socket 0 last RC */ +#define SOCKET0_LAST_RC 7 + +/* Socket 1 first RC */ +#define SOCKET1_FIRST_RC 10 + +/* Socket 1 last RC */ +#define SOCKET1_LAST_RC 15 + +// +// SMpro EFUSE Shadow register +// +#define SMPRO_EFUSE_SHADOW0 (FixedPcdGet64 (PcdSmproEfuseShadow0)) + +#define CFG2P_OFFSET 0x200 +#define SLAVE_PRESENT_N BIT1 // Slave socket present + +#endif /* PLATFORM_AC01_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/PlatformInfoHob.h b/Sili= con/Ampere/AmpereAltraPkg/Include/PlatformInfoHob.h new file mode 100644 index 000000000000..f8abcb92a17c --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/PlatformInfoHob.h @@ -0,0 +1,182 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PLATFORM_INFO_HOB_H_ +#define PLATFORM_INFO_HOB_H_ + +#include +#include + +/* DIMM type */ +enum { + UDIMM, + RDIMM, + SODIMM, + RSODIMM, + LRDIMM, + NVRDIMM +}; + +/* DIMM status */ +enum { + DIMM_NOT_INSTALLED =3D 0, + DIMM_INSTALLED_OPERATIONAL, /* installed and operational */ + DIMM_INSTALLED_NONOPERATIONAL, /* installed and non-operational */ + DIMM_INSTALLED_FAILED /* installed and failed */ +}; + +typedef struct { + UINT32 NumRegion; + UINT64 TotalSize; + UINT64 Base[PLATFORM_DRAM_INFO_MAX_REGION]; + UINT64 Size[PLATFORM_DRAM_INFO_MAX_REGION]; + UINT64 Node[PLATFORM_DRAM_INFO_MAX_REGION]; + UINT64 Socket[PLATFORM_DRAM_INFO_MAX_REGION]; + UINT32 MaxSpeed; + UINT32 McuMask[PLATFORM_CPU_MAX_SOCKET]; + UINT32 NvdRegion[PLATFORM_DRAM_INFO_MAX_REGION]; + UINT32 NvdimmMode[PLATFORM_CPU_MAX_SOCKET]; +} PLATFORM_DRAM_INFO; + +typedef struct { + CHAR8 PartNumber[32]; + UINT64 DimmSize; + UINT16 DimmMfcId; + UINT16 Reserved; + UINT8 DimmNrRank; + UINT8 DimmType; + UINT8 DimmStatus; + UINT8 DimmDevType; +} PLATFORM_DIMM_INFO; + +typedef struct { + UINT8 Data[512]; +} PLATFORM_DIMM_SPD_DATA; + +typedef struct { + PLATFORM_DIMM_INFO Info; + PLATFORM_DIMM_SPD_DATA SpdData; + UINT32 NodeId; +} PLATFORM_DIMM; + +typedef struct { + UINT32 BoardDimmSlots; + PLATFORM_DIMM Dimm[PLATFORM_DIMM_INFO_MAX_SLOT]; +} PLATFORM_DIMM_LIST; + +typedef struct { + UINT32 EnableMask[4]; +} PLATFORM_CLUSTER_EN; + +// +// Algorithm ID defined in pre-UEFI firmware +// +typedef enum { + PLATFORM_ALGORITHM_SHA1 =3D 1, + PLATFORM_ALGORITHM_SHA256 +} PLATFORM_ALGORITHM_ID; + +// +// Platform digest data definition +// +typedef union { + unsigned char Sha1[SHA1_DIGEST_SIZE]; + unsigned char Sha256[SHA256_DIGEST_SIZE]; +} PLATFORM_TPM_DIGEST; + +#define MAX_VIRTUAL_PCR_INDEX 0x0002 + +#pragma pack(1) +typedef struct { + PLATFORM_ALGORITHM_ID AlgorithmId; + struct { + PLATFORM_TPM_DIGEST Hash; + } VPcr[MAX_VIRTUAL_PCR_INDEX]; // vPCR 0 or 1 +} PLATFORM_VPCR_HASH_INFO; + +typedef struct { + UINT8 InterfaceType; // If I/F is CRB then CRB parameters = are expected + UINT64 InterfaceParametersAddress; // Physical address of interface, by = Value */ + UINT64 InterfaceParametersLength; + UINT32 SupportedAlgorithmsBitMask; + UINT64 EventLogAddress; + UINT64 EventLogLength; + UINT8 Reserved[3]; +} PLATFORM_TPM2_CONFIG_DATA; + +typedef struct { + UINT32 CurrentRequest; + UINT32 LastRequest; + UINT32 LastRequestStatus; +} PLATFORM_TPM2_PPI_REQUEST; + +typedef struct { + UINT64 AddressOfControlArea; + UINT64 ControlAreaLength; + UINT8 InterruptMode; + UINT8 Reserved[3]; + UINT32 InterruptNumber; // Should have a va= lue of zero polling + UINT32 SmcFunctionId; // SMC Function ID + UINT64 PpiRequestNotifyAddress; // Doorbell/Interru= pt Address + PLATFORM_TPM2_PPI_REQUEST *PpiRequest; // PPI Request +} PLATFORM_TPM2_CRB_INTERFACE_PARAMETERS; + +typedef struct { + PLATFORM_TPM2_CONFIG_DATA Tpm2ConfigData; + PLATFORM_TPM2_CRB_INTERFACE_PARAMETERS Tpm2CrbInterfaceParams; + PLATFORM_VPCR_HASH_INFO Tpm2VPcrHashInfo; +} PLATFORM_TPM2_INFO; +#pragma pack() + +typedef struct { + UINT8 MajorNumber; + UINT8 MinorNumber; + UINT64 PcpClk; + UINT64 CpuClk; + UINT64 SocClk; + UINT64 AhbClk; + UINT64 SysClk; + UINT8 CpuInfo[128]; + UINT8 CpuVer[32]; + UINT8 SmPmProVer[32]; + UINT8 SmPmProBuild[32]; + PLATFORM_DRAM_INFO DramInfo; + PLATFORM_DIMM_LIST DimmList; + PLATFORM_CLUSTER_EN ClusterEn[2]; + UINT32 FailSafeStatus; + UINT32 RcDisableMask[2]; + UINT8 ResetStatus; + UINT16 CoreVoltage[2]; + UINT16 SocVoltage[2]; + UINT16 Dimm1Voltage[2]; + UINT16 Dimm2Voltage[2]; + + /* Chip information */ + UINT32 ScuProductId[2]; + UINT8 MaxNumOfCore[2]; + UINT8 Warranty[2]; + UINT8 SubNumaMode[2]; + UINT8 AvsEnable[2]; + UINT32 AvsVoltageMV[2]; + UINT8 TurboCapability[2]; + UINT32 TurboFrequency[2]; + + UINT8 SkuMaxTurbo[2]; + UINT8 SkuMaxCore[2]; + UINT32 AHBCId[2]; + + /* TPM2 Info */ + PLATFORM_TPM2_INFO Tpm2Info; + + /* 2P link info for RCA0/RCA1 */ + UINT8 Link2PSpeed[2]; + UINT8 Link2PWidth[2]; + +} PLATFORM_INFO_HOB; + +#endif /* PLATFORM_INFO_HOB_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.c b= /Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.c new file mode 100644 index 000000000000..04def9fa2e42 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.c @@ -0,0 +1,52 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +BuildPlatformInformationHob ( + VOID + ) +{ + VOID *Hob; + + /* The ATF HOB handoff base is at PcdSystemMemoryBase */ + Hob =3D GetNextGuidHob ( + &gPlatformHobGuid, + (CONST VOID *)FixedPcdGet64 (PcdSystemMemoryBase) + ); + if (Hob !=3D NULL) { + BuildGuidDataHob ( + &gPlatformHobGuid, + GET_GUID_HOB_DATA (Hob), + GET_GUID_HOB_DATA_SIZE (Hob) + ); + } +} + +EFI_STATUS +EFIAPI +InitializeATFHobPeim ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + BuildPlatformInformationHob (); + + return EFI_SUCCESS; +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryIni= tPeim.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInitPe= im.c new file mode 100644 index 000000000000..4098b4664bf8 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInitPeim.c @@ -0,0 +1,151 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +/* + * The protocols, PPI and GUID defintions for this module + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +MemoryPeim ( + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase, + IN UINT64 UefiMemorySize + ); + +VOID +BuildMemoryTypeInformationHob ( + VOID + ) +{ + EFI_MEMORY_TYPE_INFORMATION Info[10]; + + Info[0].Type =3D EfiACPIReclaimMemory; + Info[0].NumberOfPages =3D PcdGet32 (PcdMemoryTypeEfiACPIReclaimMemory); + Info[1].Type =3D EfiACPIMemoryNVS; + Info[1].NumberOfPages =3D PcdGet32 (PcdMemoryTypeEfiACPIMemoryNVS); + Info[2].Type =3D EfiReservedMemoryType; + Info[2].NumberOfPages =3D PcdGet32 (PcdMemoryTypeEfiReservedMemoryType); + Info[3].Type =3D EfiRuntimeServicesData; + Info[3].NumberOfPages =3D PcdGet32 (PcdMemoryTypeEfiRuntimeServicesData)= ; + Info[4].Type =3D EfiRuntimeServicesCode; + Info[4].NumberOfPages =3D PcdGet32 (PcdMemoryTypeEfiRuntimeServicesCode)= ; + Info[5].Type =3D EfiBootServicesCode; + Info[5].NumberOfPages =3D PcdGet32 (PcdMemoryTypeEfiBootServicesCode); + Info[6].Type =3D EfiBootServicesData; + Info[6].NumberOfPages =3D PcdGet32 (PcdMemoryTypeEfiBootServicesData); + Info[7].Type =3D EfiLoaderCode; + Info[7].NumberOfPages =3D PcdGet32 (PcdMemoryTypeEfiLoaderCode); + Info[8].Type =3D EfiLoaderData; + Info[8].NumberOfPages =3D PcdGet32 (PcdMemoryTypeEfiLoaderData); + + /* Terminator for the list */ + Info[9].Type =3D EfiMaxMemoryType; + Info[9].NumberOfPages =3D 0; + + BuildGuidDataHob (&gEfiMemoryTypeInformationGuid, &Info, sizeof (Info)); +} + +EFI_STATUS +EFIAPI +InitializeMemory ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + UINTN SystemMemoryBase; + UINTN SystemMemoryTop; + UINTN FdBase; + UINTN FdTop; + UINTN UefiMemoryBase; + UINTN Index; + VOID *Hob; + PLATFORM_INFO_HOB *PlatformHob; + + DEBUG ((DEBUG_INFO, "Memory Init PEIM Loaded\n")); + + Hob =3D GetFirstGuidHob (&gPlatformHobGuid); + ASSERT (Hob !=3D NULL); + if (Hob =3D=3D NULL) { + return EFI_DEVICE_ERROR; + } + + PlatformHob =3D (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob); + + /* Find system memory top of the first node */ + SystemMemoryTop =3D 0; + for (Index =3D 0; Index < PlatformHob->DramInfo.NumRegion; Index++) { + if (SystemMemoryTop <=3D PlatformHob->DramInfo.Base[Index] && + PlatformHob->DramInfo.Node[Index] =3D=3D 0 && + (PlatformHob->DramInfo.Base[Index] + + PlatformHob->DramInfo.Size[Index] - 1) <=3D 0xFFFFFFFF) + { + SystemMemoryTop =3D PlatformHob->DramInfo.Base[Index] + PlatformHob-= >DramInfo.Size[Index]; + } + } + + DEBUG ((DEBUG_INFO, "PEIM memory configuration.\n")); + + SystemMemoryBase =3D (UINTN)FixedPcdGet64 (PcdSystemMemoryBase); + FdBase =3D (UINTN)PcdGet64 (PcdFdBaseAddress); + FdTop =3D FdBase + (UINTN)PcdGet32 (PcdFdSize); + + // In case the firmware has been shadowed in the System Memory + if ((FdBase >=3D SystemMemoryBase) && (FdTop <=3D SystemMemoryTop)) { + // + // Check if there is enough space between the top of the system memory= and the top of the + // firmware to place the UEFI memory (for PEI & DXE phases) + // + if (SystemMemoryTop - FdTop >=3D FixedPcdGet32 (PcdSystemMemoryUefiReg= ionSize)) { + UefiMemoryBase =3D SystemMemoryTop - FixedPcdGet32 (PcdSystemMemoryU= efiRegionSize); + } else { + // Check there is enough space for the UEFI memory + ASSERT (SystemMemoryBase + FixedPcdGet32 (PcdSystemMemoryUefiRegionS= ize) <=3D FdBase); + + UefiMemoryBase =3D FdBase - FixedPcdGet32 (PcdSystemMemoryUefiRegion= Size); + } + } else { + // Check the Firmware does not overlapped with the system memory + ASSERT ((FdBase < SystemMemoryBase) || (FdBase >=3D SystemMemoryTop)); + ASSERT ((FdTop <=3D SystemMemoryBase) || (FdTop > SystemMemoryTop)); + + UefiMemoryBase =3D SystemMemoryTop - FixedPcdGet32 (PcdSystemMemoryUef= iRegionSize); + } + + Status =3D PeiServicesInstallPeiMemory ( + UefiMemoryBase, + FixedPcdGet32 (PcdSystemMemoryUefiRegionSize) + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error: Failed to install Pei Memory\n")); + } else { + DEBUG ((DEBUG_INFO, "Info: Installed Pei Memory\n")); + } + ASSERT_EFI_ERROR (Status); + + // Initialize MMU and Memory HOBs (Resource Descriptor HOBs) + Status =3D MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUef= iRegionSize)); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error: Failed to initialize MMU and Memory HOBS\= n")); + } + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLi= b.c b/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.c new file mode 100644 index 000000000000..8da698e0b855 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.c @@ -0,0 +1,706 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +STATIC PLATFORM_INFO_HOB *mPlatformInfoHob =3D NULL; + +PLATFORM_INFO_HOB * +GetPlatformHob ( + VOID + ) +{ + VOID *Hob; + + if (mPlatformInfoHob =3D=3D NULL) { + Hob =3D GetNextGuidHob ( + &gPlatformHobGuid, + (CONST VOID *)FixedPcdGet64 (PcdSystemMemoryBase) + ); + ASSERT (Hob !=3D NULL); + if (Hob =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Failed to get gPlatformHobGuid!\n", __FUNC= TION__)); + return NULL; + } + + mPlatformInfoHob =3D (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob); + } + + return mPlatformInfoHob; +} + +/** + Get the SubNUMA mode. + + @return UINT8 The SubNUMA mode. + +**/ +UINT8 +EFIAPI +CpuGetSubNumaMode ( + VOID + ) +{ + PLATFORM_INFO_HOB *PlatformHob; + + PlatformHob =3D GetPlatformHob (); + if (PlatformHob =3D=3D NULL) { + return SUBNUMA_MODE_MONOLITHIC; + } + + return PlatformHob->SubNumaMode[0]; +} + +/** + Get the number of SubNUMA region. + + @return UINT8 The number of SubNUMA region. + +**/ +UINT8 +EFIAPI +CpuGetNumberOfSubNumaRegion ( + VOID + ) +{ + UINT8 SubNumaMode; + UINT8 NumberOfSubNumaRegion; + + SubNumaMode =3D CpuGetSubNumaMode (); + ASSERT (SubNumaMode <=3D SUBNUMA_MODE_QUADRANT); + + switch (SubNumaMode) { + case SUBNUMA_MODE_MONOLITHIC: + NumberOfSubNumaRegion =3D MONOLITIC_NUM_OF_REGION; + break; + + case SUBNUMA_MODE_HEMISPHERE: + NumberOfSubNumaRegion =3D HEMISPHERE_NUM_OF_REGION; + break; + + case SUBNUMA_MODE_QUADRANT: + NumberOfSubNumaRegion =3D QUADRANT_NUM_OF_REGION; + break; + + default: + // Should never reach there. + ASSERT (FALSE); + break; + } + + return NumberOfSubNumaRegion; +} + +/** + Get the SubNUMA node of a CPM. + + @param SocketId Socket index. + @param Cpm CPM index. + @return UINT8 The SubNUMA node of a CPM. + +**/ +UINT8 +EFIAPI +CpuGetSubNumNode ( + UINT8 SocketId, + UINT16 Cpm + ) +{ + BOOLEAN IsAsymMesh; + UINT8 SubNumaNode; + UINT16 MaxNumberOfCPM; + UINT8 MiddleRow; + UINT8 QuadrantHigherRowNodeNumber[NUM_OF_CPM_PER_MESH_ROW] =3D {1, 1, = 1, 1, 3, 3, 3, 3}; + UINT8 QuadrantLowerRowNodeNumber[NUM_OF_CPM_PER_MESH_ROW] =3D {0, 0, = 0, 0, 2, 2, 2, 2}; + UINT8 QuadrantMiddleRowNodeNumber[NUM_OF_CPM_PER_MESH_ROW] =3D {0, 0, = 1, 1, 3, 3, 2, 2}; + UINT8 SubNumaMode; + + MaxNumberOfCPM =3D GetMaximumNumberOfCPMs (); + SubNumaMode =3D CpuGetSubNumaMode (); + ASSERT (SubNumaMode <=3D SUBNUMA_MODE_QUADRANT); + + switch (SubNumaMode) { + case SUBNUMA_MODE_MONOLITHIC: + SubNumaNode =3D (SocketId =3D=3D 0) ? 0 : 1; + break; + + case SUBNUMA_MODE_HEMISPHERE: + if (CPM_PER_ROW_OFFSET (Cpm) >=3D SUBNUMA_CPM_REGION_SIZE) { + SubNumaNode =3D 1; + } else { + SubNumaNode =3D 0; + } + + if (SocketId =3D=3D 1) { + SubNumaNode +=3D HEMISPHERE_NUM_OF_REGION; + } + break; + + case SUBNUMA_MODE_QUADRANT: + // + // CPM Mesh Rows + // + // |---------------------------------------| + // | 00 ----------- 03 | 04 ----------- 07 | Row 0 + // |-------------------|-------------------| + // | 08 ----------- 11 | 12 ----------- 15 | Row 1 + // |-------------------|-------------------| + // | 16 - 17 | 18 - 19 | 20 - 21 | 22 - 23 | Middle Row + // |-------------------|-------------------| + // | 24 ----------- 27 | 28 ----------- 31 | Row 3 + // |-------------------|-------------------| + // | 32 ----------- 35 | 36 ----------- 39 | Row 4 + // |---------------------------------------| + // + + IsAsymMesh =3D (BOOLEAN)(CPM_ROW_NUMBER (MaxNumberOfCPM) % 2 !=3D 0); + MiddleRow =3D CPM_ROW_NUMBER (MaxNumberOfCPM) / 2; + if (IsAsymMesh + && CPM_ROW_NUMBER (Cpm) =3D=3D MiddleRow) + { + SubNumaNode =3D QuadrantMiddleRowNodeNumber[CPM_PER_ROW_OFFSET (Cpm)= ]; + + } else if (CPM_ROW_NUMBER (Cpm) >=3D MiddleRow) { + SubNumaNode =3D QuadrantHigherRowNodeNumber[CPM_PER_ROW_OFFSET (Cpm)= ]; + + } else { + SubNumaNode =3D QuadrantLowerRowNodeNumber[CPM_PER_ROW_OFFSET (Cpm)]= ; + } + + if (SocketId =3D=3D 1) { + SubNumaNode +=3D QUADRANT_NUM_OF_REGION; + } + break; + + default: + // Should never reach there. + ASSERT (FALSE); + break; + } + + return SubNumaNode; +} + +/** + Get the associativity of cache. + + @param Level Cache level. + @return UINT32 Associativity of cache. + +**/ +UINT32 +EFIAPI +CpuGetAssociativity ( + UINT32 Level + ) +{ + UINT64 CacheCCSIDR; + UINT64 CacheCLIDR; + UINT32 Value =3D 0x2; /* Unknown Set-Associativity */ + + CacheCLIDR =3D ReadCLIDR (); + if (!CLIDR_CTYPE (CacheCLIDR, Level)) { + return Value; + } + + CacheCCSIDR =3D ReadCCSIDR (Level); + switch (CCSIDR_ASSOCIATIVITY (CacheCCSIDR)) { + case 0: + /* Direct mapped */ + Value =3D 0x3; + break; + + case 1: + /* 2-way Set-Associativity */ + Value =3D 0x4; + break; + + case 3: + /* 4-way Set-Associativity */ + Value =3D 0x5; + break; + + case 7: + /* 8-way Set-Associativity */ + Value =3D 0x7; + break; + + case 15: + /* 16-way Set-Associativity */ + Value =3D 0x8; + break; + + case 11: + /* 12-way Set-Associativity */ + Value =3D 0x9; + break; + + case 23: + /* 24-way Set-Associativity */ + Value =3D 0xA; + break; + + case 31: + /* 32-way Set-Associativity */ + Value =3D 0xB; + break; + + case 47: + /* 48-way Set-Associativity */ + Value =3D 0xC; + break; + + case 63: + /* 64-way Set-Associativity */ + Value =3D 0xD; + break; + + case 19: + /* 20-way Set-Associativity */ + Value =3D 0xE; + break; + } + + return Value; +} + +/** + Get the cache size. + + @param Level Cache level. + @return UINT32 Cache size. + +**/ +UINT32 +EFIAPI +CpuGetCacheSize ( + UINT32 Level + ) +{ + UINT32 CacheLineSize; + UINT32 Count; + UINT64 CacheCCSIDR; + UINT64 CacheCLIDR; + + CacheCLIDR =3D ReadCLIDR (); + if (!CLIDR_CTYPE (CacheCLIDR, Level)) { + return 0; + } + + CacheCCSIDR =3D ReadCCSIDR (Level); + CacheLineSize =3D 1; + Count =3D CCSIDR_LINE_SIZE (CacheCCSIDR) + 4; + while (Count-- > 0) { + CacheLineSize *=3D 2; + } + + return ((CCSIDR_NUMSETS (CacheCCSIDR) + 1) * + (CCSIDR_ASSOCIATIVITY (CacheCCSIDR) + 1) * + CacheLineSize); +} + +/** + Get the number of supported socket. + + @return UINT8 Number of supported socket. + +**/ +UINT8 +EFIAPI +GetNumberOfSupportedSockets ( + VOID + ) +{ + PLATFORM_INFO_HOB *PlatformHob; + + PlatformHob =3D GetPlatformHob (); + if (PlatformHob =3D=3D NULL) { + // + // By default, the number of supported sockets is 1. + // + return 1; + } + + return (sizeof (PlatformHob->ClusterEn) / sizeof (PLATFORM_CLUSTER_EN)); +} + +/** + Get the number of active socket. + + @return UINT8 Number of active socket. + +**/ +UINT8 +EFIAPI +GetNumberOfActiveSockets ( + VOID + ) +{ + UINT8 NumberOfActiveSockets, Count, Index, Index1; + PLATFORM_CLUSTER_EN *Socket; + PLATFORM_INFO_HOB *PlatformHob; + + PlatformHob =3D GetPlatformHob (); + if (PlatformHob =3D=3D NULL) { + // + // By default, the number of active sockets is 1. + // + return 1; + } + + NumberOfActiveSockets =3D 0; + + for (Index =3D 0; Index < GetNumberOfSupportedSockets (); Index++) { + Socket =3D &PlatformHob->ClusterEn[Index]; + Count =3D ARRAY_SIZE (Socket->EnableMask); + for (Index1 =3D 0; Index1 < Count; Index1++) { + if (Socket->EnableMask[Index1] !=3D 0) { + NumberOfActiveSockets++; + break; + } + } + } + + return NumberOfActiveSockets; +} + +/** + Get the number of active CPM per socket. + + @param SocketId Socket index. + @return UINT16 Number of CPM. + +**/ +UINT16 +EFIAPI +GetNumberOfActiveCPMsPerSocket ( + UINT8 SocketId + ) +{ + UINT16 NumberOfCPMs, Count, Index; + UINT32 Val32; + PLATFORM_CLUSTER_EN *Socket; + PLATFORM_INFO_HOB *PlatformHob; + + PlatformHob =3D GetPlatformHob (); + if (PlatformHob =3D=3D NULL) { + return 0; + } + + if (SocketId >=3D GetNumberOfActiveSockets ()) { + return 0; + } + + NumberOfCPMs =3D 0; + Socket =3D &PlatformHob->ClusterEn[SocketId]; + Count =3D ARRAY_SIZE (Socket->EnableMask); + for (Index =3D 0; Index < Count; Index++) { + Val32 =3D Socket->EnableMask[Index]; + while (Val32 > 0) { + if ((Val32 & 0x1) !=3D 0) { + NumberOfCPMs++; + } + Val32 >>=3D 1; + } + } + + return NumberOfCPMs; +} + +/** + Get the number of configured CPM per socket. This number + should be the same for all sockets. + + @param SocketId Socket index. + @return UINT8 Number of configured CPM. + +**/ +UINT16 +EFIAPI +GetNumberOfConfiguredCPMs ( + UINT8 SocketId + ) +{ + EFI_STATUS Status; + UINT32 Value; + UINT32 Param, ParamStart, ParamEnd; + UINT16 Count; + + Count =3D 0; + ParamStart =3D NV_SI_S0_PCP_ACTIVECPM_0_31 + SocketId * NV_PARAM_ENTRYSI= ZE * (PLATFORM_CPU_MAX_CPM / 32); + ParamEnd =3D ParamStart + NV_PARAM_ENTRYSIZE * (PLATFORM_CPU_MAX_CPM / 3= 2); + for (Param =3D ParamStart; Param < ParamEnd; Param +=3D NV_PARAM_ENTRYSI= ZE) { + Status =3D NVParamGet ( + Param, + NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC, + &Value + ); + if (EFI_ERROR (Status)) { + break; + } + while (Value !=3D 0) { + if ((Value & 0x01) !=3D 0) { + Count++; + } + Value >>=3D 1; + } + } + + return Count; +} + +/** + Set the number of configured CPM per socket. + + @param SocketId Socket index. + @param NumberOfCPMs Number of CPM to be configured. + @return EFI_SUCCESS Operation succeeded. + @return Others An error has occurred. + +**/ +EFI_STATUS +EFIAPI +SetNumberOfConfiguredCPMs ( + UINT8 SocketId, + UINT16 NumberOfCPMs + ) +{ + EFI_STATUS Status; + UINT32 Value; + UINT32 Param, ParamStart, ParamEnd; + BOOLEAN IsClear; + + IsClear =3D FALSE; + if (NumberOfCPMs =3D=3D 0) { + IsClear =3D TRUE; + } + + Status =3D EFI_SUCCESS; + + ParamStart =3D NV_SI_S0_PCP_ACTIVECPM_0_31 + SocketId * NV_PARAM_ENTRYSI= ZE * (PLATFORM_CPU_MAX_CPM / 32); + ParamEnd =3D ParamStart + NV_PARAM_ENTRYSIZE * (PLATFORM_CPU_MAX_CPM / 3= 2); + for (Param =3D ParamStart; Param < ParamEnd; Param +=3D NV_PARAM_ENTRYSI= ZE) { + if (NumberOfCPMs >=3D 32) { + Value =3D 0xffffffff; + NumberOfCPMs -=3D 32; + } else { + Value =3D 0; + while (NumberOfCPMs > 0) { + Value |=3D (1 << (--NumberOfCPMs)); + } + } + if (IsClear) { + /* Clear this param */ + Status =3D NVParamClr ( + Param, + NV_PERM_BIOS | NV_PERM_MANU + ); + } else { + Status =3D NVParamSet ( + Param, + NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC, + NV_PERM_BIOS | NV_PERM_MANU, + Value + ); + } + } + + return Status; +} + +/** + Get the maximum number of core per socket. + + @return UINT16 Maximum number of core. + +**/ +UINT16 +EFIAPI +GetMaximumNumberOfCores ( + VOID + ) +{ + PLATFORM_INFO_HOB *PlatformHob; + + PlatformHob =3D GetPlatformHob (); + if (PlatformHob =3D=3D NULL) { + return 0; + } + + return PlatformHob->MaxNumOfCore[0]; +} + +/** + Get the maximum number of CPM per socket. This number + should be the same for all sockets. + + @return UINT16 Maximum number of CPM. + +**/ +UINT16 +EFIAPI +GetMaximumNumberOfCPMs ( + VOID + ) +{ + return GetMaximumNumberOfCores () / PLATFORM_CPU_NUM_CORES_PER_CPM; +} + +/** + Get the number of active cores of a sockets. + + @param SocketId Socket Index. + @return UINT16 Number of active core. + +**/ +UINT16 +EFIAPI +GetNumberOfActiveCoresPerSocket ( + UINT8 SocketId + ) +{ + return GetNumberOfActiveCPMsPerSocket (SocketId) * PLATFORM_CPU_NUM_CORE= S_PER_CPM; +} + +/** + Get the number of active cores of all sockets. + + @return UINT16 Number of active core. + +**/ +UINT16 +EFIAPI +GetNumberOfActiveCores ( + VOID + ) +{ + UINT16 NumberOfActiveCores; + UINT8 Index; + + NumberOfActiveCores =3D 0; + + for (Index =3D 0; Index < GetNumberOfActiveSockets (); Index++) { + NumberOfActiveCores +=3D GetNumberOfActiveCoresPerSocket (Index); + } + + return NumberOfActiveCores; +} + +/** + Check if the logical CPU is enabled or not. + + @param CpuId The logical Cpu ID. Started from 0. + @return BOOLEAN TRUE if the Cpu enabled + FALSE if the Cpu disabled. + +**/ +BOOLEAN +EFIAPI +IsCpuEnabled ( + UINT16 CpuId + ) +{ + PLATFORM_CLUSTER_EN *Socket; + PLATFORM_INFO_HOB *PlatformHob; + UINT8 SocketId; + UINT16 ClusterId; + + SocketId =3D SOCKET_ID (CpuId); + ClusterId =3D CLUSTER_ID (CpuId); + + PlatformHob =3D GetPlatformHob (); + if (PlatformHob =3D=3D NULL) { + return FALSE; + } + + if (SocketId >=3D GetNumberOfActiveSockets ()) { + return FALSE; + } + + Socket =3D &PlatformHob->ClusterEn[SocketId]; + if ((Socket->EnableMask[ClusterId / 32] & (1 << (ClusterId % 32))) !=3D = 0) { + return TRUE; + } + + return FALSE; +} + +/** + Check if the slave socket is present + + @return BOOLEAN TRUE if the Slave Cpu is present + FALSE if the Slave Cpu is not present + +**/ +BOOLEAN +EFIAPI +IsSlaveSocketPresent ( + VOID + ) +{ + UINT32 Value; + + Value =3D MmioRead32 (SMPRO_EFUSE_SHADOW0 + CFG2P_OFFSET); + + return ((Value & SLAVE_PRESENT_N) !=3D 0) ? FALSE : TRUE; +} + +/** + Check if the slave socket is active + + @return BOOLEAN TRUE if the Slave CPU Socket is active. + FALSE if the Slave CPU Socket is not active. + +**/ +BOOLEAN +EFIAPI +IsSlaveSocketActive ( + VOID + ) +{ + return (GetNumberOfActiveSockets () > 1) ? TRUE : FALSE; +} + +/** + Check if the CPU product ID is Ac01 + @return BOOLEAN TRUE if the Product ID is Ac01 + FALSE otherwise. + +**/ +BOOLEAN +EFIAPI +IsAc01Processor ( + VOID + ) +{ + PLATFORM_INFO_HOB *PlatformHob; + + PlatformHob =3D GetPlatformHob (); + ASSERT (PlatformHob !=3D NULL); + + if (PlatformHob !=3D NULL) { + if ((PlatformHob->ScuProductId[0] & 0xFF) =3D=3D 0x01) { + return TRUE; + } + } + + return FALSE; +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatfo= rmLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformL= ib.c new file mode 100644 index 000000000000..8c1eb93f00fd --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c @@ -0,0 +1,169 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +ARM_CORE_INFO mArmPlatformMpCoreInfoTable[PLATFORM_CPU_MAX_NUM_CORES]; + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + + @return Return the current Boot Mode of the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Initialize controllers that must setup in the normal world + + This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/Pl= atformPei + in the PEI phase. + +**/ +EFI_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + RETURN_STATUS Status; + UINT64 BaudRate; + UINT32 ReceiveFifoDepth; + EFI_PARITY_TYPE Parity; + UINT8 DataBits; + EFI_STOP_BITS_TYPE StopBits; + + Status =3D EFI_SUCCESS; + + if (FixedPcdGet64 (PcdSerialRegisterBase) !=3D 0) { + /* Debug port should use the same parameters with console */ + BaudRate =3D FixedPcdGet64 (PcdUartDefaultBaudRate); + ReceiveFifoDepth =3D FixedPcdGet32 (PcdUartDefaultReceiveFifoDepth); + Parity =3D (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity); + DataBits =3D FixedPcdGet8 (PcdUartDefaultDataBits); + StopBits =3D (EFI_STOP_BITS_TYPE)FixedPcdGet8 (PcdUartDefaultStopBits)= ; + + /* Initialize uart debug port */ + Status =3D PL011UartInitializePort ( + (UINTN)FixedPcdGet64 (PcdSerialRegisterBase), + FixedPcdGet32 (PL011UartClkInHz), + &BaudRate, + &ReceiveFifoDepth, + &Parity, + &DataBits, + &StopBits + ); + } + + return Status; +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + UINTN mArmPlatformCoreCount; + UINTN ClusterId; + UINTN SocketId; + UINTN Index; + + ASSERT (CoreCount !=3D NULL); + ASSERT (ArmCoreTable !=3D NULL); + ASSERT (*ArmCoreTable !=3D NULL); + + mArmPlatformCoreCount =3D 0; + for (Index =3D 0; Index < PLATFORM_CPU_MAX_NUM_CORES; Index++) { + if (!IsCpuEnabled (Index)) { + continue; + } + SocketId =3D SOCKET_ID (Index); + ClusterId =3D CLUSTER_ID (Index); + mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].ClusterId =3D Socke= tId; + mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].CoreId =3D + (ClusterId << 8) | (Index % PLATFORM_CPU_NUM_CORES_PER_CPM); + mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].MailboxClearAddress= =3D 0; + mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].MailboxClearValue = =3D 0; + mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].MailboxGetAddress = =3D 0; + mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].MailboxSetAddress = =3D 0; + mArmPlatformCoreCount++; + } + + *CoreCount =3D mArmPlatformCoreCount; + + *ArmCoreTable =3D mArmPlatformMpCoreInfoTable; + ASSERT (*ArmCoreTable !=3D NULL); + + return EFI_SUCCESS; +} + +// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is un= defined in the contect of PrePeiCore +EFI_GUID mArmMpCoreInfoPpiGuid =3D ARM_MP_CORE_INFO_PPI_GUID; +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &mArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + }, +}; + +/** + Return the Platform specific PPIs + + This function exposes the Platform Specific PPIs. They can be used by an= y PrePi modules or passed + to the PeiCore by PrePeiCore. + + @param[out] PpiListSize Size in Bytes of the Platform PPI List + @param[out] PpiList Platform PPI List + +**/ +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + ASSERT (PpiListSize !=3D NULL); + ASSERT (PpiList !=3D NULL); + ASSERT (*PpiList !=3D NULL); + + if (ArmIsMpCore ()) { + *PpiListSize =3D sizeof (gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; + } else { + *PpiListSize =3D 0; + *PpiList =3D NULL; + } +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatfo= rmLibMemory.c b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPla= tformLibMemory.c new file mode 100644 index 000000000000..117c9cc56ac2 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLibMe= mory.c @@ -0,0 +1,399 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Number of Virtual Memory Map Descriptors */ +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 50 + +/* DDR attributes */ +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_= BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACH= ED_UNBUFFERED + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR = describing a Physical-to- + Virtual Memory mapping. This array mus= t be ended by a zero-filled + entry + +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + OUT ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap + ) +{ + UINTN Index =3D 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + UINT32 NumRegion; + UINTN Count; + VOID *Hob; + PLATFORM_INFO_HOB *PlatformHob; + + Hob =3D GetFirstGuidHob (&gPlatformHobGuid); + ASSERT (Hob !=3D NULL); + if (Hob =3D=3D NULL) { + return; + } + + PlatformHob =3D (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob); + + ASSERT (VirtualMemoryMap !=3D NULL); + + VirtualMemoryTable =3D (ARM_MEMORY_REGION_DESCRIPTOR *)AllocatePages (EF= I_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY= _MAP_DESCRIPTORS)); + if (VirtualMemoryTable =3D=3D NULL) { + return; + } + + /* For Address space 0x1000_0000_0000 to 0x1001_00FF_FFFF + * - Device memory + */ + VirtualMemoryTable[Index].PhysicalBase =3D 0x100000000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x100000000000ULL; + VirtualMemoryTable[Index].Length =3D 0x102000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* For Address space 0x5000_0000_0000 to 0x5001_00FF_FFFF + * - Device memory + */ + if (IsSlaveSocketActive ()) + { + VirtualMemoryTable[++Index].PhysicalBase =3D 0x500000000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x500000000000ULL; + VirtualMemoryTable[Index].Length =3D 0x101000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _DEVICE; + } + + /* + * - PCIe RCA0 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x300000000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x300000000000ULL; + VirtualMemoryTable[Index].Length =3D 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - 2P/PCIe Socket0 RCA0 32-bit Device memory + * - 1P/PCIe consolidated to RCB2 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x20000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x20000000ULL; + VirtualMemoryTable[Index].Length =3D 0x8000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - PCIe RCA1 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x340000000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x340000000000ULL; + VirtualMemoryTable[Index].Length =3D 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - 2P/PCIe Socket0 RCA1 32-bit Device memory + * - 1P/PCIe consolidated to RCB2 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x28000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x28000000ULL; + VirtualMemoryTable[Index].Length =3D 0x8000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - PCIe RCA2 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x380000000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x380000000000ULL; + VirtualMemoryTable[Index].Length =3D 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - 2P/PCIe Socket0 RCA2 32-bit Device memory + * - 1P/PCIe consolidated to RCB3 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x30000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x30000000ULL; + VirtualMemoryTable[Index].Length =3D 0x8000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - PCIe RCA3 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x3C0000000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x3C0000000000ULL; + VirtualMemoryTable[Index].Length =3D 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - 2P/PCIe Socket0 RCA3 32-bit Device memory + * - 1P/PCIe consolidated to RCB3 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x38000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x38000000ULL; + VirtualMemoryTable[Index].Length =3D 0x8000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - PCIe RCB0 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x200000000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x200000000000ULL; + VirtualMemoryTable[Index].Length =3D 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - 2P/PCIe Socket0 RCB0 32-bit Device memory + * - 1P/PCIe consolidated to RCB0 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x00000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x00000000ULL; + VirtualMemoryTable[Index].Length =3D 0x8000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - PCIe RCB1 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x240000000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x240000000000ULL; + VirtualMemoryTable[Index].Length =3D 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - 2P/PCIe Socket0 RCB1 32-bit Device memory + * - 1P/PCIe consolidated to RCB0 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x08000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x08000000ULL; + VirtualMemoryTable[Index].Length =3D 0x8000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - PCIe RCB2 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x280000000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x280000000000ULL; + VirtualMemoryTable[Index].Length =3D 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - 2P/PCIe Socket0 RCB2 32-bit Device memory + * - 1P/PCIe consolidated to RCB1 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x10000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x10000000ULL; + VirtualMemoryTable[Index].Length =3D 0x8000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - PCIe RCB3 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x2C0000000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x2C0000000000ULL; + VirtualMemoryTable[Index].Length =3D 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - 2P/PCIe Socket0 RCB3 32-bit Device memory + * - 1P/PCIe consolidated to RCB1 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x18000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x18000000ULL; + VirtualMemoryTable[Index].Length =3D 0x8000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + if (IsSlaveSocketActive ()) { + // Slave socket exist + /* + * - PCIe RCA0 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x700000000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x700000000000ULL; + VirtualMemoryTable[Index].Length =3D 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _DEVICE; + + /* + * - PCIe RCA1 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x740000000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x740000000000ULL; + VirtualMemoryTable[Index].Length =3D 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _DEVICE; + + /* + * - PCIe RCA2 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x780000000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x780000000000ULL; + VirtualMemoryTable[Index].Length =3D 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _DEVICE; + + /* + * - PCIe RCA3 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x7C0000000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x7C0000000000ULL; + VirtualMemoryTable[Index].Length =3D 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _DEVICE; + + /* + * - PCIe RCB0 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x600000000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x600000000000ULL; + VirtualMemoryTable[Index].Length =3D 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _DEVICE; + + /* + * - PCIe RCB1 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x640000000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x640000000000ULL; + VirtualMemoryTable[Index].Length =3D 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _DEVICE; + + /* + * - PCIe RCB2 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x680000000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x680000000000ULL; + VirtualMemoryTable[Index].Length =3D 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _DEVICE; + + /* + * - PCIe RCB3 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x6C0000000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x6C0000000000ULL; + VirtualMemoryTable[Index].Length =3D 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _DEVICE; + } + + /* + * - 2P/PCIe Socket1 RCA0 32-bit Device memory + * - 1P/PCIe consolidated to RCA2 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x60000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x60000000ULL; + VirtualMemoryTable[Index].Length =3D 0x8000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - 2P/PCIe Socket1 RCA1 32-bit Device memory + * - 1P/PCIe consolidated to RCA2 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x68000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x68000000ULL; + VirtualMemoryTable[Index].Length =3D 0x8000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - 2P/PCIe Socket1 RCA2 32-bit Device memory + * - 1P/PCIe consolidated to RCA3 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x70000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x70000000ULL; + VirtualMemoryTable[Index].Length =3D 0x8000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - 2P/PCIe Socket1 RCA3 32-bit Device memory + * - 1P/PCIe consolidated to RCA3 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x78000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x78000000ULL; + VirtualMemoryTable[Index].Length =3D 0x8000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - 2P/PCIe Socket1 RCB0 32-bit Device memory + * - 1P/PCIe consolidated to RCA0 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x40000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x40000000ULL; + VirtualMemoryTable[Index].Length =3D 0x8000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - 2P/PCIe Socket1 RCB1 32-bit Device memory + * - 1P/PCIe consolidated to RCA0 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x48000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x48000000ULL; + VirtualMemoryTable[Index].Length =3D 0x8000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - 2P/PCIe Socket1 RCB2 32-bit Device memory + * - 1P/PCIe consolidated to RCA1 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x50000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x50000000ULL; + VirtualMemoryTable[Index].Length =3D 0x8000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - 2P/PCIe Socket1 RCB3 32-bit Device memory + * - 1P/PCIe consolidated to RCA1 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x58000000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x58000000ULL; + VirtualMemoryTable[Index].Length =3D 0x8000000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - BERT memory region + */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0x88230000ULL; + VirtualMemoryTable[Index].VirtualBase =3D 0x88230000ULL; + VirtualMemoryTable[Index].Length =3D 0x50000ULL; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + /* + * - DDR memory region + */ + NumRegion =3D PlatformHob->DramInfo.NumRegion; + Count =3D 0; + while (NumRegion-- > 0) { + if (PlatformHob->DramInfo.NvdRegion[Count]) { /* Skip NVDIMM Region */ + Count++; + continue; + } + + VirtualMemoryTable[++Index].PhysicalBase =3D PlatformHob->DramInfo.Bas= e[Count]; + VirtualMemoryTable[Index].VirtualBase =3D PlatformHob->DramInfo.Base[= Count]; + VirtualMemoryTable[Index].Length =3D PlatformHob->DramInfo.Size[= Count]; + VirtualMemoryTable[Index].Attributes =3D DDR_ATTRIBUTES_CACHED; + Count++; + } + + /* SPM MM NS Buffer for MmCommunicateDxe */ + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdMmBufferBase); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdMmBufferBase); + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdMmBufferSize); + VirtualMemoryTable[Index].Attributes =3D DDR_ATTRIBUTES_CACHED; + + /* End of Table */ + VirtualMemoryTable[++Index].PhysicalBase =3D 0; + VirtualMemoryTable[Index].VirtualBase =3D 0; + VirtualMemoryTable[Index].Length =3D 0; + VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRIBUTES= )0; + + ASSERT ((Index + 1) <=3D MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap =3D VirtualMemoryTable; +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/MailboxInterfaceLib/Mail= boxInterfaceLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/MailboxInterfaceL= ib/MailboxInterfaceLib.c new file mode 100644 index 000000000000..0da1f90699f6 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/MailboxInterfaceLib/MailboxInte= rfaceLib.c @@ -0,0 +1,282 @@ +/** @file + The library implements the hardware Mailbox (Doorbell) interface for com= munication + between the Application Processor (ARMv8) and the System Control Process= ors (SMpro/PMpro). + + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include + +// +// Hardware Doorbells +// +#define SMPRO_DB0_IRQ_OFST 40 +#define SMPRO_DB0_BASE_ADDRESS (FixedPcdGet64 (PcdSmproDbBaseReg= )) + +#define PMPRO_DB0_IRQ_OFST 56 +#define PMPRO_DB0_BASE_ADDRESS (FixedPcdGet64 (PcdPmproDbBaseReg= )) + +#define SLAVE_SOCKET_BASE_ADDRESS_OFFSET 0x400000000000 + +// +// The base SPI interrupt number of the Slave socket +// +#define SLAVE_SOCKET_SPI_INTERRUPT 352 + +#define SLAVE_SOCKET_DOORBELL_INTERRUPT_BASE(Socket) ((Socket) * SLAVE_SOC= KET_SPI_INTERRUPT - 32) + +// +// Doorbell base register stride size +// +#define DB_BASE_REG_STRIDE 0x00001000 + +#define SMPRO_DBx_ADDRESS(socket, db) \ + ((socket) * SLAVE_SOCKET_BASE_ADDRESS_OFFSET + SMPRO_DB0_BASE_ADDR= ESS + DB_BASE_REG_STRIDE * (db)) + +#define PMPRO_DBx_ADDRESS(socket, db) \ + ((socket) * SLAVE_SOCKET_BASE_ADDRESS_OFFSET + PMPRO_DB0_BASE_ADDR= ESS + DB_BASE_REG_STRIDE * (db)) + +// +// Doorbell Status Bits +// +#define DB_STATUS_AVAIL_BIT BIT16 +#define DB_STATUS_ACK_BIT BIT0 + +/** + Get the base address of a doorbell. + + @param[in] Socket Active socket index. + @param[in] Doorbell Doorbell channel for communication with th= e SMpro/PMpro. + + @retval UINT32 The base address of the doorbell. + The returned value is 0 indicate that the = input parameters are invalid. + +**/ +UINTN +EFIAPI +MailboxGetDoorbellAddress ( + IN UINT8 Socket, + IN DOORBELL_CHANNELS Doorbell + ) +{ + UINTN DoorbellAddress; + + if (Socket >=3D GetNumberOfActiveSockets () + || Doorbell >=3D NUMBER_OF_DOORBELLS_PER_SOCKET) + { + return 0; + } + + if (Doorbell >=3D SMproDoorbellChannel0) { + DoorbellAddress =3D SMPRO_DBx_ADDRESS (Socket, (UINT8)(Doorbell - SMpr= oDoorbellChannel0)); + } else { + DoorbellAddress =3D PMPRO_DBx_ADDRESS (Socket, (UINT8)Doorbell); + } + + return DoorbellAddress; +} + +/** + Get the interrupt number of a doorbell. + + @param[in] Socket Active socket index. + @param[in] Doorbell Doorbell channel for communication with th= e SMpro/PMpro. + + @retval UINT32 The interrupt number. + The returned value is 0 indicate that the = input parameters are invalid. + +**/ +UINT32 +EFIAPI +MailboxGetDoorbellInterruptNumber ( + IN UINT8 Socket, + IN DOORBELL_CHANNELS Doorbell + ) +{ + UINT32 DoorbellInterruptNumber; + + if (Socket >=3D GetNumberOfActiveSockets () + || Doorbell >=3D NUMBER_OF_DOORBELLS_PER_SOCKET) + { + return 0; + } + + DoorbellInterruptNumber =3D 0; + + if (Socket > 0) { + DoorbellInterruptNumber =3D SLAVE_SOCKET_DOORBELL_INTERRUPT_BASE (Sock= et); + } + + if (Doorbell >=3D SMproDoorbellChannel0) { + DoorbellInterruptNumber +=3D SMPRO_DB0_IRQ_OFST + (UINT8)(Doorbell - S= MproDoorbellChannel0); + } else { + DoorbellInterruptNumber +=3D PMPRO_DB0_IRQ_OFST + (UINT8)Doorbell; + } + + return DoorbellInterruptNumber; +} + +/** + Read a message via the hardware Doorbell interface. + + @param[in] Socket Active socket index. + @param[in] Doorbell Doorbell channel for communication with th= e SMpro/PMpro. + @param[out] Message Pointer to the Mailbox message. + + @retval EFI_SUCCESS Read the message successfully. + @retval EFI_TIMEOUT Timeout occurred when waiting for availabl= e message in the mailbox. + @retval EFI_INVALID_PARAMETER A parameter is invalid. +**/ +EFI_STATUS +EFIAPI +MailboxRead ( + IN UINT8 Socket, + IN DOORBELL_CHANNELS Doorbell, + OUT MAILBOX_MESSAGE_DATA *Message + ) +{ + UINTN TimeoutCount; + UINTN DoorbellAddress; + + if (Socket >=3D GetNumberOfActiveSockets () + || Doorbell >=3D NUMBER_OF_DOORBELLS_PER_SOCKET + || Message =3D=3D NULL) + { + return EFI_INVALID_PARAMETER; + } + + TimeoutCount =3D MAILBOX_POLL_COUNT; + + DoorbellAddress =3D MailboxGetDoorbellAddress (Socket, Doorbell); + ASSERT (DoorbellAddress !=3D 0); + + // + // Polling Doorbell status + // + while ((MmioRead32 ((DoorbellAddress + DB_STATUS_REG_OFST)) & DB_STATUS_= AVAIL_BIT) =3D=3D 0) { + MicroSecondDelay (MAILBOX_POLL_INTERVAL_US); + if (--TimeoutCount =3D=3D 0) { + return EFI_TIMEOUT; + } + } + + Message->ExtendedData[0] =3D MmioRead32 (DoorbellAddress + DB_DIN0_REG_O= FST); + Message->ExtendedData[1] =3D MmioRead32 (DoorbellAddress + DB_DIN1_REG_O= FST); + Message->Data =3D MmioRead32 (DoorbellAddress + DB_IN_REG_OFST); + + // + // Write 1 to clear the AVAIL status + // + MmioWrite32 (DoorbellAddress + DB_STATUS_REG_OFST, DB_STATUS_AVAIL_BIT); + + return EFI_SUCCESS; +} + +/** + Write a message via the hardware Doorbell interface. + + @param[in] Socket Active socket index. + @param[in] Doorbell Doorbel channel for communication with the= SMpro/PMpro. + @param[in] Message Pointer to the Mailbox message. + + @retval EFI_SUCCESS Write the message successfully. + @retval EFI_TIMEOUT Timeout occurred when waiting for acknowle= dge signal from the mailbox. + @retval EFI_INVALID_PARAMETER A parameter is invalid. +**/ +EFI_STATUS +EFIAPI +MailboxWrite ( + IN UINT8 Socket, + IN DOORBELL_CHANNELS Doorbell, + IN MAILBOX_MESSAGE_DATA *Message + ) +{ + UINTN TimeoutCount; + UINTN DoorbellAddress; + + if (Socket >=3D GetNumberOfActiveSockets () + || Doorbell >=3D NUMBER_OF_DOORBELLS_PER_SOCKET + || Message =3D=3D NULL) + { + return EFI_INVALID_PARAMETER; + } + + TimeoutCount =3D MAILBOX_POLL_COUNT; + + DoorbellAddress =3D MailboxGetDoorbellAddress (Socket, Doorbell); + ASSERT (DoorbellAddress !=3D 0); + + // + // Clear previous pending ack if any + // + if ((MmioRead32 (DoorbellAddress + DB_STATUS_REG_OFST) & DB_STATUS_ACK_B= IT) !=3D 0) { + MmioWrite32 (DoorbellAddress + DB_STATUS_REG_OFST, DB_STATUS_ACK_BIT); + } + + // + // Send message + // + MmioWrite32 (DoorbellAddress + DB_DOUT0_REG_OFST, Message->ExtendedData[= 0]); + MmioWrite32 (DoorbellAddress + DB_DOUT1_REG_OFST, Message->ExtendedData[= 1]); + MmioWrite32 (DoorbellAddress + DB_OUT_REG_OFST, Message->Data); + + // + // Wait for ACK + // + while ((MmioRead32 (DoorbellAddress + DB_STATUS_REG_OFST) & DB_STATUS_AC= K_BIT) =3D=3D 0) { + MicroSecondDelay (MAILBOX_POLL_INTERVAL_US); + if (--TimeoutCount =3D=3D 0) { + return EFI_TIMEOUT; + } + } + + // + // Write 1 to clear the ACK status + // + MmioWrite32 (DoorbellAddress + DB_STATUS_REG_OFST, DB_STATUS_ACK_BIT); + + return EFI_SUCCESS; +} + +/** + Unmask the Doorbell interrupt status. + + @param Socket Active socket index. + @param Doorbell Doorbel channel for communication with the SMpro/PMpro= . + + @retval EFI_SUCCESS Unmask the Doorbell interrupt successfull= y. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + +**/ +EFI_STATUS +EFIAPI +MailboxUnmaskInterrupt ( + IN UINT8 Socket, + IN UINT16 Doorbell + ) +{ + UINTN DoorbellAddress; + + if (Socket >=3D GetNumberOfActiveSockets () + || Doorbell >=3D NUMBER_OF_DOORBELLS_PER_SOCKET) + { + return EFI_INVALID_PARAMETER; + } + + DoorbellAddress =3D MailboxGetDoorbellAddress (Socket, Doorbell); + ASSERT (DoorbellAddress !=3D 0); + + MmioWrite32 (DoorbellAddress + DB_STATUS_MASK_REG_OFST, ~DB_STATUS_AVAIL= _BIT); + + return EFI_SUCCESS; +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryI= nitPeiLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/Memory= InitPeiLib.c new file mode 100644 index 000000000000..edf8925d5a1e --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiL= ib.c @@ -0,0 +1,93 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include + +STATIC +VOID +InitMmu ( + IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable + ) +{ + VOID *TranslationTableBase; + UINTN TranslationTableSize; + RETURN_STATUS Status; + + // Note: Because we called PeiServicesInstallPeiMemory() before to call = InitMmu() + // the MMU Page Table resides in DRAM (even at the top of DRAM as it is = the first + // permanent memory allocation) + // + Status =3D ArmConfigureMmu (MemoryTable, &TranslationTableBase, &Transla= tionTableSize); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error: Failed to enable MMU\n")); + } + + BuildMemoryAllocationHob ( + (EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, + EFI_SIZE_TO_PAGES (TranslationTableSize) * EFI_PAGE_SIZE, + EfiBootServicesData + ); +} + +EFI_STATUS +EFIAPI +MemoryPeim ( + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase, + IN UINT64 UefiMemorySize + ) +{ + ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable; + UINTN Index; + + /* Get Virtual Memory Map from the Platform Library */ + ArmPlatformGetVirtualMemoryMap (&MemoryTable); + + Index =3D 0; + while (MemoryTable[Index].Length !=3D 0) { + if (MemoryTable[Index].Attributes =3D=3D ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK) { + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryTable[Index].PhysicalBase, + MemoryTable[Index].Length + ); + } else if (MemoryTable[Index].Attributes =3D=3D ARM_MEMORY_REGION_ATTR= IBUTE_DEVICE) { + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED, + MemoryTable[Index].PhysicalBase, + MemoryTable[Index].Length + ); + } + Index++; + } + + BuildMemoryAllocationHob ( + PcdGet64 (PcdFdBaseAddress), + PcdGet32 (PcdFdSize), + EfiRuntimeServicesData + ); + + InitMmu (MemoryTable); + + return EFI_SUCCESS; +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCom= municationLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/= MmCommunicationLib.c new file mode 100644 index 000000000000..bf400ec0a835 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicat= ionLib.c @@ -0,0 +1,184 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Address, Length of the pre-allocated buffer for communication with the = secure +// world. +// +STATIC ARM_MEMORY_REGION_DESCRIPTOR mNsCommBuffMemRegion; + +EFI_STATUS +EFIAPI +MmCommunicationLibConstructor ( + VOID + ) +{ + mNsCommBuffMemRegion.PhysicalBase =3D PcdGet64 (PcdMmBufferBase); + // During boot , Virtual and Physical are same + mNsCommBuffMemRegion.VirtualBase =3D mNsCommBuffMemRegion.PhysicalBase; + mNsCommBuffMemRegion.Length =3D PcdGet64 (PcdMmBufferSize); + + return EFI_SUCCESS; +} + +/** + Communicates with a registered handler. + + This function provides an interface to send and receive messages to the + Standalone MM environment in UEFI PEI phase. + + @param[in, out] CommBuffer A pointer to the buffer to convey + into MMRAM. + @param[in, out] CommSize The size of the data buffer being + passed in. This is optional. + + @retval EFI_SUCCESS The message was successfully posted. + @retval EFI_INVALID_PARAMETER The CommBuffer was NULL. + @retval EFI_BAD_BUFFER_SIZE The buffer size is incorrect for the= MM + implementation. If this error is + returned, the MessageLength field in + the CommBuffer header or the integer + pointed by CommSize are updated to r= eflect + the maximum payload size the + implementation can accommodate. + @retval EFI_ACCESS_DENIED The CommunicateBuffer parameter + or CommSize parameter, if not omitte= d, + are in address range that cannot be + accessed by the MM environment +**/ +EFI_STATUS +EFIAPI +MmCommunicationCommunicate ( + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommSize OPTIONAL + ) +{ + EFI_MM_COMMUNICATE_HEADER *CommunicateHeader; + ARM_SMC_ARGS CommunicateSmcArgs; + EFI_STATUS Status; + UINTN BufferSize; + + Status =3D EFI_ACCESS_DENIED; + BufferSize =3D 0; + + ZeroMem (&CommunicateSmcArgs, sizeof (ARM_SMC_ARGS)); + + // + // Check parameters + // + if (CommBuffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + CommunicateHeader =3D CommBuffer; + // CommBuffer is a mandatory parameter. Hence, Rely on + // MessageLength + Header to ascertain the + // total size of the communication payload rather than + // rely on optional CommSize parameter + BufferSize =3D CommunicateHeader->MessageLength + + sizeof (CommunicateHeader->HeaderGuid) + + sizeof (CommunicateHeader->MessageLength); + + // If the length of the CommBuffer is 0 then return the expected length. + if (CommSize !=3D NULL) { + // This case can be used by the consumer of this driver to find out th= e + // max size that can be used for allocating CommBuffer. + if ((*CommSize =3D=3D 0) || + (*CommSize > mNsCommBuffMemRegion.Length)) + { + *CommSize =3D mNsCommBuffMemRegion.Length; + return EFI_BAD_BUFFER_SIZE; + } + // + // CommSize must match MessageLength + sizeof (EFI_MM_COMMUNICATE_HEAD= ER); + // + if (*CommSize !=3D BufferSize) { + return EFI_INVALID_PARAMETER; + } + } + + // + // If the buffer size is 0 or greater than what can be tolerated by the = MM + // environment then return the expected size. + // + if ((BufferSize =3D=3D 0) || + (BufferSize > mNsCommBuffMemRegion.Length)) + { + CommunicateHeader->MessageLength =3D mNsCommBuffMemRegion.Length - + sizeof (CommunicateHeader->HeaderGu= id) - + sizeof (CommunicateHeader->MessageL= ength); + return EFI_BAD_BUFFER_SIZE; + } + + // SMC Function ID + CommunicateSmcArgs.Arg0 =3D ARM_SMC_ID_MM_COMMUNICATE_AARCH64; + + // Cookie + CommunicateSmcArgs.Arg1 =3D 0; + + // Copy Communication Payload + CopyMem ((VOID *)mNsCommBuffMemRegion.VirtualBase, CommBuffer, BufferSiz= e); + + // comm_buffer_address (64-bit physical address) + CommunicateSmcArgs.Arg2 =3D (UINTN)mNsCommBuffMemRegion.PhysicalBase; + + // comm_size_address (not used, indicated by setting to zero) + CommunicateSmcArgs.Arg3 =3D 0; + + // Call the Standalone MM environment. + ArmCallSmc (&CommunicateSmcArgs); + + switch (CommunicateSmcArgs.Arg0) { + case ARM_SMC_MM_RET_SUCCESS: + ZeroMem (CommBuffer, BufferSize); + // On successful return, the size of data being returned is inferred f= rom + // MessageLength + Header. + CommunicateHeader =3D (EFI_MM_COMMUNICATE_HEADER *)mNsCommBuffMemRegio= n.VirtualBase; + BufferSize =3D CommunicateHeader->MessageLength + + sizeof (CommunicateHeader->HeaderGuid) + + sizeof (CommunicateHeader->MessageLength); + + CopyMem ( + CommBuffer, + (VOID *)mNsCommBuffMemRegion.VirtualBase, + BufferSize + ); + Status =3D EFI_SUCCESS; + break; + + case ARM_SMC_MM_RET_INVALID_PARAMS: + Status =3D EFI_INVALID_PARAMETER; + break; + + case ARM_SMC_MM_RET_DENIED: + Status =3D EFI_ACCESS_DENIED; + break; + + case ARM_SMC_MM_RET_NO_MEMORY: + // Unexpected error since the CommSize was checked for zero length + // prior to issuing the SMC + Status =3D EFI_OUT_OF_RESOURCES; + ASSERT (0); + break; + + default: + Status =3D EFI_ACCESS_DENIED; + ASSERT (0); + } + + return Status; +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.c = b/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.c new file mode 100644 index 000000000000..794a0a77c25f --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.c @@ -0,0 +1,202 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +EFI_MM_COMM_REQUEST mCommBuffer; + +STATIC VOID +UefiMmCreateNVParamReq ( + IN VOID *Data, + IN UINT64 Size + ) +{ + CopyGuid (&mCommBuffer.EfiMmHdr.HeaderGuid, &gNVParamMmGuid); + mCommBuffer.EfiMmHdr.MsgLength =3D Size; + + if (Size !=3D 0) { + ASSERT (Data); + ASSERT (Size <=3D EFI_MM_MAX_PAYLOAD_SIZE); + + CopyMem (mCommBuffer.PayLoad.Data, Data, Size); + } +} + +EFI_STATUS +NVParamGet ( + IN UINT32 Param, + IN UINT16 ACLRd, + OUT UINT32 *Val + ) +{ + EFI_STATUS Status; + EFI_MM_COMMUNICATE_NVPARAM_RES *MmNVParamRes; + UINT64 MmData[5]; + UINTN Size; + + MmData[0] =3D MM_NVPARAM_FUNC_READ; + MmData[1] =3D Param; + MmData[2] =3D (UINT64)ACLRd; + + UefiMmCreateNVParamReq ((VOID *)&MmData, sizeof (MmData)); + + Size =3D sizeof (EFI_MM_COMM_HEADER_NOPAYLOAD) + sizeof (MmData); + Status =3D MmCommunicationCommunicate ( + (VOID *)&mCommBuffer, + &Size + ); + if (EFI_ERROR (Status)) { + return Status; + } + + MmNVParamRes =3D (EFI_MM_COMMUNICATE_NVPARAM_RES *)&mCommBuffer.PayLoad; + switch (MmNVParamRes->Status) { + case MM_NVPARAM_RES_SUCCESS: + *Val =3D (UINT32)MmNVParamRes->Value; + return EFI_SUCCESS; + + case MM_NVPARAM_RES_NOT_SET: + return EFI_NOT_FOUND; + + case MM_NVPARAM_RES_NO_PERM: + return EFI_ACCESS_DENIED; + + case MM_NVPARAM_RES_FAIL: + return EFI_DEVICE_ERROR; + + default: + return EFI_INVALID_PARAMETER; + } +} + +EFI_STATUS +NVParamSet ( + IN UINT32 Param, + IN UINT16 ACLRd, + IN UINT16 ACLWr, + IN UINT32 Val + ) +{ + EFI_STATUS Status; + EFI_MM_COMMUNICATE_NVPARAM_RES *MmNVParamRes; + UINT64 MmData[5]; + UINTN Size; + + MmData[0] =3D MM_NVPARAM_FUNC_WRITE; + MmData[1] =3D Param; + MmData[2] =3D (UINT64)ACLRd; + MmData[3] =3D (UINT64)ACLWr; + MmData[4] =3D (UINT64)Val; + + UefiMmCreateNVParamReq ((VOID *)&MmData, sizeof (MmData)); + Size =3D sizeof (EFI_MM_COMM_HEADER_NOPAYLOAD) + sizeof (MmData); + Status =3D MmCommunicationCommunicate ( + (VOID *)&mCommBuffer, + &Size + ); + if (EFI_ERROR (Status)) { + return Status; + } + + MmNVParamRes =3D (EFI_MM_COMMUNICATE_NVPARAM_RES *)&mCommBuffer.PayLoad; + switch (MmNVParamRes->Status) { + case MM_NVPARAM_RES_SUCCESS: + return EFI_SUCCESS; + + case MM_NVPARAM_RES_NO_PERM: + return EFI_ACCESS_DENIED; + + case MM_NVPARAM_RES_FAIL: + return EFI_DEVICE_ERROR; + + default: + return EFI_INVALID_PARAMETER; + } +} + +EFI_STATUS +NVParamClr ( + IN UINT32 Param, + IN UINT16 ACLWr + ) +{ + EFI_STATUS Status; + EFI_MM_COMMUNICATE_NVPARAM_RES *MmNVParamRes; + UINT64 MmData[5]; + UINTN Size; + + MmData[0] =3D MM_NVPARAM_FUNC_CLEAR; + MmData[1] =3D Param; + MmData[2] =3D 0; + MmData[3] =3D (UINT64)ACLWr; + + UefiMmCreateNVParamReq ((VOID *)&MmData, sizeof (MmData)); + Size =3D sizeof (EFI_MM_COMM_HEADER_NOPAYLOAD) + sizeof (MmData); + Status =3D MmCommunicationCommunicate ( + (VOID *)&mCommBuffer, + &Size + ); + if (EFI_ERROR (Status)) { + return Status; + } + + MmNVParamRes =3D (EFI_MM_COMMUNICATE_NVPARAM_RES *)&mCommBuffer.PayLoad; + switch (MmNVParamRes->Status) { + case MM_NVPARAM_RES_SUCCESS: + return EFI_SUCCESS; + + case MM_NVPARAM_RES_NO_PERM: + return EFI_ACCESS_DENIED; + + case MM_NVPARAM_RES_FAIL: + return EFI_DEVICE_ERROR; + + default: + return EFI_INVALID_PARAMETER; + } +} + +EFI_STATUS +NVParamClrAll ( + VOID + ) +{ + EFI_STATUS Status; + EFI_MM_COMMUNICATE_NVPARAM_RES *MmNVParamRes; + UINT64 MmData[5]; + UINTN Size; + + MmData[0] =3D MM_NVPARAM_FUNC_CLEAR_ALL; + + UefiMmCreateNVParamReq ((VOID *)&MmData, sizeof (MmData)); + Size =3D sizeof (EFI_MM_COMM_HEADER_NOPAYLOAD) + sizeof (MmData); + Status =3D MmCommunicationCommunicate ( + (VOID *)&mCommBuffer, + &Size + ); + if (EFI_ERROR (Status)) { + return Status; + } + + MmNVParamRes =3D (EFI_MM_COMMUNICATE_NVPARAM_RES *)&mCommBuffer.PayLoad; + switch (MmNVParamRes->Status) { + case MM_NVPARAM_RES_SUCCESS: + return EFI_SUCCESS; + + case MM_NVPARAM_RES_FAIL: + return EFI_DEVICE_ERROR; + + default: + return EFI_INVALID_PARAMETER; + } +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/PlatformPeiLib/PlatformP= eiLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/PlatformPeiLib/PlatformPeiL= ib.c new file mode 100644 index 000000000000..3ae3ecd60719 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/PlatformPeiLib/PlatformPeiLib.c @@ -0,0 +1,40 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +PlatformPeim ( + VOID + ) +{ + UINT64 FvMainBase; + UINT32 FvMainSize; + + // Build FV_MAIN Hand-off block (HOB) to let DXE IPL pick up correctly + FvMainBase =3D FixedPcdGet64 (PcdFvBaseAddress); + FvMainSize =3D FixedPcdGet32 (PcdFvSize); + ASSERT (FvMainSize !=3D 0); + + BuildFvHob (FvMainBase, FvMainSize); + + return EFI_SUCCESS; +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.c b/Silico= n/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.c new file mode 100644 index 000000000000..f7e6fb6092a6 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.c @@ -0,0 +1,141 @@ +/** @file + + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include + +/** + Generates a 16-bit random number. + + if Rand is NULL, then ASSERT(). + + @param[out] Rand Buffer pointer to store the 16-bit random value. + + @retval TRUE Random number generated successfully. + @retval FALSE Failed to generate the random number. + +**/ +BOOLEAN +EFIAPI +GetRandomNumber16 ( + OUT UINT16 *Rand + ) +{ + EFI_STATUS Status; + + ASSERT (Rand !=3D NULL); + if (Rand =3D=3D NULL) { + return FALSE; + } + + Status =3D GenerateRandomNumbers ((UINT8 *)Rand, sizeof (UINT16)); + if (EFI_ERROR (Status)) { + return FALSE; + } + + return TRUE; +} + +/** + Generates a 32-bit random number. + + if Rand is NULL, then ASSERT(). + + @param[out] Rand Buffer pointer to store the 32-bit random value. + + @retval TRUE Random number generated successfully. + @retval FALSE Failed to generate the random number. + +**/ +BOOLEAN +EFIAPI +GetRandomNumber32 ( + OUT UINT32 *Rand + ) +{ + EFI_STATUS Status; + + ASSERT (Rand !=3D NULL); + if (Rand =3D=3D NULL) { + return FALSE; + } + + Status =3D GenerateRandomNumbers ((UINT8 *)Rand, sizeof (UINT32)); + if (EFI_ERROR (Status)) { + return FALSE; + } + + return TRUE; +} + +/** + Generates a 64-bit random number. + + if Rand is NULL, then ASSERT(). + + @param[out] Rand Buffer pointer to store the 64-bit random value. + + @retval TRUE Random number generated successfully. + @retval FALSE Failed to generate the random number. + +**/ +BOOLEAN +EFIAPI +GetRandomNumber64 ( + OUT UINT64 *Rand + ) +{ + EFI_STATUS Status; + + ASSERT (Rand !=3D NULL); + if (Rand =3D=3D NULL) { + return FALSE; + } + + Status =3D GenerateRandomNumbers ((UINT8 *)Rand, sizeof (UINT64)); + if (EFI_ERROR (Status)) { + return FALSE; + } + + return TRUE; +} + +/** + Generates a 128-bit random number. + + if Rand is NULL, then ASSERT(). + + @param[out] Rand Buffer pointer to store the 128-bit random value. + + @retval TRUE Random number generated successfully. + @retval FALSE Failed to generate the random number. + +**/ +BOOLEAN +EFIAPI +GetRandomNumber128 ( + OUT UINT64 *Rand + ) +{ + EFI_STATUS Status; + + ASSERT (Rand !=3D NULL); + if (Rand =3D=3D NULL) { + return FALSE; + } + + Status =3D GenerateRandomNumbers ((UINT8 *)Rand, 2 * sizeof (UINT64)); + if (EFI_ERROR (Status)) { + return FALSE; + } + + return TRUE; +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/SystemFirmwareInterfaceL= ib/SystemFirmwareInterfaceLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/Sys= temFirmwareInterfaceLib/SystemFirmwareInterfaceLib.c new file mode 100644 index 000000000000..9cab653418fb --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/SystemFirmwareInterfaceLib/Syst= emFirmwareInterfaceLib.c @@ -0,0 +1,328 @@ +/** @file + Provides functions for communication with System Firmware (SMpro/PMpro a= nd ATF). + + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include + +/** + Read a register which is not accessible from the non-secure world + by sending a mailbox message to the SMpro processor. + + Note that not all addresses are allowed. + + @param[in] Socket Active socket index. + @param[in] Address A 64-bit register address to be read. + @param[out] Value A pointer to the read value. + + @retval EFI_SUCCESS Read the register successfully. + @retval EFI_UNSUPPORTED The register is not allowed. + @retval Otherwise Errors returned from MailboxWrite/MailboxR= ead() functions. +**/ +EFI_STATUS +EFIAPI +MailboxMsgRegisterRead ( + IN UINT8 Socket, + IN UINTN Address, + OUT UINT32 *Value + ) +{ + EFI_STATUS Status; + MAILBOX_MESSAGE_DATA Message; + UINT32 AddressLower32Bit; + UINT32 AddressUpper32Bit; + + if (Socket >=3D GetNumberOfActiveSockets ()) { + return EFI_INVALID_PARAMETER; + } + + AddressLower32Bit =3D (UINT32)(Address & 0xFFFFFFFF); + AddressUpper32Bit =3D (UINT32)RShiftU64 ((UINT64)Address, 32); + + Message.Data =3D MAILBOX_DEBUG_MESSAGE_ENCODE ( + MAILBOX_DEBUG_MESSAGE_SUBTYPE_REGISTER_READ, + (UINT16)(AddressUpper32Bit & 0xFFFF) + ); + + Message.ExtendedData[0] =3D AddressLower32Bit; + Message.ExtendedData[1] =3D 0; + + Status =3D MailboxWrite (Socket, SMproDoorbellChannel0, &Message); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D MailboxRead (Socket, SMproDoorbellChannel0, &Message); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return Status; + } + + if ((Message.Data & 0xFF00) =3D=3D 0) { + return EFI_UNSUPPORTED; + } + + if (Value !=3D NULL) { + *Value =3D Message.ExtendedData[0]; + } + + return EFI_SUCCESS; +} + +/** + Write a value to a register which is not accessible from the non-secure = world + by sending a mailbox message to the SMpro processor. + + Note that not all addresses are allowed. + + @param[in] Socket Active socket index. + @param[in] Address A 64-bit register address to be written. + @param[in] Value The value to be written to the register. + + @retval EFI_SUCCESS Write the register successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval Otherwise Errors returned from the MailboxWrite() functio= n. +**/ +EFI_STATUS +EFIAPI +MailboxMsgRegisterWrite ( + IN UINT8 Socket, + IN UINTN Address, + IN UINT32 Value + ) +{ + EFI_STATUS Status; + MAILBOX_MESSAGE_DATA Message; + UINT32 AddressLower32Bit; + UINT32 AddressUpper32Bit; + + if (Socket >=3D GetNumberOfActiveSockets ()) { + return EFI_INVALID_PARAMETER; + } + + AddressLower32Bit =3D (UINT32)(Address & 0xFFFFFFFF); + AddressUpper32Bit =3D (UINT32)RShiftU64 ((UINT64)Address, 32); + + Message.Data =3D MAILBOX_DEBUG_MESSAGE_ENCODE ( + MAILBOX_DEBUG_MESSAGE_SUBTYPE_REGISTER_WRITE, + (UINT16)(AddressUpper32Bit & 0xFFFF) + ); + + Message.ExtendedData[0] =3D AddressLower32Bit; + Message.ExtendedData[1] =3D Value; + + Status =3D MailboxWrite (Socket, SMproDoorbellChannel0, &Message); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + Set the PCC shared Memory Address to service handlers in the System Cont= rol Processors, + using for communication between the System Firmware and OSPM. + + @param[in] Socket Active socket index. + @param[in] Doorbell Doorbell index which is numbered like DOORB= ELL_CHANNELS. + @param[in] AddressAlign256 Enable/Disable 256 alignment. + @param[in] Address The shared memory address. + + @retval EFI_SUCCESS Set the shared memory address successfully= . + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval Otherwise Errors returned from the MailboxWrite() fu= nctions. +**/ +EFI_STATUS +EFIAPI +MailboxMsgSetPccSharedMem ( + IN UINT8 Socket, + IN UINT8 Doorbell, + IN BOOLEAN AddressAlign256, + IN UINTN Address + ) +{ + EFI_STATUS Status; + MAILBOX_MESSAGE_DATA Message; + UINT8 AlignBit; + UINT8 AlignControl; + + if (Socket >=3D GetNumberOfActiveSockets () || Doorbell >=3D NUMBER_OF_D= OORBELLS_PER_SOCKET) { + return EFI_INVALID_PARAMETER; + } + + if (AddressAlign256) { + AlignBit =3D 8; + AlignControl =3D MAILBOX_ADDRESS_256_ALIGNMENT; + } else { + AlignBit =3D 0; + AlignControl =3D MAILBOX_ADDRESS_NO_ALIGNMENT; + } + + Message.Data =3D MAILBOX_ADDRESS_MESSAGE_ENCODE ( + MAILBOX_ADDRESS_MESSAGE_SUBTYPE_PCC, + 0, + AlignControl + ); + + Message.ExtendedData[0] =3D (UINT32)(RShiftU64 ((UINT64)Address, AlignBi= t) & 0xFFFFFFFF); + Message.ExtendedData[1] =3D (UINT32)(RShiftU64 ((UINT64)Address, 32 + Al= ignBit)); + + Status =3D MailboxWrite (Socket, Doorbell, &Message); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + The True RNG is provided by the SMpro processor. This function is to sen= d a mailbox + message to the SMpro to request a 64-bit random number. + + @param[out] Buffer A pointer to the read 64-bit random number= . + + @retval EFI_SUCCESS The operation succeeds. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval Otherwise Errors returned from the MailboxWrite/Mail= boxRead() functions. +**/ +EFI_STATUS +EFIAPI +MailboxMsgGetRandomNumber64 ( + OUT UINT8 *Buffer + ) +{ + EFI_STATUS Status; + MAILBOX_MESSAGE_DATA Message; + + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + Message.Data =3D MAILBOX_USER_MESSAGE_ENCODE ( + MAILBOX_USER_MESSAGE_SUBTYPE_TRNG_PROXY, + MAILBOX_TRNG_PROXY_GET_RANDOM_NUMBER, + 0 + ); + Message.ExtendedData[0] =3D 0; + Message.ExtendedData[1] =3D 0; + + Status =3D MailboxWrite (0, SMproDoorbellChannel6, &Message); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D MailboxRead (0, SMproDoorbellChannel6, &Message); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return Status; + } + + CopyMem (Buffer, &Message.ExtendedData[0], sizeof (UINT32)); + CopyMem (Buffer + sizeof (UINT32), &Message.ExtendedData[1], sizeof (UIN= T32)); + + return EFI_SUCCESS; +} + +/** + Report the UEFI boot progress to the SMpro. + + @param[in] Socket Active socket index. + @param[in] BootStatus The status of the UEFI boot. + @param[in] Checkpoint The UEFI Checkpoint value. + + @retval EFI_SUCCESS Set the boot progress successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval Otherwise Errors returned from the MailboxWrite() fu= nctions. +**/ +EFI_STATUS +EFIAPI +MailboxMsgSetBootProgress ( + IN UINT8 Socket, + IN UINT8 BootStatus, + IN UINT32 Checkpoint + ) +{ + EFI_STATUS Status; + MAILBOX_MESSAGE_DATA Message; + + if (Socket >=3D GetNumberOfActiveSockets ()) { + return EFI_INVALID_PARAMETER; + } + + Message.Data =3D MAILBOX_USER_MESSAGE_ENCODE ( + MAILBOX_USER_MESSAGE_SUBTYPE_BOOT_PROGRESS, + MAILBOX_BOOT_PROGRESS_COMMAND_SET, + MAILBOX_BOOT_PROGRESS_STAGE_UEFI + ); + + // + // Extended Data Format for Boot Progress Set + // + // Data 0: + // Bit 31:16 - Boot Status + // Bit 15:0 - UEFI Checkpoint lower 16-bit + // + // Data 1: + // Bit 31:16 - Unused + // Bit 15:0 - UEFI Checkpoint upper 16-bit + // + Message.ExtendedData[0] =3D ((UINT32)BootStatus & 0xFFFF) | (((UINT32)Ch= eckpoint << 16) & 0xFFFF0000); + Message.ExtendedData[1] =3D (Checkpoint >> 16) & 0xFFFF; + + Status =3D MailboxWrite (Socket, SMproDoorbellChannel1, &Message); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + Configure the Turbo (Max Performance) mode. + + @param[in] Socket Active socket index. + @param[in] Enable Enable/Disable the Turbo (Max performance) = mode. + + @retval EFI_SUCCESS Configure the Turbo successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval Otherwise Errors returned from the MailboxWrite() fu= nctions. +**/ +EFI_STATUS +EFIAPI +MailboxMsgTurboConfig ( + IN UINT8 Socket, + IN BOOLEAN Enable + ) +{ + EFI_STATUS Status; + MAILBOX_MESSAGE_DATA Message; + + if (Socket >=3D GetNumberOfSupportedSockets ()) { + return EFI_INVALID_PARAMETER; + } + + Message.Data =3D MAILBOX_USER_MESSAGE_ENCODE ( + MAILBOX_USER_MESSAGE_SUBTYPE_SET_CONFIGURATION, + MAILBOX_SET_CONFIGURATION_TURBO, + 0 + ); + + // + // The Turbo configuration is written into the extended data 0. + // The extended data 1 is unused. + // + Message.ExtendedData[0] =3D Enable ? 1 : 0; + Message.ExtendedData[1] =3D 0; + + Status =3D MailboxWrite (Socket, PMproDoorbellChannel1, &Message); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/TrngLib/TrngLib.c b/Sili= con/Ampere/AmpereAltraPkg/Library/TrngLib/TrngLib.c new file mode 100644 index 000000000000..55250ddcb86d --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/TrngLib/TrngLib.c @@ -0,0 +1,63 @@ +/** @file + + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include + +/** + Generates a random number by using Hardware RNG in SMpro. + + @param[out] Buffer Buffer to receive the random number. + @param[in] BufferSize Number of bytes in Buffer. + + @retval EFI_SUCCESS The random value was returned successfully= . + @retval EFI_DEVICE_ERROR A random value could not be retrieved + due to a hardware or firmware error. + @retval EFI_INVALID_PARAMETER Buffer is NULL or BufferSize is zero. +**/ +EFI_STATUS +EFIAPI +GenerateRandomNumbers ( + OUT UINT8 *Buffer, + IN UINTN BufferSize + ) +{ + UINTN Count; + UINTN RandSize; + UINT64 Value; + EFI_STATUS Status; + + if ((BufferSize =3D=3D 0) || (Buffer =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + // + // SMpro only supports generating a 64-bits random number once. + // + RandSize =3D sizeof (UINT64); + for (Count =3D 0; Count < (BufferSize / sizeof (UINT64)) + 1; Count++) { + if (Count =3D=3D (BufferSize / sizeof (UINT64))) { + RandSize =3D BufferSize % sizeof (UINT64); + } + + if (RandSize !=3D 0) { + Status =3D MailboxMsgGetRandomNumber64 ((UINT8 *)&Value); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to get random number!\n", __FUNCT= ION__)); + return EFI_DEVICE_ERROR; + } + CopyMem (Buffer + Count * sizeof (UINT64), &Value, RandSize); + } + } + + return EFI_SUCCESS; +} diff --git a/Platform/Ampere/AmperePlatformPkg/FvRules.fdf.inc b/Platform/A= mpere/AmperePlatformPkg/FvRules.fdf.inc new file mode 100644 index 000000000000..027b3cf6dee4 --- /dev/null +++ b/Platform/Ampere/AmperePlatformPkg/FvRules.fdf.inc @@ -0,0 +1,176 @@ +## @file +# +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Rules are used with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are = the default +# rules for the different module type. User can add the customized rules t= o define the +# content of the FFS file. +# +##########################################################################= ###### + +##########################################################################= ## +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section = # +##########################################################################= ## +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER =3D $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_= NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING=3D"$(MODULE_NAME)" Optional +# VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_N= UMBER) +# } +# } +# } +# +##########################################################################= ## + + +[Rule.Common.SEC] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED FIXED { + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE =3D $(NAMED_GUID) FIXED { + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM =3D $(NAMED_GUID) FIXED { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.Binary] + FILE PEIM =3D $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional |.depex + TE TE Align =3D Auto |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM =3D $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED =3D TR= UE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE =3D $(NAMED_GUID) { + COMPRESS PI_STD { + GUIDED { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).e= fi + UI STRING=3D"$(MODULE_NAME)" Optional + } + } + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + COMPRESS PI_STD { + GUIDED { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).e= fi + UI STRING=3D"$(MODULE_NAME)" Optional + } + } + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + COMPRESS PI_STD { + GUIDED { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).e= fi + UI STRING=3D"$(MODULE_NAME)" Optional + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + } + } + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + COMPRESS PI_STD { + GUIDED { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).e= fi + UI STRING=3D"$(MODULE_NAME)" Optional + } + } + } + +[Rule.Common.DXE_RUNTIME_DRIVER.Binary] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + COMPRESS PI_STD { + GUIDED { + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + } + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION =3D $(NAMED_GUID) { + COMPRESS PI_STD { + GUIDED { + UI STRING =3D"$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).e= fi + } + } + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + COMPRESS PI_STD { + GUIDED { + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_N= UMBER) + } + } + } + +[Rule.Common.UEFI_DRIVER.Binary] + FILE DRIVER =3D $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NU= MBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + } + +[Rule.Common.PEIM.FMP_IMAGE_DESC] + FILE PEIM =3D $(NAMED_GUID) { + RAW BIN |.acpi + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depe= x + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).ef= i + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } diff --git a/Platform/Ampere/JadePkg/JadeBoardSetting.cfg b/Platform/Ampere= /JadePkg/JadeBoardSetting.cfg new file mode 100644 index 000000000000..5a67e8fc6a75 --- /dev/null +++ b/Platform/Ampere/JadePkg/JadeBoardSetting.cfg @@ -0,0 +1,209 @@ +# Sample board setting +# +# This is a sample board setting as used for the +# Ampere Altra reference design. +# +# Name, offset (hex), value +# value can be hex or decimal +# + +NV_SI_RO_BOARD_VENDOR, 0x0000, 0x0000CD3A +NV_SI_RO_BOARD_TYPE, 0x0008, 0x00000000 +NV_SI_RO_BOARD_REV, 0x0010, 0x00000000 +NV_SI_RO_BOARD_CFG, 0x0018, 0x00000000 +NV_SI_RO_BOARD_S0_DIMM_AVAIL, 0x0020, 0x0000FFFF +NV_SI_RO_BOARD_S1_DIMM_AVAIL, 0x0028, 0x0000FFFF +NV_SI_RO_BOARD_SPI0CS0_FREQ_KHZ, 0x0030, 0x000080E8 +NV_SI_RO_BOARD_SPI0CS1_FREQ_KHZ, 0x0038, 0x000080E8 +NV_SI_RO_BOARD_SPI1CS0_FREQ_KHZ, 0x0040, 0x00002710 +NV_SI_RO_BOARD_SPI1CS1_FREQ_KHZ, 0x0048, 0x00002710 +NV_SI_RO_BOARD_TPM_LOC, 0x0050, 0x00000000 +NV_SI_RO_BOARD_I2C0_FREQ_KHZ, 0x0058, 0x00000190 +NV_SI_RO_BOARD_I2C1_FREQ_KHZ, 0x0060, 0x00000190 +NV_SI_RO_BOARD_I2C2_10_FREQ_KHZ, 0x0068, 0x00000190 +NV_SI_RO_BOARD_I2C3_FREQ_KHZ, 0x0070, 0x00000190 +NV_SI_RO_BOARD_I2C9_FREQ_KHZ, 0x0078, 0x00000190 +NV_SI_RO_BOARD_2P_CFG, 0x0080, 0xFFFFFF01 +NV_SI_RO_BOARD_S0_RCA0_CFG, 0x0088, 0x00000000 +NV_SI_RO_BOARD_S0_RCA1_CFG, 0x0090, 0x00000000 +NV_SI_RO_BOARD_S0_RCA2_CFG, 0x0098, 0x00000004 +NV_SI_RO_BOARD_S0_RCA3_CFG, 0x00A0, 0x00000004 +NV_SI_RO_BOARD_S0_RCB0_LO_CFG, 0x00A8, 0x00020002 +NV_SI_RO_BOARD_S0_RCB0_HI_CFG, 0x00B0, 0x00020002 +NV_SI_RO_BOARD_S0_RCB1_LO_CFG, 0x00B8, 0x00020002 +NV_SI_RO_BOARD_S0_RCB1_HI_CFG, 0x00C0, 0x00020002 +NV_SI_RO_BOARD_S0_RCB2_LO_CFG, 0x00C8, 0x00020002 +NV_SI_RO_BOARD_S0_RCB2_HI_CFG, 0x00D0, 0x00000003 +NV_SI_RO_BOARD_S0_RCB3_LO_CFG, 0x00D8, 0x00000003 +NV_SI_RO_BOARD_S0_RCB3_HI_CFG, 0x00E0, 0x00020002 +NV_SI_RO_BOARD_S1_RCA0_CFG, 0x00E8, 0x00000000 +NV_SI_RO_BOARD_S1_RCA1_CFG, 0x00F0, 0x00000000 +NV_SI_RO_BOARD_S1_RCA2_CFG, 0x00F8, 0x02020202 +NV_SI_RO_BOARD_S1_RCA3_CFG, 0x0100, 0x00030003 +NV_SI_RO_BOARD_S1_RCB0_LO_CFG, 0x0108, 0x00000003 +NV_SI_RO_BOARD_S1_RCB0_HI_CFG, 0x0110, 0x00020002 +NV_SI_RO_BOARD_S1_RCB1_LO_CFG, 0x0118, 0x00020002 +NV_SI_RO_BOARD_S1_RCB1_HI_CFG, 0x0120, 0x00000003 +NV_SI_RO_BOARD_S1_RCB2_LO_CFG, 0x0128, 0x00020002 +NV_SI_RO_BOARD_S1_RCB2_HI_CFG, 0x0130, 0x00020002 +NV_SI_RO_BOARD_S1_RCB3_LO_CFG, 0x0138, 0x00020002 +NV_SI_RO_BOARD_S1_RCB3_HI_CFG, 0x0140, 0x00020002 +NV_SI_RO_BOARD_T_LTLM_DELTA_P0, 0x0148, 0x00000001 +NV_SI_RO_BOARD_T_LTLM_DELTA_P1, 0x0150, 0x00000002 +NV_SI_RO_BOARD_T_LTLM_DELTA_P2, 0x0158, 0x00000003 +NV_SI_RO_BOARD_T_LTLM_DELTA_P3, 0x0160, 0x00000004 +NV_SI_RO_BOARD_T_LTLM_DELTA_M1, 0x0168, 0xFFFFFFFF +NV_SI_RO_BOARD_T_LTLM_DELTA_M2, 0x0170, 0xFFFFFFFE +NV_SI_RO_BOARD_T_LTLM_DELTA_M3, 0x0178, 0xFFFFFFFD +NV_SI_RO_BOARD_P_LM_PID_P, 0x0180, 0x00000000 +NV_SI_RO_BOARD_P_LM_PID_I, 0x0188, 0x00000000 +NV_SI_RO_BOARD_P_LM_PID_I_L_THOLD, 0x0190, 0x00000000 +NV_SI_RO_BOARD_P_LM_PID_I_H_THOLD, 0x0198, 0x00000000 +NV_SI_RO_BOARD_P_LM_PID_D, 0x01A0, 0x00000000 +NV_SI_RO_BOARD_P_LM_EXP_SMOOTH_CONST, 0x01A8, 0x00000000 +NV_SI_RO_BOARD_TPM_ALG_ID, 0x01B0, 0x00000002 +NV_SI_RO_BOARD_DDR_SPEED_GRADE, 0x01B8, 0x00000C80 +NV_SI_RO_BOARD_DDR_S0_RTT_WR, 0x01C0, 0x00020000 +NV_SI_RO_BOARD_DDR_S1_RTT_WR, 0x01C8, 0x00020000 +NV_SI_RO_BOARD_DDR_S0_RTT_NOM, 0x01D0, 0xFF060177 +NV_SI_RO_BOARD_DDR_S1_RTT_NOM, 0x01D8, 0xFF060177 +NV_SI_RO_BOARD_DDR_S0_RTT_PARK, 0x01E0, 0x00060070 +NV_SI_RO_BOARD_DDR_S1_RTT_PARK, 0x01E8, 0x00060070 +NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_1DPC, 0x01F0, 0x00000000 +NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_1DPC, 0x01F8, 0x00000000 +NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_1DPC, 0x0200, 0x00000000 +NV_SI_RO_BOARD_DDR_CS3_RDODT_MASK_1DPC, 0x0208, 0x00000000 +NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_2DPC, 0x0210, 0x000C0CCC +NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_2DPC, 0x0218, 0x000C0CCC +NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_2DPC, 0x0220, 0x00030333 +NV_SI_RO_BOARD_DDR_CS3_RDODT_MASK_2DPC, 0x0228, 0x00030333 +NV_SI_RO_BOARD_DDR_CS0_WRODT_MASK_1DPC, 0x0230, 0x00030333 +NV_SI_RO_BOARD_DDR_CS1_WRODT_MASK_1DPC, 0x0238, 0x00030333 +NV_SI_RO_BOARD_DDR_CS2_WRODT_MASK_1DPC, 0x0240, 0x00030333 +NV_SI_RO_BOARD_DDR_CS3_WRODT_MASK_1DPC, 0x0248, 0x00030333 +NV_SI_RO_BOARD_DDR_CS0_WRODT_MASK_2DPC, 0x0250, 0x000EDEED +NV_SI_RO_BOARD_DDR_CS1_WRODT_MASK_2DPC, 0x0258, 0x000DEDDE +NV_SI_RO_BOARD_DDR_CS2_WRODT_MASK_2DPC, 0x0260, 0x000B7BB7 +NV_SI_RO_BOARD_DDR_CS3_WRODT_MASK_2DPC, 0x0268, 0x0007B77B +NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_CTRL_1DPC, 0x0270, 0x00000005 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_VAL_1DPC, 0x0278, 0x0090DD90 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_CTRL_1DPC, 0x0280, 0x00000005 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_VAL_1DPC, 0x0288, 0x0090DD90 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_CTRL_2DPC, 0x0290, 0x00000005 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_VAL_2DPC, 0x0298, 0x0090DD90 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_CTRL_2DPC, 0x02A0, 0x00000005 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_VAL_2DPC, 0x02A8, 0x0090DD90 +NV_SI_RO_BOARD_DDR_PHY_VREFDQ_RANGE_VAL_1DPC, 0x02B0, 0x00000024 +NV_SI_RO_BOARD_DDR_DRAM_VREFDQ_RANGE_VAL_1DPC, 0x02B8, 0x0000001A +NV_SI_RO_BOARD_DDR_PHY_VREFDQ_RANGE_VAL_2DPC, 0x02C0, 0x00000050 +NV_SI_RO_BOARD_DDR_DRAM_VREFDQ_RANGE_VAL_2DPC, 0x02C8, 0x00000020 +NV_SI_RO_BOARD_DDR_CLK_WRDQ_DLY_DEFAULT, 0x02D0, 0x02800280 +NV_SI_RO_BOARD_DDR_RDDQS_DQ_DLY_DEFAULT, 0x02D8, 0x90909090 +NV_SI_RO_BOARD_DDR_WRDQS_SHIFT_DEFAULT, 0x02E0, 0x00000000 +NV_SI_RO_BOARD_DDR_ADCMD_DLY_DEFAULT, 0x02E8, 0x00C000C0 +NV_SI_RO_BOARD_DDR_CLK_WRDQ_DLY_ADJ, 0x02F0, 0x00000000 +NV_SI_RO_BOARD_DDR_RDDQS_DQ_DLY_ADJ, 0x02F8, 0x00000000 +NV_SI_RO_BOARD_DDR_PHY_VREF_ADJ, 0x0300, 0x00000000 +NV_SI_RO_BOARD_DDR_DRAM_VREF_ADJ, 0x0308, 0x00000000 +NV_SI_RO_BOARD_DDR_WR_PREAMBLE_CYCLE, 0x0310, 0x02010201 +NV_SI_RO_BOARD_DDR_ADCMD_2T_MODE, 0x0318, 0x00000000 +NV_SI_RO_BOARD_I2C_VRD_CONFIG_INFO, 0x0320, 0x00000000 +NV_SI_RO_BOARD_DDR_PHY_FEATURE_CTRL, 0x0328, 0x00000000 +NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_ACCESS, 0x0330, 0x01050106 +NV_SI_RO_BOARD_DIMM_TEMP_THRESHOLD, 0x0338, 0x000005F4 +NV_SI_RO_BOARD_DIMM_SPD_COMPARE_DISABLE, 0x0340, 0x00000000 +NV_SI_RO_BOARD_S0_PCIE_CLK_CFG, 0x0348, 0x00000000 +NV_SI_RO_BOARD_S0_RCA4_CFG, 0x0350, 0x02020202 +NV_SI_RO_BOARD_S0_RCA5_CFG, 0x0358, 0x02020202 +NV_SI_RO_BOARD_S0_RCA6_CFG, 0x0360, 0x02020202 +NV_SI_RO_BOARD_S0_RCA7_CFG, 0x0368, 0x02020003 +NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET, 0x0370, 0x00000000 +NV_SI_RO_BOARD_S0_RCA1_TXRX_G3PRESET, 0x0378, 0x00000000 +NV_SI_RO_BOARD_S0_RCA2_TXRX_G3PRESET, 0x0380, 0x00000000 +NV_SI_RO_BOARD_S0_RCA3_TXRX_G3PRESET, 0x0388, 0x00000000 +NV_SI_RO_BOARD_S0_RCB0A_TXRX_G3PRESET, 0x0390, 0x00000000 +NV_SI_RO_BOARD_S0_RCB0B_TXRX_G3PRESET, 0x0398, 0x00000000 +NV_SI_RO_BOARD_S0_RCB1A_TXRX_G3PRESET, 0x03A0, 0x00000000 +NV_SI_RO_BOARD_S0_RCB1B_TXRX_G3PRESET, 0x03A8, 0x00000000 +NV_SI_RO_BOARD_S0_RCB2A_TXRX_G3PRESET, 0x03B0, 0x00000000 +NV_SI_RO_BOARD_S0_RCB2B_TXRX_G3PRESET, 0x03B8, 0x00000000 +NV_SI_RO_BOARD_S0_RCB3A_TXRX_G3PRESET, 0x03C0, 0x00000000 +NV_SI_RO_BOARD_S0_RCB3B_TXRX_G3PRESET, 0x03C8, 0x00000000 +NV_SI_RO_BOARD_S0_RCA4_TXRX_G3PRESET, 0x03D0, 0x00000000 +NV_SI_RO_BOARD_S0_RCA5_TXRX_G3PRESET, 0x03D8, 0x00000000 +NV_SI_RO_BOARD_S0_RCA6_TXRX_G3PRESET, 0x03E0, 0x00000000 +NV_SI_RO_BOARD_S0_RCA7_TXRX_G3PRESET, 0x03E8, 0x00000000 +NV_SI_RO_BOARD_S0_RCA0_TXRX_G4PRESET, 0x03F0, 0x57575757 +NV_SI_RO_BOARD_S0_RCA1_TXRX_G4PRESET, 0x03F8, 0x57575757 +NV_SI_RO_BOARD_S0_RCA2_TXRX_G4PRESET, 0x0400, 0x57575757 +NV_SI_RO_BOARD_S0_RCA3_TXRX_G4PRESET, 0x0408, 0x57575757 +NV_SI_RO_BOARD_S0_RCB0A_TXRX_G4PRESET, 0x0410, 0x57575757 +NV_SI_RO_BOARD_S0_RCB0B_TXRX_G4PRESET, 0x0418, 0x57575757 +NV_SI_RO_BOARD_S0_RCB1A_TXRX_G4PRESET, 0x0420, 0x57575757 +NV_SI_RO_BOARD_S0_RCB1B_TXRX_G4PRESET, 0x0428, 0x57575757 +NV_SI_RO_BOARD_S0_RCB2A_TXRX_G4PRESET, 0x0430, 0x57575757 +NV_SI_RO_BOARD_S0_RCB2B_TXRX_G4PRESET, 0x0438, 0x57575757 +NV_SI_RO_BOARD_S0_RCB3A_TXRX_G4PRESET, 0x0440, 0x57575757 +NV_SI_RO_BOARD_S0_RCB3B_TXRX_G4PRESET, 0x0448, 0x57575757 +NV_SI_RO_BOARD_S0_RCA4_TXRX_G4PRESET, 0x0450, 0x57575757 +NV_SI_RO_BOARD_S0_RCA5_TXRX_G4PRESET, 0x0458, 0x57575757 +NV_SI_RO_BOARD_S0_RCA6_TXRX_G4PRESET, 0x0460, 0x57575757 +NV_SI_RO_BOARD_S0_RCA7_TXRX_G4PRESET, 0x0468, 0x57575757 +NV_SI_RO_BOARD_S1_PCIE_CLK_CFG, 0x0470, 0x00000000 +NV_SI_RO_BOARD_S1_RCA4_CFG, 0x0478, 0x02020202 +NV_SI_RO_BOARD_S1_RCA5_CFG, 0x0480, 0x02020202 +NV_SI_RO_BOARD_S1_RCA6_CFG, 0x0488, 0x02020202 +NV_SI_RO_BOARD_S1_RCA7_CFG, 0x0490, 0x02020003 +NV_SI_RO_BOARD_S1_RCA2_TXRX_G3PRESET, 0x0498, 0x00000000 +NV_SI_RO_BOARD_S1_RCA3_TXRX_G3PRESET, 0x04A0, 0x00000000 +NV_SI_RO_BOARD_S1_RCB0A_TXRX_G3PRESET, 0x04A8, 0x00000000 +NV_SI_RO_BOARD_S1_RCB0B_TXRX_G3PRESET, 0x04B0, 0x00000000 +NV_SI_RO_BOARD_S1_RCB1A_TXRX_G3PRESET, 0x04B8, 0x00000000 +NV_SI_RO_BOARD_S1_RCB1B_TXRX_G3PRESET, 0x04C0, 0x00000000 +NV_SI_RO_BOARD_S1_RCB2A_TXRX_G3PRESET, 0x04C8, 0x00000000 +NV_SI_RO_BOARD_S1_RCB2B_TXRX_G3PRESET, 0x04D0, 0x00000000 +NV_SI_RO_BOARD_S1_RCB3A_TXRX_G3PRESET, 0x04D8, 0x00000000 +NV_SI_RO_BOARD_S1_RCB3B_TXRX_G3PRESET, 0x04E0, 0x00000000 +NV_SI_RO_BOARD_S1_RCA4_TXRX_G3PRESET, 0x04E8, 0x00000000 +NV_SI_RO_BOARD_S1_RCA5_TXRX_G3PRESET, 0x04F0, 0x00000000 +NV_SI_RO_BOARD_S1_RCA6_TXRX_G3PRESET, 0x04F8, 0x00000000 +NV_SI_RO_BOARD_S1_RCA7_TXRX_G3PRESET, 0x0500, 0x00000000 +NV_SI_RO_BOARD_S1_RCA2_TXRX_G4PRESET, 0x0508, 0x57575757 +NV_SI_RO_BOARD_S1_RCA3_TXRX_G4PRESET, 0x0510, 0x57575757 +NV_SI_RO_BOARD_S1_RCB0A_TXRX_G4PRESET, 0x0518, 0x57575757 +NV_SI_RO_BOARD_S1_RCB0B_TXRX_G4PRESET, 0x0520, 0x57575757 +NV_SI_RO_BOARD_S1_RCB1A_TXRX_G4PRESET, 0x0528, 0x57575757 +NV_SI_RO_BOARD_S1_RCB1B_TXRX_G4PRESET, 0x0530, 0x57575757 +NV_SI_RO_BOARD_S1_RCB2A_TXRX_G4PRESET, 0x0538, 0x57575757 +NV_SI_RO_BOARD_S1_RCB2B_TXRX_G4PRESET, 0x0540, 0x57575757 +NV_SI_RO_BOARD_S1_RCB3A_TXRX_G4PRESET, 0x0548, 0x57575757 +NV_SI_RO_BOARD_S1_RCB3B_TXRX_G4PRESET, 0x0550, 0x57575757 +NV_SI_RO_BOARD_S1_RCA4_TXRX_G4PRESET, 0x0558, 0x57575757 +NV_SI_RO_BOARD_S1_RCA5_TXRX_G4PRESET, 0x0560, 0x57575757 +NV_SI_RO_BOARD_S1_RCA6_TXRX_G4PRESET, 0x0568, 0x57575757 +NV_SI_RO_BOARD_S1_RCA7_TXRX_G4PRESET, 0x0570, 0x57575757 +NV_SI_RO_BOARD_2P_CE_MASK_THRESHOLD, 0x0578, 0x00000003 +NV_SI_RO_BOARD_2P_CE_MASK_INTERVAL, 0x0580, 0x000001A4 +NV_SI_RO_BOARD_SX_PHY_CFG_SETTING, 0x0588, 0x00000000 +NV_SI_RO_BOARD_DDR_PHY_DC_CLK, 0x0590, 0x00018000 +NV_SI_RO_BOARD_DDR_PHY_DC_DATA, 0x0598, 0x80018000 +NV_SI_RO_BOARD_SX_RCA0_TXRX_20GPRESET, 0x05A0, 0x00000000 +NV_SI_RO_BOARD_SX_RCA1_TXRX_20GPRESET, 0x05A8, 0x00000000 +NV_SI_RO_BOARD_SX_RCA2_TXRX_20GPRESET, 0x05B0, 0x00000000 +NV_SI_RO_BOARD_SX_RCA3_TXRX_20GPRESET, 0x05B8, 0x00000000 +NV_SI_RO_BOARD_SX_RCA0_TXRX_25GPRESET, 0x05C0, 0x00000000 +NV_SI_RO_BOARD_SX_RCA1_TXRX_25GPRESET, 0x05C8, 0x00000000 +NV_SI_RO_BOARD_SX_RCA2_TXRX_25GPRESET, 0x05D0, 0x00000000 +NV_SI_RO_BOARD_SX_RCA3_TXRX_25GPRESET, 0x05D8, 0x00000000 +NV_SI_RO_BOARD_DDR_2X_REFRESH_TEMP_THRESHOLD, 0x05E0, 0x00550055 +NV_SI_RO_BOARD_PCP_VRD_VOUT_WAIT_US, 0x05E8, 0x00000064 +NV_SI_RO_BOARD_PCP_VRD_VOUT_RESOLUTION_MV, 0x05F0, 0x00000005 +NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_EN, 0x05F8, 0x00000001 +NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_TIME, 0x0600, 0x00000002 +NV_SI_RO_BOARD_DVFS_VOUT_20MV_RAMP_TIME_US, 0x0608, 0x00000005 +NV_SI_RO_BOARD_PCIE_AER_FW_FIRST, 0x0610, 0x00000000 +NV_SI_RO_BOARD_RTC_GPI_LOCK_BYPASS, 0x0618, 0x00000000 +NV_SI_RO_BOARD_TPM_DISABLE, 0x0620, 0x00000000 +NV_SI_RO_BOARD_MESH_S0_CXG_RC_STRONG_ORDERING_EN, 0x0628, 0x00000000 +NV_SI_RO_BOARD_MESH_S1_CXG_RC_STRONG_ORDERING_EN, 0x0630, 0x00000000 +NV_SI_RO_BOARD_GPIO_SW_WATCHDOG_EN, 0x0638, 0x00000000 diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatfo= rmHelper.S b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatfo= rmHelper.S new file mode 100755 index 000000000000..770aa9424eed --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformHelpe= r.S @@ -0,0 +1,45 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + * Derived from edk2/ArmPlatformPkg/Library/ArmPlatformLibNull/AArch64/Arm= PlatformHelper.S + **/ + +#include +#include + +ASM_FUNC(ArmPlatformPeiBootAction) + ret + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore)) + ret + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformIsPrimaryCore) + ldr x0, =3D0x1 + ret + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformGetCorePosition) + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #7 + ret + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.uni b/Sili= con/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.uni new file mode 100644 index 000000000000..dac06405dd58 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.uni @@ -0,0 +1,13 @@ +// /** @file +// Instance of RNG (Random Number Generator) Library. +// +// Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Instance of RNG L= ibrary" + +#string STR_MODULE_DESCRIPTION #language en-US "RngLib that uses = Hardware RNG module from SMpro to generate random numbers." --=20 2.17.1