[edk2-non-osi][PATCH v3 1/2] AmpereAltraBinPkg: Add PciePhyLib library and header

["Vu Nguyen" <vunguyen@os.amperecomputing.com>]

Provide functions to initialize PCIe PHY on Ampere Altra processor.

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Vu Nguyen <vunguyen@os.amperecomputing.com>
---
 Silicon/Ampere/License.txt                                         |  25 +++++
 Silicon/Ampere/AmpereAltraBinPkg/AmpereAltraBinPkg.dec             |  16 +++
 Silicon/Ampere/AmpereAltraBinPkg/Library/PciePhyLib/PciePhyLib.inf |  23 ++++
 Silicon/Ampere/AmpereAltraBinPkg/Include/Library/PciePhyLib.h      | 111 ++++++++++++++++++++
 4 files changed, 175 insertions(+)

diff --git a/Silicon/Ampere/License.txt b/Silicon/Ampere/License.txt
new file mode 100644
index 000000000000..27b640bf5ce2
--- /dev/null
+++ b/Silicon/Ampere/License.txt
@@ -0,0 +1,25 @@
+Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+1. Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in
+   the documentation and/or other materials provided with the
+   distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
diff --git a/Silicon/Ampere/AmpereAltraBinPkg/AmpereAltraBinPkg.dec b/Silicon/Ampere/AmpereAltraBinPkg/AmpereAltraBinPkg.dec
new file mode 100644
index 000000000000..32fcd6f6b9d4
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraBinPkg/AmpereAltraBinPkg.dec
@@ -0,0 +1,16 @@
+## @file
+#
+# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  DEC_SPECIFICATION              = 0x0001001B
+  PACKAGE_NAME                   = AmpereAltraBinPkg
+  PACKAGE_GUID                   = 04F7CB64-0F97-4D05-86B8-34987F4E1B21
+  PACKAGE_VERSION                = 0.1
+
+[Includes]
+  Include
diff --git a/Silicon/Ampere/AmpereAltraBinPkg/Library/PciePhyLib/PciePhyLib.inf b/Silicon/Ampere/AmpereAltraBinPkg/Library/PciePhyLib/PciePhyLib.inf
new file mode 100644
index 000000000000..a963b8910649
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraBinPkg/Library/PciePhyLib/PciePhyLib.inf
@@ -0,0 +1,23 @@
+## @file
+#
+# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001B
+  BASE_NAME                      = PciePhyLib
+  FILE_GUID                      = F2AD0AD0-D4B6-11E3-9C1A-0800200C9A66
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = PciePhyLib
+
+[Binaries.AArch64]
+  LIB|PciePhyLib.lib|*
+
+[Packages]
+  MdePkg/MdePkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
diff --git a/Silicon/Ampere/AmpereAltraBinPkg/Include/Library/PciePhyLib.h b/Silicon/Ampere/AmpereAltraBinPkg/Include/Library/PciePhyLib.h
new file mode 100644
index 000000000000..981072c577de
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraBinPkg/Include/Library/PciePhyLib.h
@@ -0,0 +1,111 @@
+/** @file
+
+  Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PCIE_PHY_LIB_H_
+#define PCIE_PHY_LIB_H_
+
+#define PHY_TX_PARAM_SIZE     2
+#define PHY_RX_PARAM_SIZE     2
+
+//
+// PCIe PHY error code
+//
+typedef enum {
+  PHY_SRAM_UPDATE_FAIL = -1,
+  PHY_INIT_PASS = 0,
+  PHY_ROM_ECC_FAIL,
+  PHY_SRAM_ECC_FAIL,
+  PHY_CALIB_FAIL,
+  PHY_CALIB_TIMEOUT,
+  PHY_PLL_FAIL
+} PHY_STATUS;
+
+//
+// PCIe PHY debug flags
+//
+typedef enum {
+  PHY_DBG_ERROR = 0x0001,
+  PHY_DBG_INFO = 0x0002,
+  PHY_DBG_WARN = 0x0004,
+  PHY_DBG_VERBOSE = 0x0008,
+  GEN1 = 0,
+  GEN2 = 1,
+  GEN3 = 2,
+  GEN4 = 3,
+  CCIX = 4
+} PHY_DBG_FLAGS;
+
+//
+// PCIe PHY setting structure
+//
+typedef struct {
+  UINT8  IsCalBySram;
+  UINT32 PllSettings;
+  UINT64 TuneTxParam[PHY_RX_PARAM_SIZE];
+  UINT64 TuneRxParam[PHY_TX_PARAM_SIZE];
+} PHY_SETTING;
+
+//
+// PCIe PHY Platform Operations Structure
+//
+// @Puts: Prints string to serial console
+// @PutInt: Prints 32-bit unsigned integer to serial console
+// @PutHex: Prints 32-bit unsigned hex to serial console
+// @PutHex64: Prints 64-bit unsigned hex to serial console
+// @DebugPrint: Prints formated string to serial console
+// @MmioRd: Reads 32-bit unsigned integer
+// @MmioWr: Writes 32-bit unsigned integer
+//
+typedef struct {
+  VOID  (*Puts)(CONST CHAR8 *Msg);
+  VOID  (*PutInt)(UINT32 Val);
+  VOID  (*PutHex)(UINT32 Val);
+  VOID  (*PutHex64)(UINT64 Val);
+  INT32 (*DebugPrint)(CONST CHAR8 *Fmt, ...);
+  VOID  (*MmioRd)(UINT64 Addr, UINT32 *Val);
+  VOID  (*MmioWr)(UINT64 Addr, UINT32 Val);
+  VOID  (*UsDelay)(UINT32 Val);
+} PHY_PLAT_RESOURCE;
+
+//
+// PCIe PHY context structure
+//
+typedef struct {
+  UINT64            SdsAddr;          /* PHY base address */
+  UINT64            PcieCtrlInfo;     /* PCIe controller related information
+                                       * BIT0-1: SoC revision
+                                       *      0: Ampere Altra
+                                       * BIT2  : SocketID (0: Socket0, 1: Socket1)
+                                       * BIT3  : Reserved
+                                       * BIT4-6: Root Complex context (RCA0/1/2/3 or RCB0/4/5/6)
+                                       * BIT7  : Reserved
+                                       * BIT8-9: PHY Numbers within RCA/RCB [0 to 3 each controls 4 lane]
+                                       *      0: x16, 1: x8 , 2:x4, 3: 0x2
+                                       * BIT10-11 : Gen
+                                       *      0: Gen1, 1: Gen2, 2: Gen3, 3: Gen4 + ESM
+                                       * BIT13-15 : Setting configuration selection
+                                       */
+  PHY_SETTING       PhySetting;       /* PHY input setting */
+  PHY_PLAT_RESOURCE *PhyPlatResource; /* Debug & misc function pointers */
+  PHY_DBG_FLAGS     Debug;
+} PHY_CONTEXT;
+
+/**
+  Function to initial clock and reset setting of the PCIe PHY.
+
+  @param[in]     Ctx       A pointer to the PHY context structure.
+
+  @retval PHY_INIT_PASS    PHY has been initialized.
+  @retval Other            Failed to initialize the PHY.
+**/
+PHY_STATUS
+SerdesInitClkrst (
+  IN PHY_CONTEXT *Ctx
+  );
+
+#endif
-- 
2.17.1