From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) by mx.groups.io with SMTP id smtpd.web08.5026.1622185007498416211 for ; Thu, 27 May 2021 23:56:47 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=jU2zWM0a; spf=pass (domain: ventanamicro.com, ip: 209.85.216.46, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pj1-f46.google.com with SMTP id o17-20020a17090a9f91b029015cef5b3c50so3918322pjp.4 for ; Thu, 27 May 2021 23:56:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=vs92qzhJs5AFwARYrvus91TL3n5LYTGxuRmY+HoAndo=; b=jU2zWM0aoMVh6I7k4bCRZQLB7TBdIjHWngj1fLFnLfa2VCO1/pgqJJYqYbxXxj0QyW julyGAMCaoa6DgPuSjsW0md1/DLcZvYEIV/CJiK+XWOheZT6I8OsmKQYvDzhK2kADKWB 2V8tz4dGs2SlZEm+Mnx9eXpxnNU2fZRPxAddzh2J1DXEoiOy1LJ2LtKSFeIT6CP2ZAWQ Zr7qpl6tFnVVI2wNWi8FCIzzOWlI4T2Vt/ip0boNb/1a/Zhaab56SZmma9kKA3GWoV8B NoZkAjJBByD3CHilWF/cBDfec4018Jp9gpEaUzmkVSzcvOI4PFIZmlMvEbK1pxkDmB4i 6eYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=vs92qzhJs5AFwARYrvus91TL3n5LYTGxuRmY+HoAndo=; b=jTLuAqoEdUZlA4Yp4C516HBVDF7Hg41NGiE4CcfV2sTVBMcYownnbBa+HWmVAHFSly XXWH/x/9WG5WWoCAyrZxrBFOnKKYfxZhNyRiWUx6oceRUx/pkZqAJs0+HgPmU/P5uZis O3aWgIKyba4iUD3KvIs6nGsbiDxN9DdCF8z82JT7Y3WzE88geabuWIcUOSosAewN0hSM I9/Y+6Bao/DCafZrIipZKpaguWOPzrL3r/C//Qsr3+WOuK5XGE1z+blk55hjXMJpKe1M Mcc/JI57OvOL/P5qFF2e88YOr2dmeIBU7ZyjFF9HGMkka20wbXb8B4jU3ZLaxolCSGwI CeMw== X-Gm-Message-State: AOAM533ScpFSlma9UQ6fniCtwJpOTllTSBM7bWD2/IJQTYASqqCae2Vh auWqW2CsGHPklZpYaweauJveWQ== X-Google-Smtp-Source: ABdhPJyrAbjDFHctQU8QmlS84U52jbp7moCpzfGKMNKccnKD5CiMcpkwImvC5H+aHGh0kG9lrk/Leg== X-Received: by 2002:a17:902:c951:b029:ef:9dca:9943 with SMTP id i17-20020a170902c951b02900ef9dca9943mr6848369pla.62.1622185006937; Thu, 27 May 2021 23:56:46 -0700 (PDT) Return-Path: Received: from sunil-ThinkPad-T490 ([49.206.3.187]) by smtp.gmail.com with ESMTPSA id x19sm3621721pfp.153.2021.05.27.23.56.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 May 2021 23:56:46 -0700 (PDT) Date: Fri, 28 May 2021 12:26:41 +0530 From: "Sunil V L" To: Daniel Schaefer Cc: devel@edk2.groups.io, sunil.vl@gmail.com, Abner Chang , Heinrich Schuchardt , Bob Feng , Liming Gao , Yuwei Chen Subject: Re: [PATCH] Add support for RISCV GOT/PLT relocations Message-ID: <20210528065641.GA5765@sunil-ThinkPad-T490> References: <20210527144113.206426-1-sunilvl@ventanamicro.com> <2523e9e3-3476-24b0-6ec9-1223f82f72ab@hpe.com> MIME-Version: 1.0 In-Reply-To: <2523e9e3-3476-24b0-6ec9-1223f82f72ab@hpe.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Thanks Daniel. Response below. On Fri, May 28, 2021 at 11:24:14AM +0800, Daniel Schaefer wrote: > +Maintainers and Reviewers of BaseTools > > See my reply below. > > On 5/27/21 10:41 PM, Sunil V L wrote: > > Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3096 > > > > This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20 > > relocations. > > > > Signed-off-by: Sunil V L > > Cc: Abner Chang > > Cc: Daniel Schaefer > > Cc: Heinrich Schuchardt > > --- > > BaseTools/Source/C/GenFw/Elf64Convert.c | 45 +++++++++++++++++++++---- > > 1 file changed, 39 insertions(+), 6 deletions(-) > > > > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c > > index d097db8632..d05dcf9992 100644 > > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c > > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c > > @@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset; > > STATIC UINT8 *mRiscVPass1Targ = NULL; > > STATIC Elf_Shdr *mRiscVPass1Sym = NULL; > > STATIC Elf64_Half mRiscVPass1SymSecIndex = 0; > > +STATIC INT32 mRiscVPass1Offset; > > +STATIC INT32 mRiscVPass1GotFixup; > > // > > // Initialization Function > > @@ -479,11 +481,11 @@ WriteSectionRiscV64 ( > > break; > > case R_RISCV_32: > > - *(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]); > > + *(UINT64 *)Targ = Sym->st_value + Rel->r_addend; > > break; > > case R_RISCV_64: > > - *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]; > > + *(UINT64 *)Targ = Sym->st_value + Rel->r_addend; > > break; > > case R_RISCV_HI20: > > @@ -533,6 +535,18 @@ WriteSectionRiscV64 ( > > mRiscVPass1SymSecIndex = 0; > > break; > > + case R_RISCV_GOT_HI20: > > + Value = (Sym->st_value - Rel->r_offset); > > + mRiscVPass1Offset = RV_X(Value, 0, 12); > > + Value = RV_X(Value, 12, 20); > > + *(UINT32 *)Targ = (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12)); > > + > > + mRiscVPass1Targ = Targ; > > + mRiscVPass1Sym = SymShdr; > > + mRiscVPass1SymSecIndex = Sym->st_shndx; > > + mRiscVPass1GotFixup = 1; > > + break; > > + > > case R_RISCV_PCREL_HI20: > > mRiscVPass1Targ = Targ; > > mRiscVPass1Sym = SymShdr; > > @@ -545,11 +559,17 @@ WriteSectionRiscV64 ( > > if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) { > > int i; > > Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20)); > > - Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); > > - if(Value & (RISCV_IMM_REACH/2)) { > > - Value |= ~(RISCV_IMM_REACH-1); > > + > > + if(mRiscVPass1GotFixup) { > > + Value = (UINT32)(mRiscVPass1Offset); > > + } else { > > + Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); > > + if(Value & (RISCV_IMM_REACH/2)) { > > + Value |= ~(RISCV_IMM_REACH-1); > > + } > > } > > Value = Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOffset[mRiscVPass1SymSecIndex]; > > + > > if(-2048 > (INT32)Value) { > > i = (((INT32)Value * -1) / 4096); > > Value2 -= i; > > @@ -569,12 +589,22 @@ WriteSectionRiscV64 ( > > } > > } > > - *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20)); > > + if(mRiscVPass1GotFixup) { > > + *(UINT32 *)Targ = (RV_X((UINT32)Value, 0, 12) << 20) > > + | (RV_X(*(UINT32*)Targ, 0, 20)); > > + /* Convert LD instruction to ADDI */ > > + *(UINT32 *)Targ = ((*(UINT32 *)Targ & ~0x707f) | 0x13); > > + } > > + else { > > else should be on the line before, like } else { Sure. Will fix it and send next version of patch. > > > + *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20)); > > + } > > *(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12)); > > } > > mRiscVPass1Sym = NULL; > > mRiscVPass1Targ = NULL; > > mRiscVPass1SymSecIndex = 0; > > + mRiscVPass1Offset = 0; > > + mRiscVPass1GotFixup = 0; > > break; > > case R_RISCV_ADD64: > > @@ -586,6 +616,7 @@ WriteSectionRiscV64 ( > > case R_RISCV_GPREL_I: > > case R_RISCV_GPREL_S: > > case R_RISCV_CALL: > > + case R_RISCV_CALL_PLT: > > case R_RISCV_RVC_BRANCH: > > case R_RISCV_RVC_JUMP: > > case R_RISCV_RELAX: > > @@ -1528,6 +1559,7 @@ WriteRelocations64 ( > > case R_RISCV_GPREL_I: > > case R_RISCV_GPREL_S: > > case R_RISCV_CALL: > > + case R_RISCV_CALL_PLT: > > case R_RISCV_RVC_BRANCH: > > case R_RISCV_RVC_JUMP: > > case R_RISCV_RELAX: > > @@ -1537,6 +1569,7 @@ WriteRelocations64 ( > > case R_RISCV_SET16: > > case R_RISCV_SET32: > > case R_RISCV_PCREL_HI20: > > + case R_RISCV_GOT_HI20: > > case R_RISCV_PCREL_LO12_I: > > break; > > > > Just one minor nit-pick on the formatting. > Well in my email program the indentation is off, it looks fine on GitHub > though. Probably an issue with the displaying on my end. > https://github.com/vlsunil/riscv-edk2/commit/a742fab0d73ab568aa2d2578a5ccfc400ffd2fa5 > I don't see an issue with formatting with either my mail client or github. > Reviewed-by: Daniel Schaefer > Thanks! Sunil > Tested with GCC 8.3.0 on Debian Buster. > Can boot -machine sifive_u to UEFI Shell and -machine virt on QEMU to Linux > shell. > > Sunil tested to compile on GCC 10.2.0 on Debian Buster - don't know if he > booted.