From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pg1-f182.google.com (mail-pg1-f182.google.com [209.85.215.182]) by mx.groups.io with SMTP id smtpd.web08.5801.1622192151555740575 for ; Fri, 28 May 2021 01:55:51 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=QvyGnRiJ; spf=pass (domain: ventanamicro.com, ip: 209.85.215.182, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pg1-f182.google.com with SMTP id 27so2040423pgy.3 for ; Fri, 28 May 2021 01:55:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=DEcMg4X0hl/kCCoem4CIA8dGkNKkehqIJIKwlF2Osf4=; b=QvyGnRiJlxUq5O7wIMWTEpF5E0Z6THEp3t6tMA8bJsQZERtN0Rmueyu4Cvh9rb7sUZ k8iBgzgOMefYQfkB9LtrYnMN06v8PKnLyXseoc+QwDJQEqi+qQJaz4RGl6kP/FzisVL6 AHfkqckMNBMpx5T5ddHLuPx05cPC1qqxCjJbkSM8FPUuPJNfp6T3gFjtfufyRZIzW0T4 cSwbsG9Y/XWzs8AxQsKXyTlIHfrbxT9/Go7IOM0VHUMgWcM+C5a7PPG5YaOooNGlXPNT qsRq9KwA9iluRqxG5OQ+aGS00l26hq9b0GA8yg9IkZzs9U3T+IsdBKw4JB1mzgZ3lwxI e1ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=DEcMg4X0hl/kCCoem4CIA8dGkNKkehqIJIKwlF2Osf4=; b=gnXXGoohwx1lSZ6U7dTK6aQUUYUmR3kR6s+PICJCYheI47Gbs1K+0XoV7/kvPf4GWx vgbX8x7yeGHRLuYBIwMyJ/SZO8/7IbxCGoQAO097i2zBDTxA6rW50RFnleijWuzWOmtQ KV6OnuT00ah8qIFw0iaj8YjRfuh6ToKsYLEZaVgDqUgFO4T4e8WX+5YlePVxEYguxzT4 vEbC9yL0S7rMbK9bEK+eolWRUkdnAaUcuc7llMv7jz9AaJ0mUtaUU/I0l0uPR+97AQ6Z 7lbSOZYeJbZJoJlc6Jf+tjv8g3cXJBdnbtfEay2B2Oo93GvB5cGu3p2auf/SAutIk9uD I1Ow== X-Gm-Message-State: AOAM532OOrXkJ36kC5vossnLlNivYNMHqkjsyXJg5/UOnMf3KNOWqLg5 rKvBSTzRXohOIbe72cOui92H/o+VUD4BB40t X-Google-Smtp-Source: ABdhPJwn5lJji8vv3Qp6OIoFYNehB5XBi8AFajxh6EA8PYy4tmCwspff00hgPiMZVioGS3JkLoz90w== X-Received: by 2002:a63:e80c:: with SMTP id s12mr7919299pgh.334.1622192150837; Fri, 28 May 2021 01:55:50 -0700 (PDT) Return-Path: Received: from sunil-ThinkPad-T490.dc1.ventanamicro.com ([49.206.3.187]) by smtp.gmail.com with ESMTPSA id 66sm3953572pgj.9.2021.05.28.01.55.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 May 2021 01:55:50 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: sunil.vl@gmail.com, Sunil V L , Abner Chang , Daniel Schaefer , Heinrich Schuchardt Subject: [PATCH v2] Add support for RISCV GOT/PLT relocations Date: Fri, 28 May 2021 14:25:40 +0530 Message-Id: <20210528085540.11711-1-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3096 This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20 relocations generated by PIE enabled compiler. This also needed changes to R_RISCV_32 and R_RISCV_64 relocations as explained in https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682= 710 Testing: 1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models. 2) Debian 10.2.0 and booted QEMU virt model. 3) riscv-gnu-tool chain 9.2 and booted QEMU virt model. Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Daniel Schaefer Tested-by: Cc: Heinrich Schuchardt --- BaseTools/Source/C/GenFw/Elf64Convert.c | 44 +++++++++++++++++++++---- 1 file changed, 38 insertions(+), 6 deletions(-) diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/G= enFw/Elf64Convert.c index d097db8632..d684318269 100644 --- a/BaseTools/Source/C/GenFw/Elf64Convert.c +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c @@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset; STATIC UINT8 *mRiscVPass1Targ =3D NULL;=0D STATIC Elf_Shdr *mRiscVPass1Sym =3D NULL;=0D STATIC Elf64_Half mRiscVPass1SymSecIndex =3D 0;=0D +STATIC INT32 mRiscVPass1Offset;=0D +STATIC INT32 mRiscVPass1GotFixup;=0D =0D //=0D // Initialization Function=0D @@ -479,11 +481,11 @@ WriteSectionRiscV64 ( break;=0D =0D case R_RISCV_32:=0D - *(UINT32 *)Targ =3D (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_a= ddr + mCoffSectionsOffset[Sym->st_shndx]);=0D + *(UINT64 *)Targ =3D Sym->st_value + Rel->r_addend;=0D break;=0D =0D case R_RISCV_64:=0D - *(UINT64 *)Targ =3D *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSections= Offset[Sym->st_shndx];=0D + *(UINT64 *)Targ =3D Sym->st_value + Rel->r_addend;=0D break;=0D =0D case R_RISCV_HI20:=0D @@ -533,6 +535,18 @@ WriteSectionRiscV64 ( mRiscVPass1SymSecIndex =3D 0;=0D break;=0D =0D + case R_RISCV_GOT_HI20:=0D + Value =3D (Sym->st_value - Rel->r_offset);=0D + mRiscVPass1Offset =3D RV_X(Value, 0, 12);=0D + Value =3D RV_X(Value, 12, 20);=0D + *(UINT32 *)Targ =3D (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12));=0D +=0D + mRiscVPass1Targ =3D Targ;=0D + mRiscVPass1Sym =3D SymShdr;=0D + mRiscVPass1SymSecIndex =3D Sym->st_shndx;=0D + mRiscVPass1GotFixup =3D 1;=0D + break;=0D +=0D case R_RISCV_PCREL_HI20:=0D mRiscVPass1Targ =3D Targ;=0D mRiscVPass1Sym =3D SymShdr;=0D @@ -545,11 +559,17 @@ WriteSectionRiscV64 ( if (mRiscVPass1Targ !=3D NULL && mRiscVPass1Sym !=3D NULL && mRiscVPas= s1SymSecIndex !=3D 0) {=0D int i;=0D Value2 =3D (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));=0D - Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));=0D - if(Value & (RISCV_IMM_REACH/2)) {=0D - Value |=3D ~(RISCV_IMM_REACH-1);=0D +=0D + if(mRiscVPass1GotFixup) {=0D + Value =3D (UINT32)(mRiscVPass1Offset);=0D + } else {=0D + Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));=0D + if(Value & (RISCV_IMM_REACH/2)) {=0D + Value |=3D ~(RISCV_IMM_REACH-1);=0D + }=0D }=0D Value =3D Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOff= set[mRiscVPass1SymSecIndex];=0D +=0D if(-2048 > (INT32)Value) {=0D i =3D (((INT32)Value * -1) / 4096);=0D Value2 -=3D i;=0D @@ -569,12 +589,21 @@ WriteSectionRiscV64 ( }=0D }=0D =0D - *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Tar= g, 0, 20));=0D + if(mRiscVPass1GotFixup) {=0D + *(UINT32 *)Targ =3D (RV_X((UINT32)Value, 0, 12) << 20)=0D + | (RV_X(*(UINT32*)Targ, 0, 20));=0D + /* Convert LD instruction to ADDI */=0D + *(UINT32 *)Targ =3D ((*(UINT32 *)Targ & ~0x707f) | 0x13);=0D + } else {=0D + *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)T= arg, 0, 20));=0D + }=0D *(UINT32 *)mRiscVPass1Targ =3D (RV_X(Value2, 0, 20)<<12) | (RV_X(*(U= INT32 *)mRiscVPass1Targ, 0, 12));=0D }=0D mRiscVPass1Sym =3D NULL;=0D mRiscVPass1Targ =3D NULL;=0D mRiscVPass1SymSecIndex =3D 0;=0D + mRiscVPass1Offset =3D 0;=0D + mRiscVPass1GotFixup =3D 0;=0D break;=0D =0D case R_RISCV_ADD64:=0D @@ -586,6 +615,7 @@ WriteSectionRiscV64 ( case R_RISCV_GPREL_I:=0D case R_RISCV_GPREL_S:=0D case R_RISCV_CALL:=0D + case R_RISCV_CALL_PLT:=0D case R_RISCV_RVC_BRANCH:=0D case R_RISCV_RVC_JUMP:=0D case R_RISCV_RELAX:=0D @@ -1528,6 +1558,7 @@ WriteRelocations64 ( case R_RISCV_GPREL_I:=0D case R_RISCV_GPREL_S:=0D case R_RISCV_CALL:=0D + case R_RISCV_CALL_PLT:=0D case R_RISCV_RVC_BRANCH:=0D case R_RISCV_RVC_JUMP:=0D case R_RISCV_RELAX:=0D @@ -1537,6 +1568,7 @@ WriteRelocations64 ( case R_RISCV_SET16:=0D case R_RISCV_SET32:=0D case R_RISCV_PCREL_HI20:=0D + case R_RISCV_GOT_HI20:=0D case R_RISCV_PCREL_LO12_I:=0D break;=0D =0D --=20 2.25.1