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* [PATCH v3 1/1] UefiCpuPkg/CpuCommonFeaturesLib: Update processor location info
@ 2021-06-02  2:25 Li, Daoxiang
  2021-06-02  2:41 ` Ni, Ray
  0 siblings, 1 reply; 3+ messages in thread
From: Li, Daoxiang @ 2021-06-02  2:25 UTC (permalink / raw)
  To: devel; +Cc: Daoxiang Li, Eric Dong, Ray Ni, Laszlo Ersek, Rahul Kumar

From: Daoxiang Li <daoxiang.li@intel.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3424

Processor location information check needs to updated
When Core 0 is disabled

Signed-off-by: Daoxiang Li <daoxiang.li@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
---
 UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c          | 4 ++--
 UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c | 4 ++--
 UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c         | 6 +++---
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
index e6e5db75917c..6f9685733202 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
@@ -63,9 +63,9 @@ C1eInitialize (
 {
   //
   // The scope of C1EEnable bit in the MSR_NEHALEM_POWER_CTL is Package, only program
-  // MSR_FEATURE_CONFIG for thread 0 core 0 in each package.
+  // MSR_NEHALEM_POWER_CTL once for each package.
   //
-  if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) {
+  if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) {
   return RETURN_SUCCESS;
   }
 
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
index bb5d983d1f4b..a3a2861cee5b 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
@@ -152,10 +152,10 @@ McaInitialize (
 
   //
   // The scope of MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS is package for below processor type, only program
-  // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS for thread 0 core 0 in each package.
+  // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS once for each package.
   //
   if (IS_NEHALEM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
-    if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) {
+    if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) {
       return RETURN_SUCCESS;
     }
   }
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
index 8450c7ea3eaf..3c4c1bc706ba 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
@@ -130,10 +130,10 @@ PpinInitialize (
   // Support function already check the processor which support PPIN feature, so this function not need
   // to check the processor again.
   //
-  // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only program MSR_IVY_BRIDGE_PPIN_CTL for
-  // thread 0 core 0 in each package.
+  // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only program MSR_IVY_BRIDGE_PPIN_CTL
+  // once for each package.
   //
-  if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) {
+  if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) {
     return RETURN_SUCCESS;
   }
 
-- 
2.28.0.windows.1


^ permalink raw reply related	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2021-06-02  2:48 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-06-02  2:25 [PATCH v3 1/1] UefiCpuPkg/CpuCommonFeaturesLib: Update processor location info Li, Daoxiang
2021-06-02  2:41 ` Ni, Ray
2021-06-02  2:48   ` [edk2-devel] " Li, Daoxiang

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