From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web08.7988.1622602892539332750 for ; Tue, 01 Jun 2021 20:01:32 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: daoxiang.li@intel.com) IronPort-SDR: zfw6YTbT+WPm9uWnq0q1Jn2CqXGN5ZcH7eMwNioQFtS4XxDIhOD5ndbguJ/gY4TDjNiCg9Zu4C SVc0zYEBd2EA== X-IronPort-AV: E=McAfee;i="6200,9189,10002"; a="203683741" X-IronPort-AV: E=Sophos;i="5.83,241,1616482800"; d="scan'208";a="203683741" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 20:01:28 -0700 IronPort-SDR: rD29LeIKFOk2/avEnXug7e0D+FVdmRtcXY1DdPJpyNFP+XSbv66A1MUk6VtCbDJkfLziUkF6pj fuUper/Vk6uA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,241,1616482800"; d="scan'208";a="482822117" Received: from sh1gapp1014.ccr.corp.intel.com ([10.239.189.84]) by fmsmga002.fm.intel.com with ESMTP; 01 Jun 2021 20:01:23 -0700 From: "Li, Daoxiang" To: devel@edk2.groups.io Cc: Daoxiang Li , Eric Dong , Ray Ni , Laszlo Ersek , Rahul Kumar Subject: [PATCH v4 1/1] UefiCpuPkg/CpuCommonFeaturesLib: Correct the CPU location check Date: Wed, 2 Jun 2021 11:01:13 +0800 Message-Id: <20210602030113.152-1-daoxiang.li@intel.com> X-Mailer: git-send-email 2.28.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Daoxiang Li REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3424 Processor location information check needs to updated When Core 0 is disabled. In C1e.c, change MSR_FEATURE_CONFIG to MSR_NEHALEM_POWER_CTL in comments to match the correct MSR name. Signed-off-by: Daoxiang Li Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar --- UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c | 4 ++-- UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c | 4 ++-- UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c b/UefiCpuPkg/Lib= rary/CpuCommonFeaturesLib/C1e.c index e6e5db75917c..6f9685733202 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c @@ -63,9 +63,9 @@ C1eInitialize ( {=0D //=0D // The scope of C1EEnable bit in the MSR_NEHALEM_POWER_CTL is Package, o= nly program=0D - // MSR_FEATURE_CONFIG for thread 0 core 0 in each package.=0D + // MSR_NEHALEM_POWER_CTL once for each package.=0D //=0D - if ((CpuInfo->ProcessorInfo.Location.Thread !=3D 0) || (CpuInfo->Process= orInfo.Location.Core !=3D 0)) {=0D + if ((CpuInfo->First.Thread =3D=3D 0) || (CpuInfo->First.Core =3D=3D 0)) = {=0D return RETURN_SUCCESS;=0D }=0D =0D diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c b/UefiC= puPkg/Library/CpuCommonFeaturesLib/MachineCheck.c index bb5d983d1f4b..a3a2861cee5b 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c @@ -152,10 +152,10 @@ McaInitialize ( =0D //=0D // The scope of MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS is package for belo= w processor type, only program=0D - // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS for thread 0 core 0 in each pack= age.=0D + // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS once for each package.=0D //=0D if (IS_NEHALEM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)= ) {=0D - if ((CpuInfo->ProcessorInfo.Location.Thread !=3D 0) || (CpuInfo->Proce= ssorInfo.Location.Core !=3D 0)) {=0D + if ((CpuInfo->First.Thread =3D=3D 0) || (CpuInfo->First.Core =3D=3D 0)= ) {=0D return RETURN_SUCCESS;=0D }=0D }=0D diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c b/UefiCpuPkg/Li= brary/CpuCommonFeaturesLib/Ppin.c index 8450c7ea3eaf..3c4c1bc706ba 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c @@ -130,10 +130,10 @@ PpinInitialize ( // Support function already check the processor which support PPIN featu= re, so this function not need=0D // to check the processor again.=0D //=0D - // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only progr= am MSR_IVY_BRIDGE_PPIN_CTL for=0D - // thread 0 core 0 in each package.=0D + // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only progr= am MSR_IVY_BRIDGE_PPIN_CTL=0D + // once for each package.=0D //=0D - if ((CpuInfo->ProcessorInfo.Location.Thread !=3D 0) || (CpuInfo->Process= orInfo.Location.Core !=3D 0)) {=0D + if ((CpuInfo->First.Thread =3D=3D 0) || (CpuInfo->First.Core =3D=3D 0)) = {=0D return RETURN_SUCCESS;=0D }=0D =0D --=20 2.28.0.windows.1