From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.8732.1622610089312915481 for ; Tue, 01 Jun 2021 22:01:29 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: khasim.mohammed@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 024656D; Tue, 1 Jun 2021 22:01:29 -0700 (PDT) Received: from usa.arm.com (unknown [10.163.35.111]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A46153F774; Tue, 1 Jun 2021 22:01:26 -0700 (PDT) From: "Khasim Mohammed" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar , Khasim Syed Mohammed Subject: [edk2-platforms][PATCH V1 1/4] Silicon/ARM/NeoverseN1Soc: Add mem regions to support multi-chip usecase Date: Wed, 2 Jun 2021 10:31:11 +0530 Message-Id: <20210602050114.26593-2-khasim.mohammed@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602050114.26593-1-khasim.mohammed@arm.com> References: <20210602050114.26593-1-khasim.mohammed@arm.com> From: Khasim Mohammed This patch adds resource descriptor for multi-chip usecase and introduces corresponding PCD definitions. Signed-off-by: Chandni Cherukuri Signed-off-by: Khasim Syed Mohammed --- Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 30 ++++++- Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf | 28 ++++--- Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 10 +-- Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c | 18 ++--- Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c | 43 ++++++++-- Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 84 +++++++++++++++++--- 6 files changed, 172 insertions(+), 41 deletions(-) diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec index 54b793a937ff..8789795bbae3 100644 --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec @@ -1,5 +1,7 @@ +## @file +# Describes the entire platform configuration. # -# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. +# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -33,8 +35,8 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000005 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000006 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase|0x0|UINT32|0x00000007 - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x00FFFFFF|UINT32|0x00000008 - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x01000000|UINT32|0x00000009 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x001FFFF|UINT32|0x00000008 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x020000|UINT32|0x00000009 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoTranslation|0x75200000|UINT32|0x0000000A gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base|0x71200000|UINT32|0x0000000B gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32MaxBase|0x751FFFFF|UINT32|0x0000000C @@ -44,3 +46,25 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64|0x00000010 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x00000011 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00000012 + + # CCIX + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount|18|UINT32|0x00000016 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax|17|UINT32|0x00000017 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin|0|UINT32|0x00000018 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UINT32|0x00000019 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001A + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x01FFFF|UINT32|0x0000001B + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x020000|UINT32|0x0000001C + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0x00000001D + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x0000001E + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0x00000001F + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size|0x04000000|UINT32|0x00000020 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Translation|0x0|UINT32|0x00000021 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base|0x2900000000|UINT64|0x00000022 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64MaxBase|0x48FFFFFFFF|UINT64|0x00000023 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size|0x2000000000|UINT64|0x00000024 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation|0x0|UINT64|0x00000025 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress|0x62000000|UINT32|0x00000026 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize|0x00001000|UINT32|0x00000027 + + gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000|UINT64|0x00000029 diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf index 166c9e044483..8e2154aadf47 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf @@ -1,6 +1,7 @@ ## @file +# Platform Library for N1Sdp. # -# Copyright (c) 2018-2020, ARM Limited. All rights reserved. +# Copyright (c) 2018-2021, ARM Limited. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -29,13 +30,17 @@ AArch64/Helper.S | GCC [FixedPcd] - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress - - gArmTokenSpaceGuid.PcdSystemMemoryBase - gArmTokenSpaceGuid.PcdSystemMemorySize - gArmTokenSpaceGuid.PcdArmPrimaryCore - gArmTokenSpaceGuid.PcdArmPrimaryCoreMask - + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base + gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base @@ -45,7 +50,12 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize - gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base + gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress [Guids] gEfiHobListGuid ## CONSUMES ## SystemTable diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h index 097160c7e2d1..309a5c627845 100644 --- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h +++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h @@ -1,9 +1,9 @@ /** @file -* -* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + + Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + **/ #ifndef NEOVERSEN1SOC_PLATFORM_H_ diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c index 9332939f63eb..ac88415fd24c 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -1,10 +1,10 @@ /** @file -* PCI Host Bridge Library instance for ARM Neoverse N1 platform -* -* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + PCI Host Bridge Library instance for ARM Neoverse N1 platform + + Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + **/ #include @@ -96,7 +96,7 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = { /** Return all the root bridge instances in an array. - @param Count Return the count of root bridge instances. + @param Count Return the count of root bridge instances. @return All the root bridge instances in an array. The array should be passed into PciHostBridgeFreeRootBridges() @@ -115,8 +115,8 @@ PciHostBridgeGetRootBridges ( /** Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). - @param Bridges The root bridge instances array. - @param Count The count of the array. + @param Bridges The root bridge instances array. + @param Count The count of the array. **/ VOID EFIAPI diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c index f722080e566b..d5ec0ff30d10 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c @@ -1,9 +1,9 @@ /** @file -* -* Copyright (c) 2018-2020, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + + Copyright (c) 2018-2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + **/ #include @@ -17,6 +17,12 @@ STATIC ARM_CORE_INFO mCoreInfoTable[] = { { 0x1, 0x1 } // Cluster 1, Core 1 }; +/** + Return the current Boot Mode. + + This function returns the boot reason on the platform. + +**/ EFI_BOOT_MODE ArmPlatformGetBootMode ( VOID @@ -25,6 +31,15 @@ ArmPlatformGetBootMode ( return BOOT_WITH_FULL_CONFIGURATION; } +/** + Initialize controllers that must be setup in the normal world. + + This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim + in the PEI phase. + + @param[in] MpId Processor ID + +**/ RETURN_STATUS ArmPlatformInitialize ( IN UINTN MpId @@ -33,6 +48,15 @@ ArmPlatformInitialize ( return RETURN_SUCCESS; } +/** + Populate the Platform core information. + + This function populates the ARM_MP_CORE_INFO_PPI with information about the cores. + + @param[out] CoreCount Number of cores + @param[out] ArmCoreTable Table containing information about the cores + +**/ EFI_STATUS PrePeiCoreGetMpCoreInfo ( OUT UINTN *CoreCount, @@ -56,6 +80,15 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { } }; +/** + Return the Platform specific PPIs + + This function exposes the N1Sdp Specific PPIs. + + @param[out] PpiListSize Size in Bytes of the Platform PPI List + @param[out] PpiList Platform PPI List + +**/ VOID ArmPlatformGetPlatformPpiList ( OUT UINTN *PpiListSize, diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c index f9b3d037537d..ebdcf437599a 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c @@ -1,9 +1,9 @@ /** @file -* -* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + + Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + **/ #include @@ -13,7 +13,7 @@ #include // The total number of descriptors, including the final "end-of-table" descriptor. -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 13 +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19 /** Returns the Virtual Memory Map of the platform. @@ -21,21 +21,23 @@ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. - @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing - a Physical-to-Virtual Memory mapping. This array - must be ended by a zero-filled entry. + @param[in] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing + a Physical-to-Virtual Memory mapping. This array + must be ended by a zero-filled entry. **/ VOID ArmPlatformGetVirtualMemoryMap ( IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap ) { - UINTN Index = 0; + UINTN Index; ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; NEOVERSEN1SOC_PLAT_INFO *PlatInfo; UINT64 DramBlock2Size; + UINT64 RemoteDdrSize; + Index = 0; PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; DramBlock2Size = ((UINT64)(PlatInfo->LocalDdrSize - NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) * @@ -55,6 +57,24 @@ ArmPlatformGetVirtualMemoryMap ( FixedPcdGet64 (PcdDramBlock2Base), DramBlock2Size); + if (PlatInfo->MultichipMode == 1) { + RemoteDdrSize = ((PlatInfo->RemoteDdrSize - 2) * 1024UL * 1024UL * 1024UL); + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FixedPcdGet64 (PcdExtMemorySpace) + FixedPcdGet64 (PcdSystemMemoryBase), + PcdGet64 (PcdSystemMemorySize) + ); + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FixedPcdGet64 (PcdExtMemorySpace) + FixedPcdGet64 (PcdDramBlock2Base), + RemoteDdrSize + ); + } + ASSERT (VirtualMemoryMap != NULL); Index = 0; @@ -114,6 +134,32 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length = PcdGet64 (PcdPcieMmio64Size); VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + // CCIX RC Configuration Space + VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdCcixRootPortConfigBaseAddress); + VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdCcixRootPortConfigBaseAddress); + VirtualMemoryTable[Index].Length = PcdGet32 (PcdCcixRootPortConfigBaseSize); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // CCIX ECAM Configuration Space + VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdCcixExpressBaseAddress); + VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdCcixExpressBaseAddress); + VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdCcixBusMax) - + FixedPcdGet32 (PcdCcixBusMin) + 1) * + SIZE_1MB; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // CCIX MMIO32 Memory Space + VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdCcixMmio32Base); + VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdCcixMmio32Base); + VirtualMemoryTable[Index].Length = PcdGet32 (PcdCcixMmio32Size); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // CCIX MMIO64 Memory Space + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdCcixMmio64Base); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdCcixMmio64Base); + VirtualMemoryTable[Index].Length = PcdGet64 (PcdCcixMmio64Size); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + // SubSystem Pheripherals - UART0 VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_UART0_BASE; VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_UART0_BASE; @@ -138,6 +184,24 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ; VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + if (PlatInfo->MultichipMode == 1) { + //Remote DDR (2GB) + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdExtMemorySpace) + + PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdExtMemorySpace) + + PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH; + + //Remote DDR + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdExtMemorySpace) + + PcdGet64 (PcdDramBlock2Base); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdExtMemorySpace) + + PcdGet64 (PcdDramBlock2Base); + VirtualMemoryTable[Index].Length = RemoteDdrSize; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH; + } + // End of Table VirtualMemoryTable[++Index].PhysicalBase = 0; VirtualMemoryTable[Index].VirtualBase = 0; -- 2.17.1