From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f42.google.com (mail-pj1-f42.google.com [209.85.216.42]) by mx.groups.io with SMTP id smtpd.web08.12467.1623160491318487350 for ; Tue, 08 Jun 2021 06:54:51 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=Xul4iUOU; spf=pass (domain: nuviainc.com, ip: 209.85.216.42, mailfrom: rebecca@nuviainc.com) Received: by mail-pj1-f42.google.com with SMTP id g24so11964769pji.4 for ; Tue, 08 Jun 2021 06:54:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=47yIjJPzhsBJKqp2HeALSgtdTZsBaB+Uil4oh+yrHLY=; b=Xul4iUOUCmYS5cbA929lg+JS9/n3lBQOnapHIT6l8+EFM48Kx9DK4LTETd2gW0nWWs FzSJ7b/tcJARHzJCyGSynNxjfJnqsQQUxJU9iZCsMQGKaVivveBiSGoYrUBauD7spkWq xySH6pfRyKNiQ1E+LaGZ9q0sAKWUYG2x/vraz+yzKv2tfTQmO98jmjdKAs5awIEGd1c9 HsC3mKOloeM/ofW+ZrGwjYpljA9j1cnsgcSdGBxP7cHThz2qT4Sk7ZrPGGFkZP1WtrMl MhluKgdnzWTdb91hq1ASXyC/FpxzAjUnxKU0nu/d20VHRCojnsvQfTdhTLiBse16Cmrx 8rFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=47yIjJPzhsBJKqp2HeALSgtdTZsBaB+Uil4oh+yrHLY=; b=ToDhHko2XGKBcUe8N/TkZa+e3kMmgk9CF5qRdqyQSusmD69x2riJcv5G9sW8P31Hkw xADVAsM6NCRWCoj5yhm+WPZmekh/6byzS1EjhiUEf7MbtWaK3ZCqmXAE659nfyX8j+eP x/wIWef3zaBr03y0BbTxu9l/RpZ2f/oc4KyxZb6rGHuj8tz5I+AtPLmg/yspoHQ4EU6S 5WLEGlGOdPBBFcxFzo8g76KRXc5djLkzUDj4cRXM9NvotoRTufTYUDgzdBQFQF6at99U AKNcV8f4ywfPEKJ0iY09M7T7YBmTTik2Hb1beIbAeQLHCUT+tAlNeZE7ThmffrFXW86b bT4A== X-Gm-Message-State: AOAM531nB4bgzCH2yPR/hHYItZRxxsArDwcUg4p58NDgA37wK5Td+JEk b5jMRdHsXi30H3xvVu2yO52bUhZPbwPpYCXleAd+qy50vMBkdM99P+HlNw/6/Qla1dry7JiZmjC JTF4JTCxSGQgb1mywU2pFQuzmtsm1xPyHdjgNMTa6Qrj110eNvR0xrAqLLM8j9RybhwS8cLDm X-Google-Smtp-Source: ABdhPJxltcLXZfwuDKkfwlruZttLRMaJ58xuxi7Y92RBCQEQOer+9uIqaYlexk05j+nPPe1tUivi/A== X-Received: by 2002:a17:90a:bf90:: with SMTP id d16mr5107967pjs.174.1623160490228; Tue, 08 Jun 2021 06:54:50 -0700 (PDT) Return-Path: Received: from linbox.int.bluestop.org.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id m18sm11549896pff.88.2021.06.08.06.54.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Jun 2021 06:54:49 -0700 (PDT) From: "Rebecca Cran" To: devel@edk2.groups.io, Leif Lindholm , Ard Biesheuvel Cc: Rebecca Cran Subject: [PATCH 1/1] ArmPkg: Move cache defs used in Universal/Smbios into ArmLib.h Date: Tue, 8 Jun 2021 07:54:32 -0600 Message-Id: <20210608135432.23420-1-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Many of the cache definitions in ArmLibPrivate.h are being used outside of ArmLib, in Universal/Smbios. Move them into ArmLib.h to make them public, and remove the include of ArmLibPrivate.h from files in Universal/Smbios. Signed-off-by: Rebecca Cran --- ArmPkg/Include/Library/ArmLib.h | 128 +++++++++++++++++++- ArmPkg/Library/ArmLib/ArmLibPrivate.h | 123 ------------------- ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 1 - ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c | 1 - ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c | 1 - ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c | 1 - 6 files changed, 127 insertions(+), 128 deletions(-) diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h index 5c232d779c83..0052adaa70aa 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -2,7 +2,7 @@ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.
- Copyright (c) 2020, NUVIA Inc. All rights reserved.
+ Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -113,6 +113,132 @@ typedef enum { // to 7 levels of cache, L1 through L7. #define MAX_ARM_CACHE_LEVEL 7 +/// Defines the structure of the CSSELR (Cache Size Selection) register +typedef union { + struct { + UINT32 InD :1; ///< Instruction not Data bit + UINT32 Level :3; ///< Cache level (zero based) + UINT32 TnD :1; ///< Allocation not Data bit + UINT32 Reserved :27; ///< Reserved, RES0 + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CSSELR_DATA; + +/// The cache type values for the InD field of the CSSELR register +typedef enum +{ + /// Select the data or unified cache + CsselrCacheTypeDataOrUnified = 0, + /// Select the instruction cache + CsselrCacheTypeInstruction, + CsselrCacheTypeMax +} CSSELR_CACHE_TYPE; + +/// Defines the structure of the CCSIDR (Current Cache Size ID) register +typedef union { + struct { + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4) + UINT64 Associativity :10; ///< Associativity - 1 + UINT64 NumSets :15; ///< Number of sets in the cache -1 + UINT64 Unknown :4; ///< Reserved, UNKNOWN + UINT64 Reserved :32; ///< Reserved, RES0 + } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported. + struct { + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4) + UINT64 Associativity :21; ///< Associativity - 1 + UINT64 Reserved1 :8; ///< Reserved, RES0 + UINT64 NumSets :24; ///< Number of sets in the cache -1 + UINT64 Reserved2 :8; ///< Reserved, RES0 + } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported. + struct { + UINT64 LineSize : 3; + UINT64 Associativity : 21; + UINT64 Reserved : 8; + UINT64 Unallocated : 32; + } BitsCcidxAA32; + UINT64 Data; ///< The entire 64-bit value +} CCSIDR_DATA; + +/// Defines the structure of the AARCH32 CCSIDR2 register. +typedef union { + struct { + UINT32 NumSets :24; ///< Number of sets in the cache - 1 + UINT32 Reserved :8; ///< Reserved, RES0 + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CCSIDR2_DATA; + +/** Defines the structure of the CLIDR (Cache Level ID) register. + * + * The lower 32 bits are the same for both AARCH32 and AARCH64 + * so we can use the same structure for both. +**/ +typedef union { + struct { + UINT32 Ctype1 : 3; ///< Level 1 cache type + UINT32 Ctype2 : 3; ///< Level 2 cache type + UINT32 Ctype3 : 3; ///< Level 3 cache type + UINT32 Ctype4 : 3; ///< Level 4 cache type + UINT32 Ctype5 : 3; ///< Level 5 cache type + UINT32 Ctype6 : 3; ///< Level 6 cache type + UINT32 Ctype7 : 3; ///< Level 7 cache type + UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable + UINT32 LoC : 3; ///< Level of Coherency + UINT32 LoUU : 3; ///< Level of Unification Uniprocessor + UINT32 Icb : 3; ///< Inner Cache Boundary + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CLIDR_DATA; + +/// The cache types reported in the CLIDR register. +typedef enum { + /// No cache is present + ClidrCacheTypeNone = 0, + /// There is only an instruction cache + ClidrCacheTypeInstructionOnly, + /// There is only a data cache + ClidrCacheTypeDataOnly, + /// There are separate data and instruction caches + ClidrCacheTypeSeparate, + /// There is a unified cache + ClidrCacheTypeUnified, + ClidrCacheTypeMax +} CLIDR_CACHE_TYPE; + +#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111) + +/** Reads the CCSIDR register for the specified cache. + + @param CSSELR The CSSELR cache selection register value. + + @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode. + Returns the contents of the CCSIDR register in AARCH32 mode. +**/ +UINTN +ReadCCSIDR ( + IN UINT32 CSSELR + ); + +/** Reads the CCSIDR2 for the specified cache. + + @param CSSELR The CSSELR cache selection register value + + @return The contents of the CCSIDR2 register for the specified cache. +**/ +UINT32 +ReadCCSIDR2 ( + IN UINT32 CSSELR + ); + +/** Reads the Cache Level ID (CLIDR) register. + + @return The contents of the CLIDR_EL1 register. +**/ +UINT32 +ReadCLIDR ( + VOID + ); + UINTN EFIAPI ArmDataCacheLineLength ( diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/ArmLibPrivate.h index 5db83d620bfc..668aefd6a088 100644 --- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h +++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h @@ -52,101 +52,6 @@ #define CACHE_ARCHITECTURE_UNIFIED (0UL) #define CACHE_ARCHITECTURE_SEPARATE (1UL) - -/// Defines the structure of the CSSELR (Cache Size Selection) register -typedef union { - struct { - UINT32 InD :1; ///< Instruction not Data bit - UINT32 Level :3; ///< Cache level (zero based) - UINT32 TnD :1; ///< Allocation not Data bit - UINT32 Reserved :27; ///< Reserved, RES0 - } Bits; ///< Bitfield definition of the register - UINT32 Data; ///< The entire 32-bit value -} CSSELR_DATA; - -/// The cache type values for the InD field of the CSSELR register -typedef enum -{ - /// Select the data or unified cache - CsselrCacheTypeDataOrUnified = 0, - /// Select the instruction cache - CsselrCacheTypeInstruction, - CsselrCacheTypeMax -} CSSELR_CACHE_TYPE; - -/// Defines the structure of the CCSIDR (Current Cache Size ID) register -typedef union { - struct { - UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4) - UINT64 Associativity :10; ///< Associativity - 1 - UINT64 NumSets :15; ///< Number of sets in the cache -1 - UINT64 Unknown :4; ///< Reserved, UNKNOWN - UINT64 Reserved :32; ///< Reserved, RES0 - } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported. - struct { - UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4) - UINT64 Associativity :21; ///< Associativity - 1 - UINT64 Reserved1 :8; ///< Reserved, RES0 - UINT64 NumSets :24; ///< Number of sets in the cache -1 - UINT64 Reserved2 :8; ///< Reserved, RES0 - } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported. - struct { - UINT64 LineSize : 3; - UINT64 Associativity : 21; - UINT64 Reserved : 8; - UINT64 Unallocated : 32; - } BitsCcidxAA32; - UINT64 Data; ///< The entire 64-bit value -} CCSIDR_DATA; - -/// Defines the structure of the AARCH32 CCSIDR2 register. -typedef union { - struct { - UINT32 NumSets :24; ///< Number of sets in the cache - 1 - UINT32 Reserved :8; ///< Reserved, RES0 - } Bits; ///< Bitfield definition of the register - UINT32 Data; ///< The entire 32-bit value -} CCSIDR2_DATA; - -/** Defines the structure of the CLIDR (Cache Level ID) register. - * - * The lower 32 bits are the same for both AARCH32 and AARCH64 - * so we can use the same structure for both. -**/ -typedef union { - struct { - UINT32 Ctype1 : 3; ///< Level 1 cache type - UINT32 Ctype2 : 3; ///< Level 2 cache type - UINT32 Ctype3 : 3; ///< Level 3 cache type - UINT32 Ctype4 : 3; ///< Level 4 cache type - UINT32 Ctype5 : 3; ///< Level 5 cache type - UINT32 Ctype6 : 3; ///< Level 6 cache type - UINT32 Ctype7 : 3; ///< Level 7 cache type - UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable - UINT32 LoC : 3; ///< Level of Coherency - UINT32 LoUU : 3; ///< Level of Unification Uniprocessor - UINT32 Icb : 3; ///< Inner Cache Boundary - } Bits; ///< Bitfield definition of the register - UINT32 Data; ///< The entire 32-bit value -} CLIDR_DATA; - -/// The cache types reported in the CLIDR register. -typedef enum { - /// No cache is present - ClidrCacheTypeNone = 0, - /// There is only an instruction cache - ClidrCacheTypeInstructionOnly, - /// There is only a data cache - ClidrCacheTypeDataOnly, - /// There are separate data and instruction caches - ClidrCacheTypeSeparate, - /// There is a unified cache - ClidrCacheTypeUnified, - ClidrCacheTypeMax -} CLIDR_CACHE_TYPE; - -#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111) - VOID CPSRMaskInsert ( IN UINT32 Mask, @@ -158,32 +63,4 @@ CPSRRead ( VOID ); -/** Reads the CCSIDR register for the specified cache. - - @param CSSELR The CSSELR cache selection register value. - - @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode. - Returns the contents of the CCSIDR register in AARCH32 mode. -**/ -UINTN -ReadCCSIDR ( - IN UINT32 CSSELR - ); - -/** Reads the CCSIDR2 for the specified cache. - - @param CSSELR The CSSELR cache selection register value - - @return The contents of the CCSIDR2 register for the specified cache. -**/ -UINT32 -ReadCCSIDR2 ( - IN UINT32 CSSELR - ); - -UINT32 -ReadCLIDR ( - VOID - ); - #endif // ARM_LIB_PRIVATE_H_ diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c index 0cb56c53975e..02297871c92c 100644 --- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c index ddd774b16f83..e5309ff598f9 100644 --- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c @@ -9,7 +9,6 @@ #include #include -#include #include "SmbiosProcessor.h" diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c index c78bd41a7e06..8176409b24e6 100644 --- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c @@ -9,7 +9,6 @@ #include #include -#include #include "SmbiosProcessor.h" diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c index bccb21cfbb41..07e18b3c04ea 100644 --- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include -- 2.26.2