From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com []) by mx.groups.io with SMTP id smtpd.web11.4374.1623288826156455282 for ; Wed, 09 Jun 2021 18:33:48 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: zhiguang.liu@intel.com) IronPort-SDR: Jmn3/7x0YwG4kSHxrSe4ut7RRJHThvGqfWzKkVQuq44hVCG+68VPVKA9iqz6fDBkdubPgzPF03 MnzmwCZSZXPQ== X-IronPort-AV: E=McAfee;i="6200,9189,10010"; a="266359691" X-IronPort-AV: E=Sophos;i="5.83,262,1616482800"; d="scan'208";a="266359691" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jun 2021 18:33:48 -0700 IronPort-SDR: X6uivXCUAyd8573fe13yqUGh0Qsuv4pdvZg25J1CAa9f49qoomrqE+kFzduJjeMVlPbT5SyzmM aQ2fLroB0sjA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,262,1616482800"; d="scan'208";a="402630970" Received: from fieedk002.ccr.corp.intel.com ([10.239.158.144]) by orsmga003.jf.intel.com with ESMTP; 09 Jun 2021 18:33:47 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Jian J Wang , Hao A Wu Subject: [Patch V4 2/9] MdeModulePkg: Add new structure for the PCI Root Bridge Info Hob Date: Thu, 10 Jun 2021 09:33:11 +0800 Message-Id: <20210610013318.1885-3-zhiguang.liu@intel.com> X-Mailer: git-send-email 2.30.0.windows.2 In-Reply-To: <20210610013318.1885-1-zhiguang.liu@intel.com> References: <20210610013318.1885-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Cc: Michael D Kinney Cc: Liming Gao Cc: Jian J Wang Cc: Hao A Wu Reviewed-by: Hao A Wu Signed-off-by: Zhiguang Liu --- MdeModulePkg/Include/UniversalPayload/PciRootBridges.h | 91 ++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++ MdeModulePkg/MdeModulePkg.dec | 6 ++++++ 2 files changed, 97 insertions(+) diff --git a/MdeModulePkg/Include/UniversalPayload/PciRootBridges.h b/MdeMo= dulePkg/Include/UniversalPayload/PciRootBridges.h new file mode 100644 index 0000000000..ea5b87480e --- /dev/null +++ b/MdeModulePkg/Include/UniversalPayload/PciRootBridges.h @@ -0,0 +1,91 @@ +/** @file=0D + This file defines the structure for the PCI Root Bridges.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D + @par Revision Reference:=0D + - Universal Payload Specification 0.75 (https://universalpayload.githu= b.io/documentation/)=0D +**/=0D +=0D +#ifndef __UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H__=0D +#define __UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H__=0D +=0D +#include =0D +=0D +#pragma pack(1)=0D +=0D +//=0D +// (Base > Limit) indicates an aperture is not available.=0D +//=0D +typedef struct {=0D + //=0D + // Base and Limit are the device address instead of host address when=0D + // Translation is not zero=0D + //=0D + UINT64 Base;=0D + UINT64 Limit;=0D + //=0D + // According to UEFI 2.7, Device Address =3D Host Address + Translation,= =0D + // so Translation =3D Device Address - Host Address.=0D + // On platforms where Translation is not zero, the subtraction is probab= ly to=0D + // be performed with UINT64 wrap-around semantics, for we may translate = an=0D + // above-4G host address into a below-4G device address for legacy PCIe = device=0D + // compatibility.=0D + //=0D + // NOTE: The alignment of Translation is required to be larger than any = BAR=0D + // alignment in the same root bridge, so that the same alignment can be= =0D + // applied to both device address and host address, which simplifies the= =0D + // situation and makes the current resource allocation code in generic P= CI=0D + // host bridge driver still work.=0D + //=0D + UINT64 Translation;=0D +} UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE;=0D +=0D +///=0D +/// Payload PCI Root Bridge Information HOB=0D +///=0D +typedef struct {=0D + UINT32 Segment; ///< S= egment number.=0D + UINT64 Supports; ///< S= upported attributes.=0D + ///< R= efer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()=0D + ///< a= nd SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.=0D + UINT64 Attributes; ///< I= nitial attributes.=0D + ///< R= efer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()=0D + ///< a= nd SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.=0D + BOOLEAN DmaAbove4G; ///< D= MA above 4GB memory.=0D + ///< S= et to TRUE when root bridge supports DMA above 4GB memory.=0D + BOOLEAN NoExtendedConfigSpace; ///< W= hen FALSE, the root bridge supports=0D + ///< E= xtended (4096-byte) Configuration Space.=0D + ///< W= hen TRUE, the root bridge supports=0D + ///< 2= 56-byte Configuration Space only.=0D + UINT64 AllocationAttributes; ///< A= llocation attributes.=0D + ///< R= efer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and=0D + ///< E= FI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes()=0D + ///< i= n EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.=0D + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Bus; ///< B= us aperture which can be used by the root bridge.=0D + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Io; ///< I= O aperture which can be used by the root bridge.=0D + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Mem; ///< M= MIO aperture below 4GB which can be used by the root bridge.=0D + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE MemAbove4G; ///< M= MIO aperture above 4GB which can be used by the root bridge.=0D + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMem; ///< P= refetchable MMIO aperture below 4GB which can be used by the root bridge.=0D + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; ///< P= refetchable MMIO aperture above 4GB which can be used by the root bridge.=0D + UINT32 HID; ///< P= nP hardware ID of the root bridge. This value must match the corresponding= =0D + ///< _= HID in the ACPI name space.=0D + UINT32 UID; ///< U= nique ID that is required by ACPI if two devices have the same _HID.=0D + ///< T= his value must also match the corresponding _UID/_HID pair in the ACPI name= space.=0D +} UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE;=0D +=0D +typedef struct {=0D + UNIVERSAL_PAYLOAD_GENERIC_HEADER Header;=0D + BOOLEAN ResourceAssigned;=0D + UINT8 Count;=0D + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE RootBridge[0];=0D +} UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES;=0D +=0D +#pragma pack()=0D +=0D +#define UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_REVISION 1=0D +=0D +extern GUID gUniversalPayloadPciRootBridgeInfoGuid;=0D +=0D +#endif // __UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H__=0D diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 8d38383915..5cee4e159a 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -404,6 +404,12 @@ ## Include/Guid/MigratedFvInfo.h=0D gEdkiiMigratedFvInfoGuid =3D { 0xc1ab12f7, 0x74aa, 0x408d, { 0xa2, 0xf4,= 0xc6, 0xce, 0xfd, 0x17, 0x98, 0x71 } }=0D =0D + #=0D + # GUID defined in UniversalPayload=0D + #=0D + ## Include/UniversalPayload/PciRootBridges.h=0D + gUniversalPayloadPciRootBridgeInfoGuid =3D { 0xec4ebacb, 0x2638, 0x416e,= { 0xbe, 0x80, 0xe5, 0xfa, 0x4b, 0x51, 0x19, 0x01 }}=0D +=0D [Ppis]=0D ## Include/Ppi/AtaController.h=0D gPeiAtaControllerPpiGuid =3D { 0xa45e60d1, 0xc719, 0x44aa, { 0xb0,= 0x7a, 0xaa, 0x77, 0x7f, 0x85, 0x90, 0x6d }}=0D --=20 2.30.0.windows.2