From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web12.1043.1623365182622647901 for ; Thu, 10 Jun 2021 15:46:22 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: michael.d.kinney@intel.com) IronPort-SDR: pHOOr/NKxLP661T67oxLS/QnJ5BZ/lkT3qBPh7rqJ9BQGMg7PaECMtSO/tYV2XEqbTIUts0SPW tAZ6/EaF/HCg== X-IronPort-AV: E=McAfee;i="6200,9189,10011"; a="291051496" X-IronPort-AV: E=Sophos;i="5.83,264,1616482800"; d="scan'208";a="291051496" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2021 15:46:09 -0700 IronPort-SDR: NZ1lsj7homwRCCGPTfkZD8ZTSav0B6A2rCxRmbrpjFhYUY8vZe/uIqBKyi3SkArlOICDYoLIkY PzndYzAPHAtg== X-IronPort-AV: E=Sophos;i="5.83,264,1616482800"; d="scan'208";a="419883435" Received: from mdkinney-mobl2.amr.corp.intel.com ([10.209.9.161]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2021 15:46:08 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Nate DeSimone Subject: [edk2-platforms][Patch 3/3] QuarkSocPkg/SmbusLib: Fix SmBusSendByte value Date: Thu, 10 Jun 2021 15:45:50 -0700 Message-Id: <20210610224550.855-4-michael.d.kinney@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20210610224550.855-1-michael.d.kinney@intel.com> References: <20210610224550.855-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3452 Update SmBusSendByte() to write value to Command Register instead of Host Data registers. Cc: Nate DeSimone Signed-off-by: Michael D Kinney --- .../Library/SmbusLib/SmbusLib.c | 27 ++++++++++++------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/Silicon/Intel/QuarkSocPkg/QuarkNorthCluster/Library/SmbusLib/SmbusLib.c b/Silicon/Intel/QuarkSocPkg/QuarkNorthCluster/Library/SmbusLib/SmbusLib.c index 319e103cf4..34437582d4 100644 --- a/Silicon/Intel/QuarkSocPkg/QuarkNorthCluster/Library/SmbusLib/SmbusLib.c +++ b/Silicon/Intel/QuarkSocPkg/QuarkNorthCluster/Library/SmbusLib/SmbusLib.c @@ -165,15 +165,24 @@ InternalSmBusNonBlock ( } // - // Set Host Commond Register. + // We do not need Data Register for SendByte Command // - IoWrite8 (IoPortBaseAddress + R_QNC_SMBUS_HCMD, (UINT8) SMBUS_LIB_COMMAND (SmBusAddress)); - // - // Write value to Host Data 0 and Host Data 1 Registers. - // - IoWrite8 (IoPortBaseAddress + R_QNC_SMBUS_HD0, (UINT8) Value); - IoWrite8 (IoPortBaseAddress + R_QNC_SMBUS_HD1, (UINT8) (Value >> 8)); - + if ((HostControl == V_QNC_SMBUS_HCTL_CMD_BYTE) && ((SmBusAddress & BIT0) == V_QNC_SMBUS_RW_SEL_WRITE)) { + // + // Set Host Command Register. + // + IoWrite8 (IoPortBaseAddress + R_QNC_SMBUS_HCMD, (UINT8)Value); + } else { + // + // Set Host Command Register. + // + IoWrite8 (IoPortBaseAddress + R_QNC_SMBUS_HCMD, (UINT8) SMBUS_LIB_COMMAND (SmBusAddress)); + // + // Write value to Host Data 0 and Host Data 1 Registers. + // + IoWrite8 (IoPortBaseAddress + R_QNC_SMBUS_HD0, (UINT8) Value); + IoWrite8 (IoPortBaseAddress + R_QNC_SMBUS_HD1, (UINT8) (Value >> 8)); + } // // Set SMBUS slave address for the device to send/receive from. @@ -351,7 +360,7 @@ SmBusSendByte ( return (UINT8) InternalSmBusNonBlock ( V_QNC_SMBUS_HCTL_CMD_BYTE, - SmBusAddress & V_QNC_SMBUS_RW_SEL_WRITE, + SmBusAddress | V_QNC_SMBUS_RW_SEL_WRITE, Value, Status ); -- 2.31.1.windows.1