From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) by mx.groups.io with SMTP id smtpd.web09.8905.1623420313227009096 for ; Fri, 11 Jun 2021 07:05:13 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=iChpyedL; spf=pass (domain: ventanamicro.com, ip: 209.85.216.53, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pj1-f53.google.com with SMTP id go18-20020a17090b03d2b029016e4ae973f7so4952267pjb.0 for ; Fri, 11 Jun 2021 07:05:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=inoZcExpNw83htij0VFbQEpcJQkTsqobJE2nX5a9umw=; b=iChpyedL5Wp5E5BB1wqPi2tE18u0yj5g9c11pfNxJ4S1toG5dAJQqqyZFiqezhKaAB P6RtvcyOMhP56yDAr8aBQgRWM2BSDGuBLZQ2cBvCfa8M+/MfHV5piNyIykfyLz2pMDF/ FafHB8edt097fqeultFwwp+TadKxKbNbPFOoBNhmbaKfmMS9X8+x2nUI6zE+nL4KoG4K xAZSZl5nUA+XleTJOOf2NFgxDQHMERQTPgFHYmIp/cj1eB61/aKyDnDaKmWavKpdWMCT UqkYgHJj86RA7Ij2QPGC9DYnOpjkXCQFtwe6shrEHyDj5mW8iJHRTcQA0fYnx6DCky0M UyIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=inoZcExpNw83htij0VFbQEpcJQkTsqobJE2nX5a9umw=; b=lKvwfkQDu2oYMFNHh0pqrTaSZozNoGriZTP/6bpL5t6sPxr6NnBammVT+N0K67dsEA Tke/eo7dkd5XacHoik2eXpzMJXQwkqCcnDijLzeKox2TxZ4WR0H5bTzrGcFygi8/3gj5 r3bXHtyQad2YVXVWQtJoYS++3GRZqEhDEEr9CXg5/RKBfXh9PFvSpcK4xybWEhhOMLXI FTIXMF92co179ZAiSGCj/vMLG6EhiruBwMyNFe0nYEnp11/3Elbk7YlH4nILsCU2BnGn OeakEYgtBBSxpz0gchXlPgQukikv8Y+ZMCkJmM1YOFSNdUxDQR4DsFYOrmHBpVF2xtlW d5NQ== X-Gm-Message-State: AOAM532GvE6Mypm/8+DO+IIICdvsUhTMXR2GnMQoFBqMlgpcwhcdrEbT /ddslxc5o8FisFs4VHQ0K79zzjo2x7xM//jD X-Google-Smtp-Source: ABdhPJwiRJU7JW3U6/bSkVj7kNcRr41nu4Do2McMy6cZ8uGIUI1W20ua+nMQxQwAVWYr0mtgwXTxqg== X-Received: by 2002:a17:90a:6a8d:: with SMTP id u13mr4709002pjj.55.1623420312309; Fri, 11 Jun 2021 07:05:12 -0700 (PDT) Return-Path: Received: from sunil-ThinkPad-T490.dc1.ventanamicro.com ([49.206.3.187]) by smtp.gmail.com with ESMTPSA id k63sm10631806pjh.13.2021.06.11.07.05.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jun 2021 07:05:11 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Sunil V L , Abner Chang , Daniel Schaefer , Bob Feng , Liming Gao , Yuwei Chen , Heinrich Schuchardt Subject: [RESEND PATCH v2] BaseTools: Add support for RISCV GOT/PLT relocations Date: Fri, 11 Jun 2021 19:35:03 +0530 Message-Id: <20210611140503.28409-1-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3096 This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20 relocations generated by PIE enabled compiler. This also needed changes to R_RISCV_32 and R_RISCV_64 relocations as explained in https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682= 710 Changes in v2: - Addressed Daniel's comment on formatting Testing: 1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models. 2) Debian 10.2.0 and booted QEMU virt model. 3) riscv-gnu-tool chain 9.2 and booted QEMU virt model. Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Daniel Schaefer Tested-by: Cc: Bob Feng Cc: Liming Gao Cc: Yuwei Chen Cc: Heinrich Schuchardt --- BaseTools/Source/C/GenFw/Elf64Convert.c | 44 +++++++++++++++++++++---- 1 file changed, 38 insertions(+), 6 deletions(-) diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/G= enFw/Elf64Convert.c index d097db8632..d684318269 100644 --- a/BaseTools/Source/C/GenFw/Elf64Convert.c +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c @@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset; STATIC UINT8 *mRiscVPass1Targ =3D NULL;=0D STATIC Elf_Shdr *mRiscVPass1Sym =3D NULL;=0D STATIC Elf64_Half mRiscVPass1SymSecIndex =3D 0;=0D +STATIC INT32 mRiscVPass1Offset;=0D +STATIC INT32 mRiscVPass1GotFixup;=0D =0D //=0D // Initialization Function=0D @@ -479,11 +481,11 @@ WriteSectionRiscV64 ( break;=0D =0D case R_RISCV_32:=0D - *(UINT32 *)Targ =3D (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_a= ddr + mCoffSectionsOffset[Sym->st_shndx]);=0D + *(UINT64 *)Targ =3D Sym->st_value + Rel->r_addend;=0D break;=0D =0D case R_RISCV_64:=0D - *(UINT64 *)Targ =3D *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSections= Offset[Sym->st_shndx];=0D + *(UINT64 *)Targ =3D Sym->st_value + Rel->r_addend;=0D break;=0D =0D case R_RISCV_HI20:=0D @@ -533,6 +535,18 @@ WriteSectionRiscV64 ( mRiscVPass1SymSecIndex =3D 0;=0D break;=0D =0D + case R_RISCV_GOT_HI20:=0D + Value =3D (Sym->st_value - Rel->r_offset);=0D + mRiscVPass1Offset =3D RV_X(Value, 0, 12);=0D + Value =3D RV_X(Value, 12, 20);=0D + *(UINT32 *)Targ =3D (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12));=0D +=0D + mRiscVPass1Targ =3D Targ;=0D + mRiscVPass1Sym =3D SymShdr;=0D + mRiscVPass1SymSecIndex =3D Sym->st_shndx;=0D + mRiscVPass1GotFixup =3D 1;=0D + break;=0D +=0D case R_RISCV_PCREL_HI20:=0D mRiscVPass1Targ =3D Targ;=0D mRiscVPass1Sym =3D SymShdr;=0D @@ -545,11 +559,17 @@ WriteSectionRiscV64 ( if (mRiscVPass1Targ !=3D NULL && mRiscVPass1Sym !=3D NULL && mRiscVPas= s1SymSecIndex !=3D 0) {=0D int i;=0D Value2 =3D (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));=0D - Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));=0D - if(Value & (RISCV_IMM_REACH/2)) {=0D - Value |=3D ~(RISCV_IMM_REACH-1);=0D +=0D + if(mRiscVPass1GotFixup) {=0D + Value =3D (UINT32)(mRiscVPass1Offset);=0D + } else {=0D + Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));=0D + if(Value & (RISCV_IMM_REACH/2)) {=0D + Value |=3D ~(RISCV_IMM_REACH-1);=0D + }=0D }=0D Value =3D Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOff= set[mRiscVPass1SymSecIndex];=0D +=0D if(-2048 > (INT32)Value) {=0D i =3D (((INT32)Value * -1) / 4096);=0D Value2 -=3D i;=0D @@ -569,12 +589,21 @@ WriteSectionRiscV64 ( }=0D }=0D =0D - *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Tar= g, 0, 20));=0D + if(mRiscVPass1GotFixup) {=0D + *(UINT32 *)Targ =3D (RV_X((UINT32)Value, 0, 12) << 20)=0D + | (RV_X(*(UINT32*)Targ, 0, 20));=0D + /* Convert LD instruction to ADDI */=0D + *(UINT32 *)Targ =3D ((*(UINT32 *)Targ & ~0x707f) | 0x13);=0D + } else {=0D + *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)T= arg, 0, 20));=0D + }=0D *(UINT32 *)mRiscVPass1Targ =3D (RV_X(Value2, 0, 20)<<12) | (RV_X(*(U= INT32 *)mRiscVPass1Targ, 0, 12));=0D }=0D mRiscVPass1Sym =3D NULL;=0D mRiscVPass1Targ =3D NULL;=0D mRiscVPass1SymSecIndex =3D 0;=0D + mRiscVPass1Offset =3D 0;=0D + mRiscVPass1GotFixup =3D 0;=0D break;=0D =0D case R_RISCV_ADD64:=0D @@ -586,6 +615,7 @@ WriteSectionRiscV64 ( case R_RISCV_GPREL_I:=0D case R_RISCV_GPREL_S:=0D case R_RISCV_CALL:=0D + case R_RISCV_CALL_PLT:=0D case R_RISCV_RVC_BRANCH:=0D case R_RISCV_RVC_JUMP:=0D case R_RISCV_RELAX:=0D @@ -1528,6 +1558,7 @@ WriteRelocations64 ( case R_RISCV_GPREL_I:=0D case R_RISCV_GPREL_S:=0D case R_RISCV_CALL:=0D + case R_RISCV_CALL_PLT:=0D case R_RISCV_RVC_BRANCH:=0D case R_RISCV_RVC_JUMP:=0D case R_RISCV_RELAX:=0D @@ -1537,6 +1568,7 @@ WriteRelocations64 ( case R_RISCV_SET16:=0D case R_RISCV_SET32:=0D case R_RISCV_PCREL_HI20:=0D + case R_RISCV_GOT_HI20:=0D case R_RISCV_PCREL_LO12_I:=0D break;=0D =0D --=20 2.25.1