From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pg1-f174.google.com (mail-pg1-f174.google.com [209.85.215.174]) by mx.groups.io with SMTP id smtpd.web08.9033.1623420493910721130 for ; Fri, 11 Jun 2021 07:08:14 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=iQAnXis5; spf=pass (domain: ventanamicro.com, ip: 209.85.215.174, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pg1-f174.google.com with SMTP id q15so2533094pgg.12 for ; Fri, 11 Jun 2021 07:08:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=PjAsITWe8fEAq/q3DV4wlBpWBnRxx+WxIRSXBC4rmWo=; b=iQAnXis5GV4Jg8SD2qmEIuQbjip9g3uEwvZVlT80qrlMsV/PcixKykwQwz9MlYK0O3 vhlQlwEFQTiHngzNlbs3Fl0OTBswMppehc0ln6KS8DOQHYvdT+hIK6bcAIT2LdevW4Xf pKRtcvX78+gDPMvbKvxIki5t1bwjo5Mr+Ah8e2Zkan2LZBs+eK2s6JF9KavkloJUME+6 oczL+IS1scDkfWie7oy5RwMTFDfyu7EQoLo2bmmjfheNNz3PGjpAmfsoSyE5bq4xyZWx oqia0KFRCPy4USPhI1qUeFEc3Kye/y8YP5nyQwoT5gO7bXDkPrklvUh2sSajph82quHa QIYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=PjAsITWe8fEAq/q3DV4wlBpWBnRxx+WxIRSXBC4rmWo=; b=TclxvRO8y95dx8SfhmitVj/UqAN5kbgxS/AcQgMScrMakf8plDzF3t5XVeFFfsTA0W TQKgzhcCfqChUujE/hx3NDofgtcvRRs9D5T9oFAj+L/8cc13Ww8+2N9ZRfSP4c9YKT6F xhc6QtELSzgQe5qM5iujFm8bzapa6j9f2hof7AjBx8dlR9bU80hYRvbwrik8mQHwEyiJ IGL/aZF8tym9tJXpTmOC4nvrLC2yvmBrWtuHYa+Rj6QHcon3j+XHKXeBglmqrfiA9zD1 xDe0nYammg28XX/eNOInmJwlbNadEmcaKwJcVsZK1fnorrGMXn+sOGn6j3lrWUzBjyU5 hMZA== X-Gm-Message-State: AOAM531zgf7v8Pr68kerWh3yE5ZITtCMc3FhE7r1vk6IMDyq9Xt05mIW dTLcoVnFbWDSrKgk1gOt648gzBtLT7GedtrN X-Google-Smtp-Source: ABdhPJx2H2LC03AHYUuzy/66ZBzoae6gXP2QzxUQUk53WuFXyGurM0sUB9nhpxMkAezfKS/uae7Uhw== X-Received: by 2002:aa7:920d:0:b029:2d9:2ead:70dd with SMTP id 13-20020aa7920d0000b02902d92ead70ddmr8338267pfo.67.1623420493186; Fri, 11 Jun 2021 07:08:13 -0700 (PDT) Return-Path: Received: from sunil-ThinkPad-T490 ([49.206.3.187]) by smtp.gmail.com with ESMTPSA id i16sm5225996pji.30.2021.06.11.07.08.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jun 2021 07:08:12 -0700 (PDT) Date: Fri, 11 Jun 2021 19:38:07 +0530 From: "Sunil V L" To: devel@edk2.groups.io Cc: Abner Chang , Daniel Schaefer , Bob Feng , Liming Gao , Yuwei Chen , Heinrich Schuchardt Subject: Re: [RESEND PATCH v2] BaseTools: Add support for RISCV GOT/PLT relocations Message-ID: <20210611140807.GA28471@sunil-ThinkPad-T490> References: <20210611140503.28409-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 In-Reply-To: <20210611140503.28409-1-sunilvl@ventanamicro.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi, I just edited the commit message to indicate the module and CC the maintainers. Could I get the feedback please? Thanks Sunil On Fri, Jun 11, 2021 at 07:35:03PM +0530, Sunil V L wrote: > Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3096 > > This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20 > relocations generated by PIE enabled compiler. This also needed > changes to R_RISCV_32 and R_RISCV_64 relocations as explained in > https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710 > > Changes in v2: > - Addressed Daniel's comment on formatting > > Testing: > 1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models. > 2) Debian 10.2.0 and booted QEMU virt model. > 3) riscv-gnu-tool chain 9.2 and booted QEMU virt model. > > Signed-off-by: Sunil V L > > Acked-by: Abner Chang > Reviewed-by: Daniel Schaefer > Tested-by: > > Cc: Bob Feng > Cc: Liming Gao > Cc: Yuwei Chen > Cc: Heinrich Schuchardt > --- > BaseTools/Source/C/GenFw/Elf64Convert.c | 44 +++++++++++++++++++++---- > 1 file changed, 38 insertions(+), 6 deletions(-) > > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c > index d097db8632..d684318269 100644 > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c > @@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset; > STATIC UINT8 *mRiscVPass1Targ = NULL; > STATIC Elf_Shdr *mRiscVPass1Sym = NULL; > STATIC Elf64_Half mRiscVPass1SymSecIndex = 0; > +STATIC INT32 mRiscVPass1Offset; > +STATIC INT32 mRiscVPass1GotFixup; > > // > // Initialization Function > @@ -479,11 +481,11 @@ WriteSectionRiscV64 ( > break; > > case R_RISCV_32: > - *(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]); > + *(UINT64 *)Targ = Sym->st_value + Rel->r_addend; > break; > > case R_RISCV_64: > - *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]; > + *(UINT64 *)Targ = Sym->st_value + Rel->r_addend; > break; > > case R_RISCV_HI20: > @@ -533,6 +535,18 @@ WriteSectionRiscV64 ( > mRiscVPass1SymSecIndex = 0; > break; > > + case R_RISCV_GOT_HI20: > + Value = (Sym->st_value - Rel->r_offset); > + mRiscVPass1Offset = RV_X(Value, 0, 12); > + Value = RV_X(Value, 12, 20); > + *(UINT32 *)Targ = (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12)); > + > + mRiscVPass1Targ = Targ; > + mRiscVPass1Sym = SymShdr; > + mRiscVPass1SymSecIndex = Sym->st_shndx; > + mRiscVPass1GotFixup = 1; > + break; > + > case R_RISCV_PCREL_HI20: > mRiscVPass1Targ = Targ; > mRiscVPass1Sym = SymShdr; > @@ -545,11 +559,17 @@ WriteSectionRiscV64 ( > if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) { > int i; > Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20)); > - Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); > - if(Value & (RISCV_IMM_REACH/2)) { > - Value |= ~(RISCV_IMM_REACH-1); > + > + if(mRiscVPass1GotFixup) { > + Value = (UINT32)(mRiscVPass1Offset); > + } else { > + Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); > + if(Value & (RISCV_IMM_REACH/2)) { > + Value |= ~(RISCV_IMM_REACH-1); > + } > } > Value = Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOffset[mRiscVPass1SymSecIndex]; > + > if(-2048 > (INT32)Value) { > i = (((INT32)Value * -1) / 4096); > Value2 -= i; > @@ -569,12 +589,21 @@ WriteSectionRiscV64 ( > } > } > > - *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20)); > + if(mRiscVPass1GotFixup) { > + *(UINT32 *)Targ = (RV_X((UINT32)Value, 0, 12) << 20) > + | (RV_X(*(UINT32*)Targ, 0, 20)); > + /* Convert LD instruction to ADDI */ > + *(UINT32 *)Targ = ((*(UINT32 *)Targ & ~0x707f) | 0x13); > + } else { > + *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20)); > + } > *(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12)); > } > mRiscVPass1Sym = NULL; > mRiscVPass1Targ = NULL; > mRiscVPass1SymSecIndex = 0; > + mRiscVPass1Offset = 0; > + mRiscVPass1GotFixup = 0; > break; > > case R_RISCV_ADD64: > @@ -586,6 +615,7 @@ WriteSectionRiscV64 ( > case R_RISCV_GPREL_I: > case R_RISCV_GPREL_S: > case R_RISCV_CALL: > + case R_RISCV_CALL_PLT: > case R_RISCV_RVC_BRANCH: > case R_RISCV_RVC_JUMP: > case R_RISCV_RELAX: > @@ -1528,6 +1558,7 @@ WriteRelocations64 ( > case R_RISCV_GPREL_I: > case R_RISCV_GPREL_S: > case R_RISCV_CALL: > + case R_RISCV_CALL_PLT: > case R_RISCV_RVC_BRANCH: > case R_RISCV_RVC_JUMP: > case R_RISCV_RELAX: > @@ -1537,6 +1568,7 @@ WriteRelocations64 ( > case R_RISCV_SET16: > case R_RISCV_SET32: > case R_RISCV_PCREL_HI20: > + case R_RISCV_GOT_HI20: > case R_RISCV_PCREL_LO12_I: > break; > > -- > 2.25.1 >