From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f41.google.com (mail-pj1-f41.google.com [209.85.216.41]) by mx.groups.io with SMTP id smtpd.web10.2108.1623697077357225055 for ; Mon, 14 Jun 2021 11:57:57 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=dTE0kSsN; spf=pass (domain: nuviainc.com, ip: 209.85.216.41, mailfrom: rebecca@nuviainc.com) Received: by mail-pj1-f41.google.com with SMTP id o10-20020a17090aac0ab029016e92770073so611415pjq.5 for ; Mon, 14 Jun 2021 11:57:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=D8h9X1P+BgFAd/uv7t4bc+VMkGQZhieIOrmVRvCpzEk=; b=dTE0kSsNIkuUmtTq8KBUGNaOVGCX2MXdq72S0PR2YomrjnsS0EmyAHA3xkhGl8Z6PX mSNUeBsDgn20LbBI59/HV2kca1hWrmcY7m7hrSUD9wBsGbEIXugRpr14YxJai/GrPPEz 9VJO7ouvS83GWuXzBHpp1Z5IPJXiDMKNn33JUc9YIC9PPxP5KOqqkQLXvaGz/9GDaaOY uiWAputQFsEADicYf5qK5e6SmiztM049XXCWd/ry5tzwgr045f8mhYNmifAbQhpw+Ckr U8hBqiUGp9xWiXRdxxceUQKPIw4dWwku1gXK1w0JgSAjbXcWTC+5pc/3Po+KLSgo0fFh DD5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=D8h9X1P+BgFAd/uv7t4bc+VMkGQZhieIOrmVRvCpzEk=; b=GUaV/nQr+Bsjml6SNM5cw6cqTWraHQTXkWdwVoa5DXW7KqWtEia7CYZ1zbIhiquzoW 6bPe1BwgXCtSFzE4R7xaX43cdpoSyHqoGF+MzVs71Cw90i8qI0nglHSyhhoYH/jtRK5W KxM5D5f1zdr1ePEpaGUKMQXdv8kQBkfkoalv6AqfM6j0VFtR/BkwZdluBtGL6KbvyfxC CiYuEcBUhTKLCTrsbYHaxYiraM8jm+ZxkexUpQ7jqDiBAj8Eill20FlJUhHnqMaKgfNi r4huiVJ0oLzzeH7u4G69cqbmtAr7Z4exaxjBnJqnxgBfVjbUMrmmx+xU3ayyoJ/VSwAP y6eg== X-Gm-Message-State: AOAM531QdQ2E/UkXUokE3QuzQcRlnGq1kanaWlMlm+aBkyH/QICHuqlb X62Ev0QrzRfYiXw/HO4FzDOgsQ== X-Google-Smtp-Source: ABdhPJw9duVNW0duh0HogKQAdRW2oe/6+6vxU6qk9Iywu2EafTjycQzYvMlnRSLjGv0pTTNk4tDn/w== X-Received: by 2002:a17:90a:f681:: with SMTP id cl1mr285208pjb.233.1623697076700; Mon, 14 Jun 2021 11:57:56 -0700 (PDT) Return-Path: Received: from linbox.int.bluestop.org.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id 22sm12939288pfo.80.2021.06.14.11.57.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jun 2021 11:57:56 -0700 (PDT) From: "Rebecca Cran" To: Ard Biesheuvel , Leif Lindholm Cc: Rebecca Cran , devel@edk2.groups.io Subject: [PATCH v2 1/1] ArmPkg: Move cache defs used in Universal/Smbios into ArmCache.h Date: Mon, 14 Jun 2021 12:57:49 -0600 Message-Id: <20210614185749.12474-1-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Many of the cache definitions in ArmLibPrivate.h are being used outside of ArmLib, in Universal/Smbios. Move them into ArmCache.h to make them public, and remove the include of ArmLibPrivate.h from files in Universal/Smbios. Signed-off-by: Rebecca Cran --- ArmPkg/Include/IndustryStandard/ArmCache.h | 112 ++++++++++++++++++ ArmPkg/Include/Library/ArmLib.h | 36 +++++- ArmPkg/Library/ArmLib/ArmLibPrivate.h | 123 -------------------- ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 2 +- ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c | 2 +- ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c | 2 +- ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c | 2 +- 7 files changed, 148 insertions(+), 131 deletions(-) diff --git a/ArmPkg/Include/IndustryStandard/ArmCache.h b/ArmPkg/Include/IndustryStandard/ArmCache.h new file mode 100644 index 000000000000..f9de46b5bffd --- /dev/null +++ b/ArmPkg/Include/IndustryStandard/ArmCache.h @@ -0,0 +1,112 @@ +/** @file + + Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef ARM_CACHE_H_ +#define ARM_CACHE_H_ + +#include + +// The ARM Architecture Reference Manual for ARMv8-A defines up +// to 7 levels of cache, L1 through L7. +#define MAX_ARM_CACHE_LEVEL 7 + +/// Defines the structure of the CSSELR (Cache Size Selection) register +typedef union { + struct { + UINT32 InD :1; ///< Instruction not Data bit + UINT32 Level :3; ///< Cache level (zero based) + UINT32 TnD :1; ///< Allocation not Data bit + UINT32 Reserved :27; ///< Reserved, RES0 + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CSSELR_DATA; + +/// The cache type values for the InD field of the CSSELR register +typedef enum +{ + /// Select the data or unified cache + CsselrCacheTypeDataOrUnified = 0, + /// Select the instruction cache + CsselrCacheTypeInstruction, + CsselrCacheTypeMax +} CSSELR_CACHE_TYPE; + +/// Defines the structure of the CCSIDR (Current Cache Size ID) register +typedef union { + struct { + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4) + UINT64 Associativity :10; ///< Associativity - 1 + UINT64 NumSets :15; ///< Number of sets in the cache -1 + UINT64 Unknown :4; ///< Reserved, UNKNOWN + UINT64 Reserved :32; ///< Reserved, RES0 + } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported. + struct { + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4) + UINT64 Associativity :21; ///< Associativity - 1 + UINT64 Reserved1 :8; ///< Reserved, RES0 + UINT64 NumSets :24; ///< Number of sets in the cache -1 + UINT64 Reserved2 :8; ///< Reserved, RES0 + } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported. + struct { + UINT64 LineSize : 3; + UINT64 Associativity : 21; + UINT64 Reserved : 8; + UINT64 Unallocated : 32; + } BitsCcidxAA32; + UINT64 Data; ///< The entire 64-bit value +} CCSIDR_DATA; + +/// Defines the structure of the AARCH32 CCSIDR2 register. +typedef union { + struct { + UINT32 NumSets :24; ///< Number of sets in the cache - 1 + UINT32 Reserved :8; ///< Reserved, RES0 + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CCSIDR2_DATA; + +/** Defines the structure of the CLIDR (Cache Level ID) register. + * + * The lower 32 bits are the same for both AARCH32 and AARCH64 + * so we can use the same structure for both. +**/ +typedef union { + struct { + UINT32 Ctype1 : 3; ///< Level 1 cache type + UINT32 Ctype2 : 3; ///< Level 2 cache type + UINT32 Ctype3 : 3; ///< Level 3 cache type + UINT32 Ctype4 : 3; ///< Level 4 cache type + UINT32 Ctype5 : 3; ///< Level 5 cache type + UINT32 Ctype6 : 3; ///< Level 6 cache type + UINT32 Ctype7 : 3; ///< Level 7 cache type + UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable + UINT32 LoC : 3; ///< Level of Coherency + UINT32 LoUU : 3; ///< Level of Unification Uniprocessor + UINT32 Icb : 3; ///< Inner Cache Boundary + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CLIDR_DATA; + +/// The cache types reported in the CLIDR register. +typedef enum { + /// No cache is present + ClidrCacheTypeNone = 0, + /// There is only an instruction cache + ClidrCacheTypeInstructionOnly, + /// There is only a data cache + ClidrCacheTypeDataOnly, + /// There are separate data and instruction caches + ClidrCacheTypeSeparate, + /// There is a unified cache + ClidrCacheTypeUnified, + ClidrCacheTypeMax +} CLIDR_CACHE_TYPE; + +#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111) + +#endif /* ARM_CACHE_H_ */ diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h index 5c232d779c83..79ea755777a9 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -2,7 +2,7 @@ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.
- Copyright (c) 2020, NUVIA Inc. All rights reserved.
+ Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -109,9 +109,37 @@ typedef enum { #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId)) #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK) -// The ARM Architecture Reference Manual for ARMv8-A defines up -// to 7 levels of cache, L1 through L7. -#define MAX_ARM_CACHE_LEVEL 7 +/** Reads the CCSIDR register for the specified cache. + + @param CSSELR The CSSELR cache selection register value. + + @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode. + Returns the contents of the CCSIDR register in AARCH32 mode. +**/ +UINTN +ReadCCSIDR ( + IN UINT32 CSSELR + ); + +/** Reads the CCSIDR2 for the specified cache. + + @param CSSELR The CSSELR cache selection register value + + @return The contents of the CCSIDR2 register for the specified cache. +**/ +UINT32 +ReadCCSIDR2 ( + IN UINT32 CSSELR + ); + +/** Reads the Cache Level ID (CLIDR) register. + + @return The contents of the CLIDR_EL1 register. +**/ +UINT32 +ReadCLIDR ( + VOID + ); UINTN EFIAPI diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/ArmLibPrivate.h index 5db83d620bfc..668aefd6a088 100644 --- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h +++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h @@ -52,101 +52,6 @@ #define CACHE_ARCHITECTURE_UNIFIED (0UL) #define CACHE_ARCHITECTURE_SEPARATE (1UL) - -/// Defines the structure of the CSSELR (Cache Size Selection) register -typedef union { - struct { - UINT32 InD :1; ///< Instruction not Data bit - UINT32 Level :3; ///< Cache level (zero based) - UINT32 TnD :1; ///< Allocation not Data bit - UINT32 Reserved :27; ///< Reserved, RES0 - } Bits; ///< Bitfield definition of the register - UINT32 Data; ///< The entire 32-bit value -} CSSELR_DATA; - -/// The cache type values for the InD field of the CSSELR register -typedef enum -{ - /// Select the data or unified cache - CsselrCacheTypeDataOrUnified = 0, - /// Select the instruction cache - CsselrCacheTypeInstruction, - CsselrCacheTypeMax -} CSSELR_CACHE_TYPE; - -/// Defines the structure of the CCSIDR (Current Cache Size ID) register -typedef union { - struct { - UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4) - UINT64 Associativity :10; ///< Associativity - 1 - UINT64 NumSets :15; ///< Number of sets in the cache -1 - UINT64 Unknown :4; ///< Reserved, UNKNOWN - UINT64 Reserved :32; ///< Reserved, RES0 - } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported. - struct { - UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4) - UINT64 Associativity :21; ///< Associativity - 1 - UINT64 Reserved1 :8; ///< Reserved, RES0 - UINT64 NumSets :24; ///< Number of sets in the cache -1 - UINT64 Reserved2 :8; ///< Reserved, RES0 - } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported. - struct { - UINT64 LineSize : 3; - UINT64 Associativity : 21; - UINT64 Reserved : 8; - UINT64 Unallocated : 32; - } BitsCcidxAA32; - UINT64 Data; ///< The entire 64-bit value -} CCSIDR_DATA; - -/// Defines the structure of the AARCH32 CCSIDR2 register. -typedef union { - struct { - UINT32 NumSets :24; ///< Number of sets in the cache - 1 - UINT32 Reserved :8; ///< Reserved, RES0 - } Bits; ///< Bitfield definition of the register - UINT32 Data; ///< The entire 32-bit value -} CCSIDR2_DATA; - -/** Defines the structure of the CLIDR (Cache Level ID) register. - * - * The lower 32 bits are the same for both AARCH32 and AARCH64 - * so we can use the same structure for both. -**/ -typedef union { - struct { - UINT32 Ctype1 : 3; ///< Level 1 cache type - UINT32 Ctype2 : 3; ///< Level 2 cache type - UINT32 Ctype3 : 3; ///< Level 3 cache type - UINT32 Ctype4 : 3; ///< Level 4 cache type - UINT32 Ctype5 : 3; ///< Level 5 cache type - UINT32 Ctype6 : 3; ///< Level 6 cache type - UINT32 Ctype7 : 3; ///< Level 7 cache type - UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable - UINT32 LoC : 3; ///< Level of Coherency - UINT32 LoUU : 3; ///< Level of Unification Uniprocessor - UINT32 Icb : 3; ///< Inner Cache Boundary - } Bits; ///< Bitfield definition of the register - UINT32 Data; ///< The entire 32-bit value -} CLIDR_DATA; - -/// The cache types reported in the CLIDR register. -typedef enum { - /// No cache is present - ClidrCacheTypeNone = 0, - /// There is only an instruction cache - ClidrCacheTypeInstructionOnly, - /// There is only a data cache - ClidrCacheTypeDataOnly, - /// There are separate data and instruction caches - ClidrCacheTypeSeparate, - /// There is a unified cache - ClidrCacheTypeUnified, - ClidrCacheTypeMax -} CLIDR_CACHE_TYPE; - -#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111) - VOID CPSRMaskInsert ( IN UINT32 Mask, @@ -158,32 +63,4 @@ CPSRRead ( VOID ); -/** Reads the CCSIDR register for the specified cache. - - @param CSSELR The CSSELR cache selection register value. - - @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode. - Returns the contents of the CCSIDR register in AARCH32 mode. -**/ -UINTN -ReadCCSIDR ( - IN UINT32 CSSELR - ); - -/** Reads the CCSIDR2 for the specified cache. - - @param CSSELR The CSSELR cache selection register value - - @return The contents of the CCSIDR2 register for the specified cache. -**/ -UINT32 -ReadCCSIDR2 ( - IN UINT32 CSSELR - ); - -UINT32 -ReadCLIDR ( - VOID - ); - #endif // ARM_LIB_PRIVATE_H_ diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c index 0cb56c53975e..fb484086a457 100644 --- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c @@ -10,11 +10,11 @@ #include #include +#include #include #include #include #include -#include #include #include #include diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c index ddd774b16f83..6fbb95afb215 100644 --- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c @@ -8,8 +8,8 @@ **/ #include +#include #include -#include #include "SmbiosProcessor.h" diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c index c78bd41a7e06..7616fca425fd 100644 --- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c @@ -8,8 +8,8 @@ **/ #include +#include #include -#include #include "SmbiosProcessor.h" diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c index bccb21cfbb41..292f10bf97eb 100644 --- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c @@ -8,10 +8,10 @@ **/ #include +#include #include #include #include -#include #include #include -- 2.26.2