From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com []) by mx.groups.io with SMTP id smtpd.web11.6828.1623748346075457462 for ; Tue, 15 Jun 2021 02:12:27 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: zhiguang.liu@intel.com) IronPort-SDR: Poii05tApGEr4m/H7wWdGPsAe0b8ZzLYNJNWbkA4OqNl2Ylk4yK9shaCCA47Fct6l08UgRu5kx Sp8YD5iZdlcQ== X-IronPort-AV: E=McAfee;i="6200,9189,10015"; a="185647619" X-IronPort-AV: E=Sophos;i="5.83,275,1616482800"; d="scan'208";a="185647619" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2021 02:12:27 -0700 IronPort-SDR: /TYSUpmCBjwOKQbza6rvmdjkwVFl8m6Of7uNK3+BakoUqAvoD680rdWV0fCfCMX/pNuxu9l/BA dq+hH8FyjLFg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,275,1616482800"; d="scan'208";a="487713163" Received: from fieedk002.ccr.corp.intel.com ([10.239.158.144]) by fmsmga002.fm.intel.com with ESMTP; 15 Jun 2021 02:12:25 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Maurice Ma , Guo Dong , Benjamin You Subject: [Patch V5 3/9] UefiPayloadPkg: UefiPayload retrieve PCI root bridge from Guid Hob Date: Tue, 15 Jun 2021 17:12:05 +0800 Message-Id: <20210615091211.801-4-zhiguang.liu@intel.com> X-Mailer: git-send-email 2.30.0.windows.2 In-Reply-To: <20210615091211.801-1-zhiguang.liu@intel.com> References: <20210615091211.801-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable UefiPayload parse gUniversalPayloadPciRootBridgeInfoGuid Guid Hob to retrieve PCI root bridges information. gUniversalPayloadPciRootBridgeInfoGuid Guid Hob should be created by Bootloader. Cc: Maurice Ma Cc: Guo Dong Cc: Benjamin You Reviewed-by: Guo Dong Signed-off-by: Zhiguang Liu --- UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h | 40 ++++++= ++++++++++++++++++++++++++++++++-- UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 47 ++++++= ++++++++++++++++++++++++++++++++++++++--- UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 8 ++++++= +- UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 73 ++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- UefiPayloadPkg/UefiPayloadPkg.dsc | 2 +- 5 files changed, 162 insertions(+), 8 deletions(-) diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h b/Uefi= PayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h index c2961b3bee..3eee1fbeac 100644 --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h @@ -2,7 +2,7 @@ Header file of PciHostBridgeLib.=0D =0D Copyright (C) 2016, Red Hat, Inc.=0D - Copyright (c) 2016, Intel Corporation. All rights reserved.
=0D + Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -11,14 +11,38 @@ #ifndef _PCI_HOST_BRIDGE_H=0D #define _PCI_HOST_BRIDGE_H=0D =0D +#include =0D +=0D typedef struct {=0D ACPI_HID_DEVICE_PATH AcpiDevicePath;=0D EFI_DEVICE_PATH_PROTOCOL EndDevicePath;=0D } CB_PCI_ROOT_BRIDGE_DEVICE_PATH;=0D =0D +/**=0D + Scan for all root bridges in platform.=0D +=0D + @param[out] NumberOfRootBridges Number of root bridges detected=0D +=0D + @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.=0D +**/=0D PCI_ROOT_BRIDGE *=0D ScanForRootBridges (=0D - UINTN *NumberOfRootBridges=0D + OUT UINTN *NumberOfRootBridges=0D +);=0D +=0D +/**=0D + Scan for all root bridges from Universal Payload PciRootBridgeInfoHob=0D +=0D + @param[in] PciRootBridgeInfo Pointer of Universal Payload PCI Root B= ridge Info Hob=0D + @param[out] NumberOfRootBridges Number of root bridges detected=0D +=0D + @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.=0D +=0D +**/=0D +PCI_ROOT_BRIDGE *=0D +RetrieveRootBridgeInfoFromHob (=0D + IN UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES *PciRootBridgeInfo,=0D + OUT UINTN *NumberOfRootBridges=0D );=0D =0D /**=0D @@ -77,4 +101,16 @@ InitRootBridge ( OUT PCI_ROOT_BRIDGE *RootBus=0D );=0D =0D +/**=0D + Initialize DevicePath for a PCI_ROOT_BRIDGE.=0D + @param[in] HID HID for device path=0D + @param[in] UID UID for device path=0D +=0D + @retval A pointer to the new created device patch.=0D +**/=0D +EFI_DEVICE_PATH_PROTOCOL *=0D +CreateRootBridgeDevicePath (=0D + IN UINT32 HID,=0D + IN UINT32 UID=0D +);=0D #endif=0D diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/U= efiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c index 512c3127cc..a0d7cdc306 100644 --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -2,7 +2,7 @@ Library instance of PciHostBridgeLib library class for coreboot.=0D =0D Copyright (C) 2016, Red Hat, Inc.=0D - Copyright (c) 2016, Intel Corporation. All rights reserved.
=0D + Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -19,6 +19,7 @@ #include =0D #include =0D #include =0D +#include =0D =0D #include "PciHostBridge.h"=0D =0D @@ -48,7 +49,6 @@ CB_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTempl= ate =3D { }=0D };=0D =0D -=0D /**=0D Initialize a PCI_ROOT_BRIDGE structure.=0D =0D @@ -145,6 +145,27 @@ InitRootBridge ( return EFI_SUCCESS;=0D }=0D =0D +/**=0D + Initialize DevicePath for a PCI_ROOT_BRIDGE.=0D + @param[in] HID HID for device path=0D + @param[in] UID UID for device path=0D +=0D + @retval A pointer to the new created device patch.=0D +**/=0D +EFI_DEVICE_PATH_PROTOCOL *=0D +CreateRootBridgeDevicePath (=0D + IN UINT32 HID,=0D + IN UINT32 UID=0D +)=0D +{=0D + CB_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;=0D + DevicePath =3D AllocateCopyPool (sizeof (mRootBridgeDevicePathTemplate),= =0D + &mRootBridgeDevicePathTemplate);=0D + ASSERT (DevicePath !=3D NULL);=0D + DevicePath->AcpiDevicePath.HID =3D HID;=0D + DevicePath->AcpiDevicePath.UID =3D UID;=0D + return (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;=0D +}=0D =0D /**=0D Return all the root bridge instances in an array.=0D @@ -161,10 +182,30 @@ PciHostBridgeGetRootBridges ( UINTN *Count=0D )=0D {=0D + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES *PciRootBridgeInfo;=0D + EFI_HOB_GUID_TYPE *GuidHob;=0D + UNIVERSAL_PAYLOAD_GENERIC_HEADER *GenericHeader;=0D + //=0D + // Find Universal Payload PCI Root Bridge Info hob=0D + //=0D + GuidHob =3D GetFirstGuidHob (&gUniversalPayloadPciRootBridgeInfoGuid);=0D + if (GuidHob !=3D NULL) {=0D + GenericHeader =3D (UNIVERSAL_PAYLOAD_GENERIC_HEADER *) GET_GUID_HOB_DA= TA (GuidHob);=0D + if ((sizeof(UNIVERSAL_PAYLOAD_GENERIC_HEADER) <=3D GET_GUID_HOB_DATA_S= IZE (GuidHob)) && (GenericHeader->Length <=3D GET_GUID_HOB_DATA_SIZE (GuidH= ob))) {=0D + if ((GenericHeader->Revision =3D=3D UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDG= ES_REVISION) && (GenericHeader->Length >=3D sizeof (UNIVERSAL_PAYLOAD_PCI_R= OOT_BRIDGES))) {=0D + //=0D + // UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES structure is used when Revis= ion equals to UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_REVISION=0D + //=0D + PciRootBridgeInfo =3D (UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES *) GET_G= UID_HOB_DATA (GuidHob);=0D + if (PciRootBridgeInfo->Count <=3D (GET_GUID_HOB_DATA_SIZE (GuidHob= ) - sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES)) / sizeof(UNIVERSAL_PAYLOAD_= PCI_ROOT_BRIDGE)) {=0D + return RetrieveRootBridgeInfoFromHob (PciRootBridgeInfo, Count);= =0D + }=0D + }=0D + }=0D + }=0D return ScanForRootBridges (Count);=0D }=0D =0D -=0D /**=0D Free the root bridge instances array returned from=0D PciHostBridgeGetRootBridges().=0D diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf b= /UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf index 7896df2416..6069dcc0ef 100644 --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf @@ -2,7 +2,7 @@ # Library instance of PciHostBridgeLib library class for coreboot.=0D #=0D # Copyright (C) 2016, Red Hat, Inc.=0D -# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
= =0D +# Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
= =0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -39,3 +39,9 @@ DevicePathLib=0D MemoryAllocationLib=0D PciLib=0D +=0D +[Guids]=0D + gUniversalPayloadPciRootBridgeInfoGuid=0D +=0D +[Pcd]=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration=0D diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c= b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c index fffbf04cad..b0268f0506 100644 --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c @@ -1,7 +1,7 @@ /** @file=0D Scan the entire PCI bus for root bridges to support coreboot UEFI payloa= d.=0D =0D - Copyright (c) 2016, Intel Corporation. All rights reserved.
=0D + Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -582,3 +582,74 @@ ScanForRootBridges ( =0D return RootBridges;=0D }=0D +=0D +/**=0D + Scan for all root bridges from Universal Payload PciRootBridgeInfoHob=0D +=0D + @param[in] PciRootBridgeInfo Pointer of Universal Payload PCI Root B= ridge Info Hob=0D + @param[out] NumberOfRootBridges Number of root bridges detected=0D +=0D + @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.=0D +=0D +**/=0D +PCI_ROOT_BRIDGE *=0D +RetrieveRootBridgeInfoFromHob (=0D + IN UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES *PciRootBridgeInfo,=0D + OUT UINTN *NumberOfRootBridges=0D +)=0D +{=0D + PCI_ROOT_BRIDGE *PciRootBridges;=0D + UINTN Size;=0D + UINT8 Index;=0D +=0D + ASSERT (PciRootBridgeInfo !=3D NULL);=0D + ASSERT (NumberOfRootBridges !=3D NULL);=0D + if (PciRootBridgeInfo =3D=3D NULL) {=0D + return NULL;=0D + }=0D + if (PciRootBridgeInfo->Count =3D=3D 0) {=0D + return NULL;=0D + }=0D + Size =3D PciRootBridgeInfo->Count * sizeof (PCI_ROOT_BRIDGE);=0D + PciRootBridges =3D (PCI_ROOT_BRIDGE *) AllocatePool (Size);=0D + ASSERT (PciRootBridges !=3D NULL);=0D + if (PciRootBridges =3D=3D NULL) {=0D + return NULL;=0D + }=0D + ZeroMem (PciRootBridges, PciRootBridgeInfo->Count * sizeof (PCI_ROOT_BRI= DGE));=0D +=0D + //=0D + // Create all root bridges with PciRootBridgeInfoHob=0D + //=0D + for (Index =3D 0; Index < PciRootBridgeInfo->Count; Index++) {=0D + PciRootBridges[Index].Segment =3D PciRootBridgeInfo->Roo= tBridge[Index].Segment;=0D + PciRootBridges[Index].Supports =3D PciRootBridgeInfo->Roo= tBridge[Index].Supports;=0D + PciRootBridges[Index].Attributes =3D PciRootBridgeInfo->Roo= tBridge[Index].Attributes;=0D + PciRootBridges[Index].DmaAbove4G =3D PciRootBridgeInfo->Roo= tBridge[Index].DmaAbove4G;=0D + PciRootBridges[Index].NoExtendedConfigSpace =3D PciRootBridgeInfo->Roo= tBridge[Index].NoExtendedConfigSpace;=0D + PciRootBridges[Index].ResourceAssigned =3D PciRootBridgeInfo->Res= ourceAssigned;=0D + PciRootBridges[Index].AllocationAttributes =3D PciRootBridgeInfo->Roo= tBridge[Index].AllocationAttributes;=0D + PciRootBridges[Index].DevicePath =3D CreateRootBridgeDevice= Path(PciRootBridgeInfo->RootBridge[Index].HID, PciRootBridgeInfo->RootBridg= e[Index].UID);=0D + CopyMem(&PciRootBridges[Index].Bus, &PciRootBridgeInfo->RootBr= idge[Index].Bus, sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE)= );=0D + CopyMem(&PciRootBridges[Index].Io, &PciRootBridgeInfo->RootBr= idge[Index].Io, sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE)= );=0D + CopyMem(&PciRootBridges[Index].Mem, &PciRootBridgeInfo->RootBr= idge[Index].Mem, sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE)= );=0D + CopyMem(&PciRootBridges[Index].MemAbove4G, &PciRootBridgeInfo->RootBr= idge[Index].MemAbove4G, sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE)= );=0D + CopyMem(&PciRootBridges[Index].PMem, &PciRootBridgeInfo->RootBr= idge[Index].PMem, sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE)= );=0D + CopyMem(&PciRootBridges[Index].PMemAbove4G, &PciRootBridgeInfo->RootBr= idge[Index].PMemAbove4G, sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE)= );=0D + }=0D +=0D + *NumberOfRootBridges =3D PciRootBridgeInfo->Count;=0D +=0D + //=0D + // Now, this library only supports RootBridge that ResourceAssigned is T= rue=0D + //=0D + if (PciRootBridgeInfo->ResourceAssigned) {=0D + PcdSetBoolS (PcdPciDisableBusEnumeration, TRUE);=0D + } else {=0D + DEBUG ((DEBUG_ERROR, "There is root bridge whose ResourceAssigned is F= ALSE\n"));=0D + PcdSetBoolS (PcdPciDisableBusEnumeration, FALSE);=0D + return NULL;=0D + }=0D +=0D + return PciRootBridges;=0D +}=0D diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayload= Pkg.dsc index 37ad5a0ae7..e9211adf86 100644 --- a/UefiPayloadPkg/UefiPayloadPkg.dsc +++ b/UefiPayloadPkg/UefiPayloadPkg.dsc @@ -323,7 +323,6 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONTRO= L)=0D gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EXTE= NDED_TX_FIFO_SIZE)=0D =0D - gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE=0D gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE= )=0D gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS= )=0D gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY)=0D @@ -363,6 +362,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100=0D gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0=0D gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE=0D =0D ##########################################################################= ######=0D #=0D --=20 2.30.0.windows.2