From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) by mx.groups.io with SMTP id smtpd.web12.3564.1623905066239370170 for ; Wed, 16 Jun 2021 21:44:26 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=Hb/mlKMh; spf=pass (domain: ventanamicro.com, ip: 209.85.216.46, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pj1-f46.google.com with SMTP id m13-20020a17090b068db02901656cc93a75so5340666pjz.3 for ; Wed, 16 Jun 2021 21:44:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to; bh=EO+dUp/mBMfwFnO1uyqlW4Cyp8ZYgXAqLVWfxwEY7Y8=; b=Hb/mlKMhm0uZEwqLwpd9MH4OPM6Lh7JBYDvUNLnSdMXWM4UFu0kFy0QMq7r/t2R89R Xes7Kg8dBZTLQ5po7BqIztzmKVXv51tpGMprBGeRXJAXnMUJWA30XDKGwi7gdovTY4xJ 7zZWyZcI4smWQ9QgoxQpfc/odaqa387xXIjeF/DSciiixd0x4H9Iggl2sJb35vd3ODPb BqFZwwzTYPiRoOadSJab6+A+wFT4n+zSTfscveKRGeghQ09Y7aAowq21vfUy2iJIpeou pbis3rSZz/NGKZEYFqr6UKqyrfMUGwCu7GYT0rnT9BqcmzvHOIL/GnkXXqM90vVwIzCs XsNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=EO+dUp/mBMfwFnO1uyqlW4Cyp8ZYgXAqLVWfxwEY7Y8=; b=FtL9qNTS/SzB+kWc2dqEyNX2FPRmrSFUUlDbaFsWJ752Lu9ul1aRCsAirz2HbhCPhw FY1lR/v9Pas5uGgft7+DKvhEpQoaBbnNhvgRtTVGFP7J+x3NN1RA1Cs2nb3XQDn+6uiI GH7lg2uLZ8x+zaobl9uTMC+/znszq5UM2+adDQfjPp5azfZ5NjXbv+UUzlnUwhNkh2fK 7hp8AX7GOGkScvoF0grFErZbSGqjBxCM1GLLW83Quy5zEUVDNotPxZLw2SfQA7sbUJuQ +OmXg3WSd76VM4YFuLmAt05gua2ZE9CDn4+qMow87VexCaYAEgwxhtMUCvdMUhigQBvp Cw9g== X-Gm-Message-State: AOAM533LreibfqnBvUBnn2G2T1hx6iAP1sHd6laeqnKG0ylkyivwRdeu LLofqFr/VEKzL8JSY5YKElR6aQ== X-Google-Smtp-Source: ABdhPJyOj9MO9Oa0RZWJ7w/MIPaVvAAgsbE48E+HzuO5fQ5wUku6CmP8IUWiIKN3VIAOzyIMnsLKYQ== X-Received: by 2002:a17:902:22d:b029:11f:2db4:4c01 with SMTP id 42-20020a170902022db029011f2db44c01mr2869607plc.29.1623905065758; Wed, 16 Jun 2021 21:44:25 -0700 (PDT) Return-Path: Received: from sunil-ThinkPad-T490 ([49.206.3.187]) by smtp.gmail.com with ESMTPSA id o3sm3576768pfd.41.2021.06.16.21.44.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Jun 2021 21:44:25 -0700 (PDT) Date: Thu, 17 Jun 2021 10:14:20 +0530 From: "Sunil V L" To: Pete Batard Cc: devel@edk2.groups.io, daniel.schaefer@hpe.com, "Chang, Abner (HPS SW/FW Technologist)" , Bob Feng , Liming Gao , Yuwei Chen , Heinrich Schuchardt Subject: Re: [edk2-devel] [RESEND PATCH v2] BaseTools: Add support for RISCV GOT/PLT relocations Message-ID: <20210617044420.GA4631@sunil-ThinkPad-T490> References: <20210611140503.28409-1-sunilvl@ventanamicro.com> <20210611140807.GA28471@sunil-ThinkPad-T490> <0fb7313d-9050-cb00-c378-a983a7c80855@akeo.ie> MIME-Version: 1.0 In-Reply-To: <0fb7313d-9050-cb00-c378-a983a7c80855@akeo.ie> Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit Hi Pete, Thank you very much!. On Wed, Jun 16, 2021 at 01:35:27PM +0100, Pete Batard wrote: > Sunil, Daniel, thanks for the patch. > > I confirm that this addresses the 0x13 and 0x14 relocation issues that I was > seeing. > > However, this patch appears to introduces new R_RISCV_PCREL_LO12_S > relocation errors that I was not seeing previously, so I still can't manage > to get a successful compilation. It is not introduced by the patch but looks like one more new relocation type is added by the latest tool chain you are using. Please raise a new bug and I will add the support for it in next patch. Thanks! Sunil > > Especially the stream of 0x13 and 0x14 relocation errors I was getting at > https://github.com/pbatard/ntfs-3g/runs/2278190652?check_suite_focus=true > has now switched to (tested on up to date Ubuntu with latest EDK2): > > ------------------------------------------------------------------------- > "GenFw" -e UEFI_DRIVER -o /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/OUTPUT/ntfs.efi /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll > GenFw: ERROR 3000: Invalid > WriteSections64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll > unsupported ELF EM_RISCV64 relocation 0x19. > GenFw: ERROR 3000: Invalid > WriteSections64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll > unsupported ELF EM_RISCV64 relocation 0x19. > GenFw: ERROR 3000: Invalid > WriteSections64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll > unsupported ELF EM_RISCV64 relocation 0x19. > GenFw: ERROR 3000: Invalid > WriteRelocations64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll > unsupported ELF EM_RISCV64 relocation 0x19. > GenFw: ERROR 3000: Invalid > WriteRelocations64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll > unsupported ELF EM_RISCV64 relocation 0x19. > GenFw: ERROR 3000: Invalid > WriteRelocations64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll > unsupported ELF EM_RISCV64 relocation 0x19. > make: *** [GNUmakefile:553: /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/OUTPUT/ntfs.efi] > Error 2 > ------------------------------------------------------------------------- > > So, in effect, some of the earlier relocation errors appear to have morphed > into 0x19/R_RISCV_PCREL_LO12_S ones... > > I can open a new bug for this issue if you prefer. > > Regards, > > /Pete > > On 2021.06.15 03:26, Daniel Schaefer wrote: > > Great commit message, thanks Sunil! > > Maintainers, please take a look and let us know if there's any other > > concern. > > This patch lets us build the RISC-V platforms using modern toolchains > > that are provided directly by the distributions, rather than building > > your own from source. > > > > Thanks, > > Daniel > > ------------------------------------------------------------------------ > > *From:* Sunil V L > > *Sent:* Friday, June 11, 2021 22:08 > > *To:* devel@edk2.groups.io > > *Cc:* Chang, Abner (HPS SW/FW Technologist) ; > > Schaefer, Daniel ; Bob Feng > > ; Liming Gao ; Yuwei > > Chen ; Heinrich Schuchardt > > *Subject:* Re: [RESEND PATCH v2] BaseTools: Add support for RISCV > > GOT/PLT relocations > > Hi, > >     I just edited the commit message to indicate the module and CC the > >     maintainers. Could I get the feedback please? > > Thanks > > Sunil > > > > On Fri, Jun 11, 2021 at 07:35:03PM +0530, Sunil V L wrote: > > > Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3096 > > > > > > > > This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20 > > > relocations generated by PIE enabled compiler. This also needed > > > changes to R_RISCV_32 and R_RISCV_64 relocations as explained in > > > https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710 > > > > > > > > Changes in v2: > > >    - Addressed Daniel's comment on formatting > > > > > > Testing: > > > 1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models. > > > 2) Debian 10.2.0 and booted QEMU virt model. > > > 3) riscv-gnu-tool chain 9.2 and booted QEMU virt model. > > > > > > Signed-off-by: Sunil V L > > > > > > Acked-by: Abner Chang > > > Reviewed-by: Daniel Schaefer > > > Tested-by: > > > > > > Cc: Bob Feng > > > Cc: Liming Gao > > > Cc: Yuwei Chen > > > Cc: Heinrich Schuchardt > > > --- > > >   BaseTools/Source/C/GenFw/Elf64Convert.c | 44 +++++++++++++++++++++---- > > >   1 file changed, 38 insertions(+), 6 deletions(-) > > > > > > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c > > > index d097db8632..d684318269 100644 > > > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c > > > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c > > > @@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset; > > >   STATIC UINT8       *mRiscVPass1Targ = NULL; > > >   STATIC Elf_Shdr    *mRiscVPass1Sym = NULL; > > >   STATIC Elf64_Half  mRiscVPass1SymSecIndex = 0; > > > +STATIC INT32       mRiscVPass1Offset; > > > +STATIC INT32       mRiscVPass1GotFixup; > > >   // > > >   // Initialization Function > > > @@ -479,11 +481,11 @@ WriteSectionRiscV64 ( > > >       break; > > >     case R_RISCV_32: > > > -    *(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]); > > > +    *(UINT64 *)Targ = Sym->st_value + Rel->r_addend; > > >       break; > > >     case R_RISCV_64: > > > -    *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]; > > > +    *(UINT64 *)Targ = Sym->st_value + Rel->r_addend; > > >       break; > > >     case R_RISCV_HI20: > > > @@ -533,6 +535,18 @@ WriteSectionRiscV64 ( > > >       mRiscVPass1SymSecIndex = 0; > > >       break; > > > +  case R_RISCV_GOT_HI20: > > > +    Value = (Sym->st_value - Rel->r_offset); > > > +    mRiscVPass1Offset = RV_X(Value, 0, 12); > > > +    Value = RV_X(Value, 12, 20); > > > +    *(UINT32 *)Targ = (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12)); > > > + > > > +    mRiscVPass1Targ = Targ; > > > +    mRiscVPass1Sym = SymShdr; > > > +    mRiscVPass1SymSecIndex = Sym->st_shndx; > > > +    mRiscVPass1GotFixup = 1; > > > +    break; > > > + > > >     case R_RISCV_PCREL_HI20: > > >       mRiscVPass1Targ = Targ; > > >       mRiscVPass1Sym = SymShdr; > > > @@ -545,11 +559,17 @@ WriteSectionRiscV64 ( > > >       if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) { > > >         int i; > > >         Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20)); > > > -      Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); > > > -      if(Value & (RISCV_IMM_REACH/2)) { > > > -        Value |= ~(RISCV_IMM_REACH-1); > > > + > > > +      if(mRiscVPass1GotFixup) { > > > +        Value = (UINT32)(mRiscVPass1Offset); > > > +      } else { > > > +        Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); > > > +        if(Value & (RISCV_IMM_REACH/2)) { > > > +          Value |= ~(RISCV_IMM_REACH-1); > > > +        } > > >         } > > >         Value = Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOffset[mRiscVPass1SymSecIndex]; > > > + > > >         if(-2048 > (INT32)Value) { > > >           i = (((INT32)Value * -1) / 4096); > > >           Value2 -= i; > > > @@ -569,12 +589,21 @@ WriteSectionRiscV64 ( > > >           } > > >         } > > > -      *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20)); > > > +      if(mRiscVPass1GotFixup) { > > > +        *(UINT32 *)Targ = (RV_X((UINT32)Value, 0, 12) << 20) > > > +                            | (RV_X(*(UINT32*)Targ, 0, 20)); > > > +        /* Convert LD instruction to ADDI */ > > > +        *(UINT32 *)Targ = ((*(UINT32 *)Targ & ~0x707f) | 0x13); > > > +      } else { > > > +        *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20)); > > > +      } > > >         *(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12)); > > >       } > > >       mRiscVPass1Sym = NULL; > > >       mRiscVPass1Targ = NULL; > > >       mRiscVPass1SymSecIndex = 0; > > > +    mRiscVPass1Offset = 0; > > > +    mRiscVPass1GotFixup = 0; > > >       break; > > >     case R_RISCV_ADD64: > > > @@ -586,6 +615,7 @@ WriteSectionRiscV64 ( > > >     case R_RISCV_GPREL_I: > > >     case R_RISCV_GPREL_S: > > >     case R_RISCV_CALL: > > > +  case R_RISCV_CALL_PLT: > > >     case R_RISCV_RVC_BRANCH: > > >     case R_RISCV_RVC_JUMP: > > >     case R_RISCV_RELAX: > > > @@ -1528,6 +1558,7 @@ WriteRelocations64 ( > > >               case R_RISCV_GPREL_I: > > >               case R_RISCV_GPREL_S: > > >               case R_RISCV_CALL: > > > +            case R_RISCV_CALL_PLT: > > >               case R_RISCV_RVC_BRANCH: > > >               case R_RISCV_RVC_JUMP: > > >               case R_RISCV_RELAX: > > > @@ -1537,6 +1568,7 @@ WriteRelocations64 ( > > >               case R_RISCV_SET16: > > >               case R_RISCV_SET32: > > >               case R_RISCV_PCREL_HI20: > > > +            case R_RISCV_GOT_HI20: > > >               case R_RISCV_PCREL_LO12_I: > > >                 break; > > > -- > > > 2.25.1 > > > > > >