From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) by mx.groups.io with SMTP id smtpd.web12.3575.1623905192287529501 for ; Wed, 16 Jun 2021 21:46:32 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=aco5WtQW; spf=pass (domain: ventanamicro.com, ip: 209.85.210.169, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pf1-f169.google.com with SMTP id q25so3979125pfh.7 for ; Wed, 16 Jun 2021 21:46:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to; bh=W/0fAaq2p2ntlE3aJohhVmn/poDiElYcNDhWs+UVuqw=; b=aco5WtQWhGVwZlL4N/QOhk3AATBehWG4MR/QkYZYQpYVC+mj2eRTiFtVe0H0DXBu+P Hjmy5JCZipELuD5p00577g/aO1SsC29Y5TqvLXyrq7+sI/Oopt3NNPORR0AXcs3qOMeX NHfem7DqqNZ/2X6WiPmt/ztprlqBYZVnko6kN3FhAeiD5ZtNp+b80EXb2t6skYDvN4FL lOdJgh383+Veqaqf4yKOSM9/xT0zSyPZJqPrgsNBc3NaVmIkg1AxroBRiy2Yq+0yFmLX LfzmKrZqqaEMbdMSRiZIPRXVGYl9Zvc/OQ4F6ZdYdRQtxAuovZYuaq/2UIhXFnT5sdqP QZpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=W/0fAaq2p2ntlE3aJohhVmn/poDiElYcNDhWs+UVuqw=; b=KT4697DGN/B48VUktN9KS+zNhBVxDlDwAPMkUBo2Qr2wRpWLgYavBh8XM7CHrnk6S0 e6P9wv6GAjwzSDobHsHnH1ZCWT5hPhFvj1w1GUMC+gaqNmc4TUp2hzK0S/6z3mHWVOcd S2B7FuzioyDaF4xTd8WkDfaj/i6IEx7Xlf2Zg9TqX2+35OOMEtDSp3dXFdeMyr/Hb7S1 wXF32wdQeSnJ9ZpmzEl5sjbQzme342+58lGHHUXVFRkCB6F0l7B37T4p/iau10tmJjV+ wYWRytu/Rzpp9wlr2hpKij4Ja78Z3HXfKjl3+GvsroTFE7Aa2hTxLPLws+c8ntd5ArJj 7S2A== X-Gm-Message-State: AOAM532l0oTbpJeZD3V1AnlpNM7WDyTeFK7FUpx3T7QaK90XGPjIt+60 /urEpjvOcTk2QrKIZbU5ZgStfTFjs7e6PtFH X-Google-Smtp-Source: ABdhPJyedfTFmOT/LTDxMX79TW2jabvlHAyBER24YoaE7paoOAp9Pkbe6au2+hG0zPHs3d6eD3s/qQ== X-Received: by 2002:a63:e316:: with SMTP id f22mr3193636pgh.100.1623905191672; Wed, 16 Jun 2021 21:46:31 -0700 (PDT) Return-Path: Received: from sunil-ThinkPad-T490 ([49.206.3.187]) by smtp.gmail.com with ESMTPSA id e2sm6747605pjc.37.2021.06.16.21.46.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Jun 2021 21:46:31 -0700 (PDT) Date: Thu, 17 Jun 2021 10:16:26 +0530 From: "Sunil V L" To: devel@edk2.groups.io, gaoliming@byosoft.com.cn Cc: 'Abner Chang' , 'Daniel Schaefer' , 'Bob Feng' , 'Yuwei Chen' , 'Heinrich Schuchardt' Subject: =?UTF-8?B?UmU6IFtlZGsyLWRldmVsXSDlm57lpI06IFtSRVNFTkQgUEFUQ0ggdjJdIEJhc2VUb29sczogQWRkIHN1cHBvcnQgZm9yIFJJU0NWIEdPVC9QTFQgcmVsb2NhdGlvbnM=?= Message-ID: <20210617044626.GB4631@sunil-ThinkPad-T490> References: <20210611140503.28409-1-sunilvl@ventanamicro.com> <004901d7631a$28140860$783c1920$@byosoft.com.cn> MIME-Version: 1.0 In-Reply-To: <004901d7631a$28140860$783c1920$@byosoft.com.cn> Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit Hi Liming, Thank you very much for the review. On Thu, Jun 17, 2021 at 09:43:21AM +0800, gaoliming wrote: > Sunil: > I add my comments below. > > Thanks > Liming > > -----邮件原件----- > > 发件人: Sunil V L > > 发送时间: 2021年6月11日 22:05 > > 收件人: devel@edk2.groups.io > > 抄送: Sunil V L ; Abner Chang > > ; Daniel Schaefer ; Bob > > Feng ; Liming Gao ; > > Yuwei Chen ; Heinrich Schuchardt > > > > 主题: [RESEND PATCH v2] BaseTools: Add support for RISCV GOT/PLT > > relocations > > > > Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3096 > > > > This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20 > > relocations generated by PIE enabled compiler. This also needed > > changes to R_RISCV_32 and R_RISCV_64 relocations as explained in > > https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-8466 > > 82710 > > > > Changes in v2: > > - Addressed Daniel's comment on formatting > > > > Testing: > > 1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models. > > 2) Debian 10.2.0 and booted QEMU virt model. > > 3) riscv-gnu-tool chain 9.2 and booted QEMU virt model. > > > > Signed-off-by: Sunil V L > > > > Acked-by: Abner Chang > > Reviewed-by: Daniel Schaefer > > Tested-by: > > Tested-By format is invalid. Its format is same Reviewed-by. Sure. Will fix it. > > > > > Cc: Bob Feng > > Cc: Liming Gao > > Cc: Yuwei Chen > > Cc: Heinrich Schuchardt > > --- > > BaseTools/Source/C/GenFw/Elf64Convert.c | 44 > > +++++++++++++++++++++---- > > 1 file changed, 38 insertions(+), 6 deletions(-) > > > > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c > > b/BaseTools/Source/C/GenFw/Elf64Convert.c > > index d097db8632..d684318269 100644 > > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c > > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c > > @@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset; > > STATIC UINT8 *mRiscVPass1Targ = NULL; > > > > STATIC Elf_Shdr *mRiscVPass1Sym = NULL; > > > > STATIC Elf64_Half mRiscVPass1SymSecIndex = 0; > > > > +STATIC INT32 mRiscVPass1Offset; > > > > +STATIC INT32 mRiscVPass1GotFixup; > > > > > > > > // > > > > // Initialization Function > > > > @@ -479,11 +481,11 @@ WriteSectionRiscV64 ( > > break; > > > > > > > > case R_RISCV_32: > > > > - *(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) - > > SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]); > > > > + *(UINT64 *)Targ = Sym->st_value + Rel->r_addend; > > > > break; > > > > > > > > case R_RISCV_64: > > > > - *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + > > mCoffSectionsOffset[Sym->st_shndx]; > > > > + *(UINT64 *)Targ = Sym->st_value + Rel->r_addend; > > > > break; > > > > > > > > case R_RISCV_HI20: > > > > @@ -533,6 +535,18 @@ WriteSectionRiscV64 ( > > mRiscVPass1SymSecIndex = 0; > > > > break; > > > > > > > > + case R_RISCV_GOT_HI20: > > > > + Value = (Sym->st_value - Rel->r_offset); > > > > + mRiscVPass1Offset = RV_X(Value, 0, 12); > > > > + Value = RV_X(Value, 12, 20); > > > > + *(UINT32 *)Targ = (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12)); > > > > + > > > > + mRiscVPass1Targ = Targ; > > > > + mRiscVPass1Sym = SymShdr; > > > > + mRiscVPass1SymSecIndex = Sym->st_shndx; > > > > + mRiscVPass1GotFixup = 1; > > > > + break; > > > > + > > > > case R_RISCV_PCREL_HI20: > > > > mRiscVPass1Targ = Targ; > > > > mRiscVPass1Sym = SymShdr; > > > > @@ -545,11 +559,17 @@ WriteSectionRiscV64 ( > > if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && > > mRiscVPass1SymSecIndex != 0) { > > > > int i; > > > > Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20)); > > > > - Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); > > > > - if(Value & (RISCV_IMM_REACH/2)) { > > > > - Value |= ~(RISCV_IMM_REACH-1); > > > > + > > > > + if(mRiscVPass1GotFixup) { > > > > + Value = (UINT32)(mRiscVPass1Offset); > > > > + } else { > > > > + Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); > > > > + if(Value & (RISCV_IMM_REACH/2)) { > > > > + Value |= ~(RISCV_IMM_REACH-1); > > > > + } > > > > } > > > > Value = Value - (UINT32)mRiscVPass1Sym->sh_addr + > > mCoffSectionsOffset[mRiscVPass1SymSecIndex]; > > > > + > > > > if(-2048 > (INT32)Value) { > > > > i = (((INT32)Value * -1) / 4096); > > > > Value2 -= i; > > > > @@ -569,12 +589,21 @@ WriteSectionRiscV64 ( > > } > > > > } > > > > > > > > - *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | > (RV_X(*(UINT32*)Targ, > > 0, 20)); > > > > + if(mRiscVPass1GotFixup) { > > > > + *(UINT32 *)Targ = (RV_X((UINT32)Value, 0, 12) << 20) > > > > + | (RV_X(*(UINT32*)Targ, 0, 20)); > > > > + /* Convert LD instruction to ADDI */ > > > > + *(UINT32 *)Targ = ((*(UINT32 *)Targ & ~0x707f) | 0x13); > > > Can you add the comments for the hard value 0x707f and 0x13? Sure. Will add. Thanks Sunil > > Thanks > Liming > > > + } else { > > > > + *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | > > (RV_X(*(UINT32*)Targ, 0, 20)); > > > > + } > > > > *(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) | > > (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12)); > > > > } > > > > mRiscVPass1Sym = NULL; > > > > mRiscVPass1Targ = NULL; > > > > mRiscVPass1SymSecIndex = 0; > > > > + mRiscVPass1Offset = 0; > > > > + mRiscVPass1GotFixup = 0; > > > > break; > > > > > > > > case R_RISCV_ADD64: > > > > @@ -586,6 +615,7 @@ WriteSectionRiscV64 ( > > case R_RISCV_GPREL_I: > > > > case R_RISCV_GPREL_S: > > > > case R_RISCV_CALL: > > > > + case R_RISCV_CALL_PLT: > > > > case R_RISCV_RVC_BRANCH: > > > > case R_RISCV_RVC_JUMP: > > > > case R_RISCV_RELAX: > > > > @@ -1528,6 +1558,7 @@ WriteRelocations64 ( > > case R_RISCV_GPREL_I: > > > > case R_RISCV_GPREL_S: > > > > case R_RISCV_CALL: > > > > + case R_RISCV_CALL_PLT: > > > > case R_RISCV_RVC_BRANCH: > > > > case R_RISCV_RVC_JUMP: > > > > case R_RISCV_RELAX: > > > > @@ -1537,6 +1568,7 @@ WriteRelocations64 ( > > case R_RISCV_SET16: > > > > case R_RISCV_SET32: > > > > case R_RISCV_PCREL_HI20: > > > > + case R_RISCV_GOT_HI20: > > > > case R_RISCV_PCREL_LO12_I: > > > > break; > > > > > > > > -- > > 2.25.1 > > > > > > > >