From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f44.google.com (mail-pj1-f44.google.com [209.85.216.44]) by mx.groups.io with SMTP id smtpd.web08.5687.1624009722324895840 for ; Fri, 18 Jun 2021 02:48:42 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmail.com header.s=20161025 header.b=KO69iaYg; spf=pass (domain: gmail.com, ip: 209.85.216.44, mailfrom: kuqin12@gmail.com) Received: by mail-pj1-f44.google.com with SMTP id pf4-20020a17090b1d84b029016f6699c3f2so442023pjb.0 for ; Fri, 18 Jun 2021 02:48:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kuj7HlFwBaCboB5/bEsp0/ovqfCBXZycIjMHsHJphTM=; b=KO69iaYgpB3p0/sdx99qCFS03d85KXBTcxGdYJ4yb5PIiYDvnYZrZjekI/50AMTHBg AoqOAOkMwqJC6amuemX78lXLkk2VJV+f33gw0m/BUoXXSJ8D7lK0L6HGYDEqJvky4seT Pt3L7QmA+LnpFhgDa3DcuR9b/o59s+68MhkQAffWnZJKIOYEmXB2TCAA38vLilxp/115 UbEgDtQH1BcMqeblxR6iJqQP2Ad6IfHvsEHspyDa9M+Xy61zjvgtQgzBaEcQw/AMu94w NzZUeHfoTrUyPHX81tNz1oboA8WNTFzZdGygsWDyS7kc72JkPCo2zd4rB1VFMz1l+GLU WhVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kuj7HlFwBaCboB5/bEsp0/ovqfCBXZycIjMHsHJphTM=; b=kTCbIbaEfuLXvMEKNmSOsCmHs8aatPC/siX/rzyZKJP8JjsfioGO15wiXysx2NkFoL 1zQIfzJV9uZaJbl80b3l/rjXsbfqg4j+P9ERCpYhyE2Ws4UeUBxlRgxOvZ2UGOkqeE8v Q+NOOk9OsxqRS2mIshIMoZqPmtbHAbwLW42qczZA+s9skN+trfualFtu/5s1vo3uMdMp QNOWAdLwHDJquBXfMY+8GkxCiw2WJJwmjyifETY9+sYYsSM/fO+wdOKAj0yzoe+dtcuA F3JAK2+Rw7Gi/lyqa2RrI/3K21dTUaMMLMsoimO5L8/zcrttfDI2nwWrUpMuOLSry6r9 JCig== X-Gm-Message-State: AOAM530B0WBSGnpHNJWA9SkTekWVxZbp/WZY+jqdHuod52SUegqtVsBj O3s3udZ+TcfivD6WuwN0m4a5/AFE3y5M2A== X-Google-Smtp-Source: ABdhPJzMeXdQl2KpC9CAGqN5z/T4opUtyaxtPjkPfg/uEd3gWeN8TITp5j7Oduis7O0sxd10rtPlJA== X-Received: by 2002:a17:903:31d3:b029:ee:bccd:e686 with SMTP id v19-20020a17090331d3b02900eebccde686mr4149748ple.1.1624009721727; Fri, 18 Jun 2021 02:48:41 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([50.35.88.161]) by smtp.gmail.com with ESMTPSA id j7sm12930291pjf.0.2021.06.18.02.48.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Jun 2021 02:48:41 -0700 (PDT) From: "Kun Qin" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Michael Kubacki Subject: [PATCH v1 2/2] MdePkg: MmConfiguration: Added definition of MM Configuration PPI Date: Fri, 18 Jun 2021 02:48:29 -0700 Message-Id: <20210618094829.2651-3-kuqin12@gmail.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20210618094829.2651-1-kuqin12@gmail.com> References: <20210618094829.2651-1-kuqin12@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3440 MM Configuration PPI was defined in PI Specification since v1.5. This change added definition of such PPI and related GUIDs into MdePkg. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Michael Kubacki Signed-off-by: Kun Qin --- MdePkg/Include/Ppi/MmConfiguration.h | 62 ++++++++++++++++++++ MdePkg/MdePkg.dec | 3 + 2 files changed, 65 insertions(+) diff --git a/MdePkg/Include/Ppi/MmConfiguration.h b/MdePkg/Include/Ppi/MmConfiguration.h new file mode 100644 index 000000000000..f950322b3877 --- /dev/null +++ b/MdePkg/Include/Ppi/MmConfiguration.h @@ -0,0 +1,62 @@ +/** @file + EFI MM Configuration PPI as defined in PI 1.5 specification. + + This PPI is used to: + 1) report the portions of MMRAM regions which cannot be used for the MMRAM heap. + 2) register the MM Foundation entry point with the processor code. The entry + point will be invoked by the MM processor entry code. + + Copyright (c) Microsoft Corporation. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef MM_CONFIGURATION_PPI_H_ +#define MM_CONFIGURATION_PPI_H_ + +#include + +#define EFI_PEI_MM_CONFIGURATION_PPI_GUID \ + { \ + 0xc109319, 0xc149, 0x450e, { 0xa3, 0xe3, 0xb9, 0xba, 0xdd, 0x9d, 0xc3, 0xa4 } \ + } + +typedef struct _EFI_PEI_MM_CONFIGURATION_PPI EFI_PEI_MM_CONFIGURATION_PPI; + +/** + This function registers the MM Foundation entry point with the processor code. This entry point will be + invoked by the MM Processor entry code as defined in PI specification. + + @param[in] This The EFI_PEI_MM_CONFIGURATION_PPI instance. + @param[in] MmEntryPoint MM Foundation entry point. + + @retval EFI_SUCCESS The entry-point was successfully registered. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MM_REGISTER_MM_ENTRY) ( + IN CONST EFI_PEI_MM_CONFIGURATION_PPI *This, + IN EFI_MM_ENTRY_POINT MmEntryPoint + ); + +/// +/// This PPI is a PPI published by a CPU PEIM to indicate which areas within MMRAM are reserved for use by +/// the CPU for any purpose, such as stack, save state or MM entry point. If a platform chooses to let a CPU +/// PEIM do MMRAM relocation, this PPI must be produced by this CPU PEIM. +/// +/// The MmramReservedRegions points to an array of one or more EFI_MM_RESERVED_MMRAM_REGION structures, with +/// the last structure having the MmramReservedSize set to 0. An empty array would contain only the last +/// structure. +/// +/// The RegisterMmEntry() function allows the MM IPL PEIM to register the MM Foundation entry point with the +/// MM entry vector code. +/// +struct _EFI_PEI_MM_CONFIGURATION_PPI { + EFI_MM_RESERVED_MMRAM_REGION *MmramReservedRegions; + EFI_PEI_MM_REGISTER_MM_ENTRY RegisterMmEntry; +}; + +extern EFI_GUID gEfiPeiMmConfigurationPpi; + +#endif diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index b49f88d8e18f..c5319fdd71ca 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -983,6 +983,9 @@ [Ppis] ## Include/Ppi/MmControl.h gEfiPeiMmControlPpiGuid = { 0x61c68702, 0x4d7e, 0x4f43, { 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }} + ## Include/Ppi/MmConfiguration.h + gEfiPeiMmConfigurationPpi = { 0xc109319, 0xc149, 0x450e, { 0xa3, 0xe3, 0xb9, 0xba, 0xdd, 0x9d, 0xc3, 0xa4 } } + # # PPIs defined in PI 1.7. # -- 2.31.1.windows.1