From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) by mx.groups.io with SMTP id smtpd.web09.7488.1624541139168415638 for ; Thu, 24 Jun 2021 06:25:39 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=O5luKr2Y; spf=pass (domain: ventanamicro.com, ip: 209.85.216.53, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pj1-f53.google.com with SMTP id s17-20020a17090a8811b029016e89654f93so5916473pjn.1 for ; Thu, 24 Jun 2021 06:25:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=j/0uTnJUMvolmAxBh2+gxJtZCLI6FgGk3HH918V5XDM=; b=O5luKr2YFu9NzuAI+nm797TacZtGnHOfsq1bA+CMVsb0+GSmr3QagFhnJiVBIA2JG0 Z3SVBjlJsDpWsJ3e7WuRLQ+8ZQGm6M30x1fPj4aoGz8tNgVw+VjQJnQkj3vQefGgQ5rp 9Jmf3aInhtINltfLmEYaRSJZRjMnT0MdWXQAVPRym+MiCMDYjbh96bpAu6runAZ+ra1g pm3b9kMWlsYz4NJZYg3sX3o36uuTjDB8kLjzZjPvBX/P58h5J6ZLS39PCkVT0DiNnoyb SUd4gxGrLN3+s2O5nf+i4FxV/WP1Ba+kqlC9P9TMvTMzTa8fmVhyR0roOskOL3TaQbJx hSHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=j/0uTnJUMvolmAxBh2+gxJtZCLI6FgGk3HH918V5XDM=; b=KB5+a4MqIpRSg7A68BN/FTyEpT+XXemNZcTi4WTxK5b/3IzzoOSSUv2jIjFVYnkJ8l wmUHRl5H7UqoFhMOlq5lbVl0liPvoPVpwDdSK4XxY+OSiBgJmLtKu3+6W+69R2dAbXf9 nTainzXdHm5V0irOzwP5Wi5ucOTrSGjc6Q1tmArvIuxdIU4gmEqabvuXMSAg4MMehPu2 veqB92b9Bu9DKVnRu2er5sadk+3utUhhYmdTUNHGEftbBtyBZeVnJkc0mp8FMYsPeMqZ wrSQuNJe8JQzt2bDbdTSwUs8OGFF8gP5U5LpYHVegFZ12z1U3qKtI3A+go4yR2FWqqvh rvFA== X-Gm-Message-State: AOAM530UqV5LQUd99vAdAN2JL7NOB3iwqTLjV2/Xq183YRT93ncs0JS1 XbX0JI6xTWZ8fnX5mY+hOSX9aaZQTNZ5FG3Z X-Google-Smtp-Source: ABdhPJwqfWtAzyxS0SD3eZHavzMsQxnSjmkLRVv9ZBH5gKvpYDhakSK0Db7TrykctVmc/hVp8FJAhQ== X-Received: by 2002:a17:902:8ec7:b029:119:a15f:3a1c with SMTP id x7-20020a1709028ec7b0290119a15f3a1cmr4565707plo.48.1624541138427; Thu, 24 Jun 2021 06:25:38 -0700 (PDT) Return-Path: Received: from sunil-ThinkPad-T490.dc1.ventanamicro.com ([49.206.3.187]) by smtp.gmail.com with ESMTPSA id q125sm2989900pfb.193.2021.06.24.06.25.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Jun 2021 06:25:38 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Sunil V L , Abner Chang , Daniel Schaefer , Bob Feng , Liming Gao , Yuwei Chen , Heinrich Schuchardt Subject: [PATCH v4] BaseTools GenFw: Add support for RISCV GOT/PLT relocations Date: Thu, 24 Jun 2021 18:55:31 +0530 Message-Id: <20210624132531.54062-1-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3096 This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20 relocations generated by PIE enabled compiler. This also needed changes to R_RISCV_32 and R_RISCV_64 relocations as explained in https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682= 710 Changes in v4: - Fixed the typecast issue found by VS2019. Changes in v3: - Added the comments to address Liming's feedback. Changes in v2: - Addressed Daniel's comment on formatting Testing: 1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models. 2) Debian 10.2.0 and booted QEMU virt model. 3) riscv-gnu-tool chain 9.2 and booted QEMU virt model. Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Daniel Schaefer Tested-by: Daniel Schaefer Cc: Bob Feng Cc: Liming Gao Cc: Yuwei Chen Cc: Heinrich Schuchardt --- BaseTools/Source/C/GenFw/Elf64Convert.c | 59 ++++++++++++++++++++++--- 1 file changed, 53 insertions(+), 6 deletions(-) diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/G= enFw/Elf64Convert.c index d097db8632..f86be95fbb 100644 --- a/BaseTools/Source/C/GenFw/Elf64Convert.c +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c @@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset; STATIC UINT8 *mRiscVPass1Targ =3D NULL;=0D STATIC Elf_Shdr *mRiscVPass1Sym =3D NULL;=0D STATIC Elf64_Half mRiscVPass1SymSecIndex =3D 0;=0D +STATIC INT32 mRiscVPass1Offset;=0D +STATIC INT32 mRiscVPass1GotFixup;=0D =0D //=0D // Initialization Function=0D @@ -473,17 +475,18 @@ WriteSectionRiscV64 ( {=0D UINT32 Value;=0D UINT32 Value2;=0D + Elf64_Addr GOTEntryRva;=0D =0D switch (ELF_R_TYPE(Rel->r_info)) {=0D case R_RISCV_NONE:=0D break;=0D =0D case R_RISCV_32:=0D - *(UINT32 *)Targ =3D (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_a= ddr + mCoffSectionsOffset[Sym->st_shndx]);=0D + *(UINT64 *)Targ =3D Sym->st_value + Rel->r_addend;=0D break;=0D =0D case R_RISCV_64:=0D - *(UINT64 *)Targ =3D *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSections= Offset[Sym->st_shndx];=0D + *(UINT64 *)Targ =3D Sym->st_value + Rel->r_addend;=0D break;=0D =0D case R_RISCV_HI20:=0D @@ -533,6 +536,18 @@ WriteSectionRiscV64 ( mRiscVPass1SymSecIndex =3D 0;=0D break;=0D =0D + case R_RISCV_GOT_HI20:=0D + GOTEntryRva =3D (Sym->st_value - Rel->r_offset);=0D + mRiscVPass1Offset =3D RV_X(GOTEntryRva, 0, 12);=0D + Value =3D (UINT32)RV_X(GOTEntryRva, 12, 20);=0D + *(UINT32 *)Targ =3D (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12));=0D +=0D + mRiscVPass1Targ =3D Targ;=0D + mRiscVPass1Sym =3D SymShdr;=0D + mRiscVPass1SymSecIndex =3D Sym->st_shndx;=0D + mRiscVPass1GotFixup =3D 1;=0D + break;=0D +=0D case R_RISCV_PCREL_HI20:=0D mRiscVPass1Targ =3D Targ;=0D mRiscVPass1Sym =3D SymShdr;=0D @@ -545,11 +560,17 @@ WriteSectionRiscV64 ( if (mRiscVPass1Targ !=3D NULL && mRiscVPass1Sym !=3D NULL && mRiscVPas= s1SymSecIndex !=3D 0) {=0D int i;=0D Value2 =3D (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));=0D - Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));=0D - if(Value & (RISCV_IMM_REACH/2)) {=0D - Value |=3D ~(RISCV_IMM_REACH-1);=0D +=0D + if(mRiscVPass1GotFixup) {=0D + Value =3D (UINT32)(mRiscVPass1Offset);=0D + } else {=0D + Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));=0D + if(Value & (RISCV_IMM_REACH/2)) {=0D + Value |=3D ~(RISCV_IMM_REACH-1);=0D + }=0D }=0D Value =3D Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOff= set[mRiscVPass1SymSecIndex];=0D +=0D if(-2048 > (INT32)Value) {=0D i =3D (((INT32)Value * -1) / 4096);=0D Value2 -=3D i;=0D @@ -569,12 +590,35 @@ WriteSectionRiscV64 ( }=0D }=0D =0D - *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Tar= g, 0, 20));=0D + if(mRiscVPass1GotFixup) {=0D + *(UINT32 *)Targ =3D (RV_X((UINT32)Value, 0, 12) << 20)=0D + | (RV_X(*(UINT32*)Targ, 0, 20));=0D + // Convert LD instruction to ADDI=0D + //=0D + // |31 20|19 15|14 12|11 7|6 0|=0D + // |-----------------------------------------|=0D + // |imm[11:0] | rs1 | 011 | rd | 0000011 | LD=0D + // -----------------------------------------=0D +=0D + // |-----------------------------------------|=0D + // |imm[11:0] | rs1 | 000 | rd | 0010011 | ADDI=0D + // -----------------------------------------=0D +=0D + // To convert, let's first reset bits 12-14 and 0-6 using ~0x707f= =0D + // Then modify the opcode to ADDI (0010011)=0D + // All other fields will remain same.=0D +=0D + *(UINT32 *)Targ =3D ((*(UINT32 *)Targ & ~0x707f) | 0x13);=0D + } else {=0D + *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)T= arg, 0, 20));=0D + }=0D *(UINT32 *)mRiscVPass1Targ =3D (RV_X(Value2, 0, 20)<<12) | (RV_X(*(U= INT32 *)mRiscVPass1Targ, 0, 12));=0D }=0D mRiscVPass1Sym =3D NULL;=0D mRiscVPass1Targ =3D NULL;=0D mRiscVPass1SymSecIndex =3D 0;=0D + mRiscVPass1Offset =3D 0;=0D + mRiscVPass1GotFixup =3D 0;=0D break;=0D =0D case R_RISCV_ADD64:=0D @@ -586,6 +630,7 @@ WriteSectionRiscV64 ( case R_RISCV_GPREL_I:=0D case R_RISCV_GPREL_S:=0D case R_RISCV_CALL:=0D + case R_RISCV_CALL_PLT:=0D case R_RISCV_RVC_BRANCH:=0D case R_RISCV_RVC_JUMP:=0D case R_RISCV_RELAX:=0D @@ -1528,6 +1573,7 @@ WriteRelocations64 ( case R_RISCV_GPREL_I:=0D case R_RISCV_GPREL_S:=0D case R_RISCV_CALL:=0D + case R_RISCV_CALL_PLT:=0D case R_RISCV_RVC_BRANCH:=0D case R_RISCV_RVC_JUMP:=0D case R_RISCV_RELAX:=0D @@ -1537,6 +1583,7 @@ WriteRelocations64 ( case R_RISCV_SET16:=0D case R_RISCV_SET32:=0D case R_RISCV_PCREL_HI20:=0D + case R_RISCV_GOT_HI20:=0D case R_RISCV_PCREL_LO12_I:=0D break;=0D =0D --=20 2.25.1