From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mx.groups.io with SMTP id smtpd.web10.410.1624656131281843640 for ; Fri, 25 Jun 2021 14:22:11 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="body hash did not verify" header.i=@linux.microsoft.com header.s=default header.b=LT8UuCbG; spf=pass (domain: linux.microsoft.com, ip: 13.77.154.182, mailfrom: mikuback@linux.microsoft.com) Received: from localhost.localdomain (unknown [167.220.2.74]) by linux.microsoft.com (Postfix) with ESMTPSA id EFF7720B83F5; Fri, 25 Jun 2021 14:22:10 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com EFF7720B83F5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1624656131; bh=SMVev3V2fStZr5mFTdIvE+oJmsWpaSBDAe7qq7Ay1c0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LT8UuCbGv8dFZf+bIfckI4caINJMP/sFrZYGQ8k+l2JaZqIZcbGw9tIK9Cxnk1DkX 4kACoB2ghy8fcRgRa5/7UrXX/TQKKxcg8lzRpI/EOyKhue19AmcZMWTmnHi3sg8LiS f5bcmpZUutYzs7coDaGHwZNXYOcRpogyVGCX5RUk= From: "Michael Kubacki" To: devel@edk2.groups.io Cc: Ray Ni , Rangasai V Chaganty , Nate DeSimone Subject: [edk2-platforms][PATCH v4 06/41] IntelSiliconPkg: Add PCH SPI PPI Date: Fri, 25 Jun 2021 17:20:45 -0400 Message-Id: <20210625212120.235-7-mikuback@linux.microsoft.com> X-Mailer: git-send-email 2.28.0.windows.1 In-Reply-To: <20210625212120.235-1-mikuback@linux.microsoft.com> References: <20210625212120.235-1-mikuback@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Kubacki REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3307 This SPI PPI definition is intended to serve as the single definition for Intel platform and silicon packages. Cc: Ray Ni Cc: Rangasai V Chaganty Signed-off-by: Michael Kubacki Reviewed-by: Nate DeSimone --- Silicon/Intel/IntelSiliconPkg/Include/Ppi/Spi.h | 25 +++++++++++++++++= +++ Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 3 +++ 2 files changed, 28 insertions(+) diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Ppi/Spi.h b/Silicon/In= tel/IntelSiliconPkg/Include/Ppi/Spi.h new file mode 100644 index 000000000000..b2410bd17300 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/Ppi/Spi.h @@ -0,0 +1,25 @@ +/** @file + This file defines the PCH SPI PPI which implements the + Intel(R) PCH SPI Host Controller Compatibility Interface. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_SPI_PPI_H_ +#define _PCH_SPI_PPI_H_ + +#include + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPchSpiPpiGuid; + +/** + Reuse the PCH_SPI_PROTOCOL definitions + This is possible becaues the PPI implementation does not rely on a Pei= Service pointer, + as it uses EDKII Glue Lib to do IO accesses +**/ +typedef PCH_SPI_PROTOCOL PCH_SPI_PPI; + +#endif diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/= Intel/IntelSiliconPkg/IntelSiliconPkg.dec index fb8391000347..1fa447f37722 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -71,6 +71,9 @@ [Guids] gEdkiiMicrocodeStorageTypeFlashGuid =3D { 0x2cba01b3, 0xd391, 0x4598, = { 0x8d, 0x89, 0xb7, 0xfc, 0x39, 0x22, 0xfd, 0x71 } } =20 [Ppis] + ## Include/Ppi/Spi.h + gPchSpiPpiGuid =3D { 0x104c7177, 0xc2e6, 0x44f0, { 0xae, 0xe3, 0x9d, 0= x0d, 0x9a, 0x52, 0xca, 0xdf } } + gEdkiiVTdInfoPpiGuid =3D { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0= x67, 0xaf, 0x2b, 0x25, 0x68, 0x4a } } gEdkiiVTdNullRootEntryTableGuid =3D { 0x3de0593f, 0x6e3e, 0x4542, { 0x= a1, 0xcb, 0xcb, 0xb2, 0xdb, 0xeb, 0xd8, 0xff } } =20 --=20 2.28.0.windows.1