From: "Brijesh Singh" <brijesh.singh@amd.com>
To: devel@edk2.groups.io
Cc: James Bottomley <jejb@linux.ibm.com>, Min Xu <min.m.xu@intel.com>,
Jiewen Yao <jiewen.yao@intel.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
Jordan Justen <jordan.l.justen@intel.com>,
Ard Biesheuvel <ardb+tianocore@kernel.org>,
Laszlo Ersek <lersek@redhat.com>,
Erdem Aktas <erdemaktas@google.com>,
Eric Dong <eric.dong@intel.com>, Ray Ni <ray.ni@intel.com>,
Rahul Kumar <rahul1.kumar@intel.com>,
Michael D Kinney <michael.d.kinney@intel.com>,
Liming Gao <gaoliming@byosoft.com.cn>,
Zhiguang Liu <zhiguang.liu@intel.com>,
Michael Roth <Michael.Roth@amd.com>,
Brijesh Singh <brijesh.singh@amd.com>
Subject: [RFC PATCH v4 02/27] OvmfPkg/ResetVector: add the macro to invoke MSR protocol based VMGEXIT
Date: Mon, 28 Jun 2021 12:41:58 -0500 [thread overview]
Message-ID: <20210628174223.1302-3-brijesh.singh@amd.com> (raw)
In-Reply-To: <20210628174223.1302-1-brijesh.singh@amd.com>
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
The upcoming SEV-SNP support will need to make a few additional MSR
protocol based VMGEXIT's. Add a macro that wraps the common setup and
response validation logic in one place to keep the code readable.
While at it, define SEV_STATUS_MSR that will be used to get the SEV STATUS
MSR instead of open coding it.
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Suggested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
---
OvmfPkg/ResetVector/Ia32/AmdSev.asm | 69 +++++++++++++++++++----------
1 file changed, 45 insertions(+), 24 deletions(-)
diff --git a/OvmfPkg/ResetVector/Ia32/AmdSev.asm b/OvmfPkg/ResetVector/Ia32/AmdSev.asm
index b32dd3b5d656..c3b4e16bf681 100644
--- a/OvmfPkg/ResetVector/Ia32/AmdSev.asm
+++ b/OvmfPkg/ResetVector/Ia32/AmdSev.asm
@@ -35,6 +35,42 @@ BITS 32
%define GHCB_CPUID_REGISTER_SHIFT 30
%define CPUID_INSN_LEN 2
+%define SEV_STATUS_MSR 0xc0010130
+
+; Macro is used to issue the MSR protocol based VMGEXIT. The caller is
+; responsible to populate values in the EDX:EAX registers. After the vmmcall
+; returns, it verifies that the response code matches with the expected
+; code. If it does not match then terminate the guest. The result of request
+; is returned in the EDX:EAX.
+;
+; args 1:Request code, 2: Response code
+%macro VmgExit 2
+ ;
+ ; Add request code:
+ ; GHCB_MSR[11:0] = Request code
+ or eax, %1
+
+ mov ecx, SEV_STATUS_MSR
+ wrmsr
+
+ ; Issue VMGEXIT - NASM doesn't support the vmmcall instruction in 32-bit
+ ; mode, so work around this by temporarily switching to 64-bit mode.
+ ;
+BITS 64
+ rep vmmcall
+BITS 32
+
+ mov ecx, SEV_STATUS_MSR
+ rdmsr
+
+ ;
+ ; Verify the reponse code, if it does not match then request to terminate
+ ; GHCB_MSR[11:0] = Response code
+ mov ecx, eax
+ and ecx, 0xfff
+ cmp ecx, %2
+ jne SevEsUnexpectedRespTerminate
+%endmacro
; Check if Secure Encrypted Virtualization (SEV) features are enabled.
;
@@ -85,7 +121,7 @@ CheckSevFeatures:
; Check if SEV memory encryption is enabled
; MSR_0xC0010131 - Bit 0 (SEV enabled)
- mov ecx, 0xc0010131
+ mov ecx, SEV_STATUS_MSR
rdmsr
bt eax, 0
jnc NoSev
@@ -100,7 +136,7 @@ CheckSevFeatures:
; Check if SEV-ES is enabled
; MSR_0xC0010131 - Bit 1 (SEV-ES enabled)
- mov ecx, 0xc0010131
+ mov ecx, SEV_STATUS_MSR
rdmsr
bt eax, 1
jnc GetSevEncBit
@@ -197,10 +233,10 @@ SevEsIdtNotCpuid:
mov eax, 1
jmp SevEsIdtTerminate
-SevEsIdtNoCpuidResponse:
+SevEsUnexpectedRespTerminate:
;
; Use VMGEXIT to request termination.
- ; 2 - GHCB_CPUID_RESPONSE not received
+ ; 2 - Unexpected Response is received
;
mov eax, 2
@@ -216,7 +252,7 @@ SevEsIdtTerminate:
shl eax, 16
or eax, 0x1100
xor edx, edx
- mov ecx, 0xc0010130
+ mov ecx, SEV_STATUS_MSR
wrmsr
;
; Issue VMGEXIT - NASM doesn't support the vmmcall instruction in 32-bit
@@ -276,7 +312,7 @@ SevEsIdtVmmComm:
mov [esp + VC_CPUID_REQUEST_REGISTER], eax
; Save current GHCB MSR value
- mov ecx, 0xc0010130
+ mov ecx, SEV_STATUS_MSR
rdmsr
mov [esp + VC_GHCB_MSR_EAX], eax
mov [esp + VC_GHCB_MSR_EDX], edx
@@ -293,31 +329,16 @@ NextReg:
jge VmmDone
shl eax, GHCB_CPUID_REGISTER_SHIFT
- or eax, GHCB_CPUID_REQUEST
mov edx, [esp + VC_CPUID_FUNCTION]
- mov ecx, 0xc0010130
- wrmsr
- ;
- ; Issue VMGEXIT - NASM doesn't support the vmmcall instruction in 32-bit
- ; mode, so work around this by temporarily switching to 64-bit mode.
- ;
-BITS 64
- rep vmmcall
-BITS 32
+ VmgExit GHCB_CPUID_REQUEST, GHCB_CPUID_RESPONSE
;
- ; Read GHCB MSR
+ ; Response GHCB MSR
; GHCB_MSR[63:32] = CPUID register value
; GHCB_MSR[31:30] = CPUID register
; GHCB_MSR[11:0] = CPUID response protocol
;
- mov ecx, 0xc0010130
- rdmsr
- mov ecx, eax
- and ecx, 0xfff
- cmp ecx, GHCB_CPUID_RESPONSE
- jne SevEsIdtNoCpuidResponse
; Save returned value
shr eax, GHCB_CPUID_REGISTER_SHIFT
@@ -335,7 +356,7 @@ VmmDone:
;
mov eax, [esp + VC_GHCB_MSR_EAX]
mov edx, [esp + VC_GHCB_MSR_EDX]
- mov ecx, 0xc0010130
+ mov ecx, SEV_STATUS_MSR
wrmsr
mov eax, [esp + VC_CPUID_RESULT_EAX]
--
2.17.1
next prev parent reply other threads:[~2021-06-28 17:43 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-28 17:41 [RFC PATCH v4 00/27] Add AMD Secure Nested Paging (SEV-SNP) support Brijesh Singh
2021-06-28 17:41 ` [RFC PATCH v4 01/27] OvmfPkg/ResetVector: move SEV specific code in a separate file Brijesh Singh
2021-06-28 17:41 ` Brijesh Singh [this message]
2021-06-29 18:06 ` [RFC PATCH v4 02/27] OvmfPkg/ResetVector: add the macro to invoke MSR protocol based VMGEXIT Brijesh Singh
2021-06-28 17:41 ` [RFC PATCH v4 03/27] OvmfPkg/ResetVector: add the macro to request guest termination Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 04/27] OvmfPkg: reserve SNP secrets page Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 05/27] OvmfPkg: reserve CPUID page for SEV-SNP Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 06/27] OvmfPkg/ResetVector: introduce SEV-SNP boot block GUID Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 07/27] OvmfPkg/ResetVector: pre-validate the data pages used in SEC phase Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 08/27] OvmfPkg/ResetVector: invalidate the GHCB page Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 09/27] UefiCpuPkg: Define the SEV-SNP specific dynamic PCDs Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 10/27] OvmfPkg/MemEncryptSevLib: add MemEncryptSevSnpEnabled() Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 11/27] OvmfPkg/SecMain: register GHCB gpa for the SEV-SNP guest Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 12/27] OvmfPkg/PlatformPei: " Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 13/27] OvmfPkg/AmdSevDxe: do not use extended PCI config space Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 14/27] OvmfPkg/MemEncryptSevLib: add support to validate system RAM Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 15/27] OvmfPkg/BaseMemEncryptSevLib: skip the pre-validated " Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 16/27] OvmfPkg/MemEncryptSevLib: add support to validate > 4GB memory in PEI phase Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 17/27] OvmfPkg/SecMain: pre-validate the memory used for decompressing Fv Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 18/27] OvmfPkg/PlatformPei: validate the system RAM when SNP is active Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 19/27] OvmfPkg/PlatformPei: set the SEV-SNP enabled PCD Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 20/27] OvmfPkg/PlatformPei: set the Hypervisor Features PCD Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 21/27] MdePkg/GHCB: increase the GHCB protocol max version Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 22/27] UefiCpuPkg/MpLib: add support to register GHCB GPA when SEV-SNP is enabled Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 23/27] OvmfPkg/MemEncryptSevLib: change the page state in the RMP table Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 24/27] OvmfPkg/MemEncryptSevLib: skip page state change for Mmio address Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 25/27] UefiCpuPkg/MpInitLib: Use SEV-SNP AP Creation NAE event to launch APs Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 26/27] OvmfPkg/PlatformPei: mark cpuid and secrets memory reserved in EFI map Brijesh Singh
2021-06-28 17:42 ` [RFC PATCH v4 27/27] OvmfPkg/AmdSev: expose the SNP reserved pages through configuration table Brijesh Singh
2021-07-28 8:16 ` [RFC PATCH v4 00/27] Add AMD Secure Nested Paging (SEV-SNP) support Yao, Jiewen
2021-07-28 15:22 ` Brijesh Singh
2021-07-28 16:38 ` [edk2-devel] " Yao, Jiewen
2021-07-29 2:22 ` Yao, Jiewen
2021-08-03 15:01 ` Brijesh Singh
2021-08-04 13:16 ` Yao, Jiewen
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