From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) by mx.groups.io with SMTP id smtpd.web08.21721.1625898695823857158 for ; Fri, 09 Jul 2021 23:31:35 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=Z6WafpH4; spf=pass (domain: ventanamicro.com, ip: 209.85.214.172, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pl1-f172.google.com with SMTP id d1so967483plg.0 for ; Fri, 09 Jul 2021 23:31:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=oQ/qBpi5YVtIYNX2ZnGzBFmmrZWopEA7Ska3q8kJwRw=; b=Z6WafpH4AaZGqsI7SvYbgmyNviIwZtcdtz7TYYYuA80FplgwecvucZZ/FKATjAHuGD GFNH8OIomiax+Hda5lWGH08nMsRxz0SgdFwZPqc98vexbWWBlznyC92psvYyVfKtJuD+ /8MfTYF2LdWfbqa/PqA+F+YzuMAI+fbV7El3AHTmP5RBL+dvPULmhaovaUfau9gLfDuo ysARrBqMVFDZYxEf/pnxpVQtl751OCCcmJfgYUX7fuM6wYEn+xZXcFWZDTAZ6KGW5Rvl 09JrifcFYXnv4u4PGBoSfBbwliEFY9nuauvGq8/ZU4LgVqVLBVpnnT6Obs2u2lDbU/3l 9ZtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=oQ/qBpi5YVtIYNX2ZnGzBFmmrZWopEA7Ska3q8kJwRw=; b=M8k4Qmh9wYjsaWfGVsS4mgBMFN4Lkj+2iKBMpM6kobH2GW2p1tlks/K5aW8x9kePYA s7BKbbO18IIeJTTXO5dV7auN/La/y+a6hh9yHFzAtm3bd+DpXYTcnYsRseVFCDgVAL1L Ms7fDrPc2gRvIWJzFYOeo1xDZKFkqFDfri4FtXXkCR3u7Mu9iLWt23c1vnPaBpnlOeRE WcmkEKwr/sAFs/N6YdzNhpEr4uTJmsLeALPJ0GVSXnCrG8ttjCCdzg1C+816QRMUsV/1 Pbr27eTPCshdq78fl1kRB1PpRwWKPzWd+hXS4mO0HRkKqyalAdnYHAJfUtwkCYtR5QoS T5vQ== X-Gm-Message-State: AOAM533TIl+D4Vs2NTd9Em+1su2KLwSNUNld4XbVdV+QeMQErVBg5MBe oq3FpulaB8sXMQe0oqJZhI4LoyLulbbTCQ== X-Google-Smtp-Source: ABdhPJzUR39T0BPB77+J6r81KkTflsUS7M9UUIrT2KCUf4r4lBflma2B7nmjwM5CEsYraVXd0qeoYA== X-Received: by 2002:a17:90a:d102:: with SMTP id l2mr41924303pju.225.1625898695183; Fri, 09 Jul 2021 23:31:35 -0700 (PDT) Return-Path: Received: from sunil-ThinkPad-T490.dc1.ventanamicro.com ([49.206.3.187]) by smtp.gmail.com with ESMTPSA id 11sm8104748pfl.41.2021.07.09.23.31.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 23:31:34 -0700 (PDT) From: Sunil V L To: devel@edk2.groups.io Cc: sunil.vl@gmail.com, Sunil V L , Liming Gao , Bob Feng , Yuwei Chen , Pete Batard , Abner Chang , Daniel Schaefer Subject: [PATCH] BaseTools GenFw: Add support for R_RISCV_PCREL_LO12_S relocation Date: Sat, 10 Jul 2021 12:01:14 +0530 Message-Id: <20210710063114.4278-1-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3459 This patch adds support for R_RISCV_PCREL_LO12_S relocation type. The logic is same as existing R_RISCV_PCREL_LO12_I relocation except the difference between load vs store instruction formats. Signed-off-by: Sunil V L Cc: Liming Gao Cc: Bob Feng Cc: Yuwei Chen Cc: Pete Batard Cc: Abner Chang Cc: Daniel Schaefer --- BaseTools/Source/C/GenFw/Elf64Convert.c | 55 +++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/G= enFw/Elf64Convert.c index 3d7e20aaff..0bb3ead228 100644 --- a/BaseTools/Source/C/GenFw/Elf64Convert.c +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c @@ -557,6 +557,60 @@ WriteSectionRiscV64 ( Value =3D (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));=0D break;=0D =0D + case R_RISCV_PCREL_LO12_S:=0D + if (mRiscVPass1Targ !=3D NULL && mRiscVPass1Sym !=3D NULL && mRiscVPas= s1SymSecIndex !=3D 0) {=0D + int i;=0D + Value2 =3D (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));=0D +=0D + Value =3D ((UINT32)(RV_X(*(UINT32 *)Targ, 25, 7)) << 5);=0D + Value =3D (Value | (UINT32)(RV_X(*(UINT32 *)Targ, 7, 5)));=0D +=0D + if(Value & (RISCV_IMM_REACH/2)) {=0D + Value |=3D ~(RISCV_IMM_REACH-1);=0D + }=0D + Value =3D Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOff= set[mRiscVPass1SymSecIndex];=0D +=0D + if(-2048 > (INT32)Value) {=0D + i =3D (((INT32)Value * -1) / 4096);=0D + Value2 -=3D i;=0D + Value +=3D 4096 * i;=0D + if(-2048 > (INT32)Value) {=0D + Value2 -=3D 1;=0D + Value +=3D 4096;=0D + }=0D + }=0D + else if( 2047 < (INT32)Value) {=0D + i =3D (Value / 4096);=0D + Value2 +=3D i;=0D + Value -=3D 4096 * i;=0D + if(2047 < (INT32)Value) {=0D + Value2 +=3D 1;=0D + Value -=3D 4096;=0D + }=0D + }=0D +=0D + // Update the IMM of SD instruction=0D + //=0D + // |31 25|24 20|19 15|14 12 |11 7|6 0|=0D + // |-------------------------------------------|-------|=0D + // |imm[11:5] | rs2 | rs1 | funct3 |imm[4:0] | opcode|=0D + // ---------------------------------------------------=0D +=0D + // First Zero out current IMM=0D + *(UINT32 *)Targ &=3D ~0xfe000f80;=0D +=0D + // Update with new IMM=0D + *(UINT32 *)Targ |=3D (RV_X(Value, 5, 7) << 25);=0D + *(UINT32 *)Targ |=3D (RV_X(Value, 0, 5) << 7);=0D +=0D + // Update previous instruction=0D + *(UINT32 *)mRiscVPass1Targ =3D (RV_X(Value2, 0, 20)<<12) | (RV_X(*(U= INT32 *)mRiscVPass1Targ, 0, 12));=0D + }=0D + mRiscVPass1Sym =3D NULL;=0D + mRiscVPass1Targ =3D NULL;=0D + mRiscVPass1SymSecIndex =3D 0;=0D + break;=0D +=0D case R_RISCV_PCREL_LO12_I:=0D if (mRiscVPass1Targ !=3D NULL && mRiscVPass1Sym !=3D NULL && mRiscVPas= s1SymSecIndex !=3D 0) {=0D int i;=0D @@ -1587,6 +1641,7 @@ WriteRelocations64 ( case R_RISCV_PCREL_HI20:=0D case R_RISCV_GOT_HI20:=0D case R_RISCV_PCREL_LO12_I:=0D + case R_RISCV_PCREL_LO12_S:=0D break;=0D =0D default:=0D --=20 2.32.0