From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web09.2664.1626136920574620140 for ; Mon, 12 Jul 2021 17:42:01 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: nathaniel.l.desimone@intel.com) X-IronPort-AV: E=McAfee;i="6200,9189,10043"; a="190456218" X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="190456218" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:57 -0700 X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="653422938" Received: from nldesimo-desk1.amr.corp.intel.com ([10.212.211.135]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:49 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Isaac Oram , Mohamed Abbas , Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-platforms] [PATCH V1 06/17] WhitleySiliconPkg: Add PCH Includes Date: Mon, 12 Jul 2021 17:41:20 -0700 Message-Id: <20210713004131.1782-7-nathaniel.l.desimone@intel.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki --- .../SouthClusterLbg/Include/GpioPinsSklH.h | 300 +++ .../SouthClusterLbg/Include/Library/GpioLib.h | 1016 ++++++++ .../Include/Library/PchMultiPchBase.h | 37 + .../Include/Library/PchPcieRpLib.h | 145 ++ .../Pch/SouthClusterLbg/Include/PchAccess.h | 629 +++++ .../Pch/SouthClusterLbg/Include/PchLimits.h | 108 + .../SouthClusterLbg/Include/PchPolicyCommon.h | 2161 +++++++++++++++++ .../Include/PchReservedResources.h | 82 + .../Pch/SouthClusterLbg/Include/PcieRegs.h | 288 +++ .../Include/Ppi/PchHsioPtssTable.h | 31 + .../Include/Ppi/PchPcieDeviceTable.h | 126 + .../SouthClusterLbg/Include/Ppi/PchPolicy.h | 23 + .../SouthClusterLbg/Include/Ppi/PchReset.h | 95 + .../Pch/SouthClusterLbg/Include/Ppi/Spi.h | 28 + .../Include/Private/Library/PchSpiCommonLib.h | 458 ++++ .../Include/Protocol/PchReset.h | 114 + .../SouthClusterLbg/Include/Protocol/Spi.h | 305 +++ 17 files changed, 5946 insertions(+) create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/GpioPinsSklH.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/GpioLib.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/PchMultiPchBase.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/PchPcieRpLib.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchAccess.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchLimits.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchPolicyCommon.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchReservedResources.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PcieRegs.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchHsioPtssTable.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchPcieDeviceTable.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchPolicy.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchReset.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/Spi.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Private/Library/PchSpiCommonLib.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Protocol/PchReset.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Protocol/Spi.h diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/GpioPinsSklH.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/GpioPinsSklH.h new file mode 100644 index 0000000000..79d6e73dc4 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/GpioPinsSklH.h @@ -0,0 +1,300 @@ +/** @file + GPIO pins for SKL-PCH-H, + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_PINS_SKL_H_H_ +#define _GPIO_PINS_SKL_H_H_ +/// +/// This header file should be used together with +/// PCH GPIO lib in C and ASL. All defines used +/// must match both ASL/C syntax +/// +/// +/// SKL H GPIO Groups +/// Use below for functions from PCH GPIO Lib which +/// require GpioGroup as argument +/// +#define GPIO_SKL_H_GROUP_GPP_A 0x0100 +#define GPIO_SKL_H_GROUP_GPP_B 0x0101 +#define GPIO_SKL_H_GROUP_GPP_C 0x0102 +#define GPIO_SKL_H_GROUP_GPP_D 0x0103 +#define GPIO_SKL_H_GROUP_GPP_E 0x0104 +#define GPIO_SKL_H_GROUP_GPP_F 0x0105 +#define GPIO_SKL_H_GROUP_GPP_G 0x0106 +#define GPIO_SKL_H_GROUP_GPP_H 0x0107 +#define GPIO_SKL_H_GROUP_GPP_I 0x0108 +#define GPIO_SKL_H_GROUP_GPP_J 0x0109 +#define GPIO_SKL_H_GROUP_GPP_K 0x010A +#define GPIO_SKL_H_GROUP_GPP_L 0x010B +#define GPIO_SKL_H_GROUP_GPD 0x010C + +/// +/// SKL H GPIO pins +/// Use below for functions from PCH GPIO Lib which +/// require GpioPad as argument. Encoding used here +/// has all information required by library functions +/// +#define GPIO_SKL_H_GPP_A0 0x01000000 +#define GPIO_SKL_H_GPP_A1 0x01000001 +#define GPIO_SKL_H_GPP_A2 0x01000002 +#define GPIO_SKL_H_GPP_A3 0x01000003 +#define GPIO_SKL_H_GPP_A4 0x01000004 +#define GPIO_SKL_H_GPP_A5 0x01000005 +#define GPIO_SKL_H_GPP_A6 0x01000006 +#define GPIO_SKL_H_GPP_A7 0x01000007 +#define GPIO_SKL_H_GPP_A8 0x01000008 +#define GPIO_SKL_H_GPP_A9 0x01000009 +#define GPIO_SKL_H_GPP_A10 0x0100000A +#define GPIO_SKL_H_GPP_A11 0x0100000B +#define GPIO_SKL_H_GPP_A12 0x0100000C +#define GPIO_SKL_H_GPP_A13 0x0100000D +#define GPIO_SKL_H_GPP_A14 0x0100000E +#define GPIO_SKL_H_GPP_A15 0x0100000F +#define GPIO_SKL_H_GPP_A16 0x01000010 +#define GPIO_SKL_H_GPP_A17 0x01000011 +#define GPIO_SKL_H_GPP_A18 0x01000012 +#define GPIO_SKL_H_GPP_A19 0x01000013 +#define GPIO_SKL_H_GPP_A20 0x01000014 +#define GPIO_SKL_H_GPP_A21 0x01000015 +#define GPIO_SKL_H_GPP_A22 0x01000016 +#define GPIO_SKL_H_GPP_A23 0x01000017 +#define GPIO_SKL_H_GPP_B0 0x01010000 +#define GPIO_SKL_H_GPP_B1 0x01010001 +#define GPIO_SKL_H_GPP_B2 0x01010002 +#define GPIO_SKL_H_GPP_B3 0x01010003 +#define GPIO_SKL_H_GPP_B4 0x01010004 +#define GPIO_SKL_H_GPP_B5 0x01010005 +#define GPIO_SKL_H_GPP_B6 0x01010006 +#define GPIO_SKL_H_GPP_B7 0x01010007 +#define GPIO_SKL_H_GPP_B8 0x01010008 +#define GPIO_SKL_H_GPP_B9 0x01010009 +#define GPIO_SKL_H_GPP_B10 0x0101000A +#define GPIO_SKL_H_GPP_B11 0x0101000B +#define GPIO_SKL_H_GPP_B12 0x0101000C +#define GPIO_SKL_H_GPP_B13 0x0101000D +#define GPIO_SKL_H_GPP_B14 0x0101000E +#define GPIO_SKL_H_GPP_B15 0x0101000F +#define GPIO_SKL_H_GPP_B16 0x01010010 +#define GPIO_SKL_H_GPP_B17 0x01010011 +#define GPIO_SKL_H_GPP_B18 0x01010012 +#define GPIO_SKL_H_GPP_B19 0x01010013 +#define GPIO_SKL_H_GPP_B20 0x01010014 +#define GPIO_SKL_H_GPP_B21 0x01010015 +#define GPIO_SKL_H_GPP_B22 0x01010016 +#define GPIO_SKL_H_GPP_B23 0x01010017 +#define GPIO_SKL_H_GPP_C0 0x01020000 +#define GPIO_SKL_H_GPP_C1 0x01020001 +#define GPIO_SKL_H_GPP_C2 0x01020002 +#define GPIO_SKL_H_GPP_C3 0x01020003 +#define GPIO_SKL_H_GPP_C4 0x01020004 +#define GPIO_SKL_H_GPP_C5 0x01020005 +#define GPIO_SKL_H_GPP_C6 0x01020006 +#define GPIO_SKL_H_GPP_C7 0x01020007 +#define GPIO_SKL_H_GPP_C8 0x01020008 +#define GPIO_SKL_H_GPP_C9 0x01020009 +#define GPIO_SKL_H_GPP_C10 0x0102000A +#define GPIO_SKL_H_GPP_C11 0x0102000B +#define GPIO_SKL_H_GPP_C12 0x0102000C +#define GPIO_SKL_H_GPP_C13 0x0102000D +#define GPIO_SKL_H_GPP_C14 0x0102000E +#define GPIO_SKL_H_GPP_C15 0x0102000F +#define GPIO_SKL_H_GPP_C16 0x01020010 +#define GPIO_SKL_H_GPP_C17 0x01020011 +#define GPIO_SKL_H_GPP_C18 0x01020012 +#define GPIO_SKL_H_GPP_C19 0x01020013 +#define GPIO_SKL_H_GPP_C20 0x01020014 +#define GPIO_SKL_H_GPP_C21 0x01020015 +#define GPIO_SKL_H_GPP_C22 0x01020016 +#define GPIO_SKL_H_GPP_C23 0x01020017 +#define GPIO_SKL_H_GPP_D0 0x01030000 +#define GPIO_SKL_H_GPP_D1 0x01030001 +#define GPIO_SKL_H_GPP_D2 0x01030002 +#define GPIO_SKL_H_GPP_D3 0x01030003 +#define GPIO_SKL_H_GPP_D4 0x01030004 +#define GPIO_SKL_H_GPP_D5 0x01030005 +#define GPIO_SKL_H_GPP_D6 0x01030006 +#define GPIO_SKL_H_GPP_D7 0x01030007 +#define GPIO_SKL_H_GPP_D8 0x01030008 +#define GPIO_SKL_H_GPP_D9 0x01030009 +#define GPIO_SKL_H_GPP_D10 0x0103000A +#define GPIO_SKL_H_GPP_D11 0x0103000B +#define GPIO_SKL_H_GPP_D12 0x0103000C +#define GPIO_SKL_H_GPP_D13 0x0103000D +#define GPIO_SKL_H_GPP_D14 0x0103000E +#define GPIO_SKL_H_GPP_D15 0x0103000F +#define GPIO_SKL_H_GPP_D16 0x01030010 +#define GPIO_SKL_H_GPP_D17 0x01030011 +#define GPIO_SKL_H_GPP_D18 0x01030012 +#define GPIO_SKL_H_GPP_D19 0x01030013 +#define GPIO_SKL_H_GPP_D20 0x01030014 +#define GPIO_SKL_H_GPP_D21 0x01030015 +#define GPIO_SKL_H_GPP_D22 0x01030016 +#define GPIO_SKL_H_GPP_D23 0x01030017 +#define GPIO_SKL_H_GPP_E0 0x01040000 +#define GPIO_SKL_H_GPP_E1 0x01040001 +#define GPIO_SKL_H_GPP_E2 0x01040002 +#define GPIO_SKL_H_GPP_E3 0x01040003 +#define GPIO_SKL_H_GPP_E4 0x01040004 +#define GPIO_SKL_H_GPP_E5 0x01040005 +#define GPIO_SKL_H_GPP_E6 0x01040006 +#define GPIO_SKL_H_GPP_E7 0x01040007 +#define GPIO_SKL_H_GPP_E8 0x01040008 +#define GPIO_SKL_H_GPP_E9 0x01040009 +#define GPIO_SKL_H_GPP_E10 0x0104000A +#define GPIO_SKL_H_GPP_E11 0x0104000B +#define GPIO_SKL_H_GPP_E12 0x0104000C +#define GPIO_SKL_H_GPP_F0 0x01050000 +#define GPIO_SKL_H_GPP_F1 0x01050001 +#define GPIO_SKL_H_GPP_F2 0x01050002 +#define GPIO_SKL_H_GPP_F3 0x01050003 +#define GPIO_SKL_H_GPP_F4 0x01050004 +#define GPIO_SKL_H_GPP_F5 0x01050005 +#define GPIO_SKL_H_GPP_F6 0x01050006 +#define GPIO_SKL_H_GPP_F7 0x01050007 +#define GPIO_SKL_H_GPP_F8 0x01050008 +#define GPIO_SKL_H_GPP_F9 0x01050009 +#define GPIO_SKL_H_GPP_F10 0x0105000A +#define GPIO_SKL_H_GPP_F11 0x0105000B +#define GPIO_SKL_H_GPP_F12 0x0105000C +#define GPIO_SKL_H_GPP_F13 0x0105000D +#define GPIO_SKL_H_GPP_F14 0x0105000E +#define GPIO_SKL_H_GPP_F15 0x0105000F +#define GPIO_SKL_H_GPP_F16 0x01050010 +#define GPIO_SKL_H_GPP_F17 0x01050011 +#define GPIO_SKL_H_GPP_F18 0x01050012 +#define GPIO_SKL_H_GPP_F19 0x01050013 +#define GPIO_SKL_H_GPP_F20 0x01050014 +#define GPIO_SKL_H_GPP_F21 0x01050015 +#define GPIO_SKL_H_GPP_F22 0x01050016 +#define GPIO_SKL_H_GPP_F23 0x01050017 +#define GPIO_SKL_H_GPP_G0 0x01060000 +#define GPIO_SKL_H_GPP_G1 0x01060001 +#define GPIO_SKL_H_GPP_G2 0x01060002 +#define GPIO_SKL_H_GPP_G3 0x01060003 +#define GPIO_SKL_H_GPP_G4 0x01060004 +#define GPIO_SKL_H_GPP_G5 0x01060005 +#define GPIO_SKL_H_GPP_G6 0x01060006 +#define GPIO_SKL_H_GPP_G7 0x01060007 +#define GPIO_SKL_H_GPP_G8 0x01060008 +#define GPIO_SKL_H_GPP_G9 0x01060009 +#define GPIO_SKL_H_GPP_G10 0x0106000A +#define GPIO_SKL_H_GPP_G11 0x0106000B +#define GPIO_SKL_H_GPP_G12 0x0106000C +#define GPIO_SKL_H_GPP_G13 0x0106000D +#define GPIO_SKL_H_GPP_G14 0x0106000E +#define GPIO_SKL_H_GPP_G15 0x0106000F +#define GPIO_SKL_H_GPP_G16 0x01060010 +#define GPIO_SKL_H_GPP_G17 0x01060011 +#define GPIO_SKL_H_GPP_G18 0x01060012 +#define GPIO_SKL_H_GPP_G19 0x01060013 +#define GPIO_SKL_H_GPP_G20 0x01060014 +#define GPIO_SKL_H_GPP_G21 0x01060015 +#define GPIO_SKL_H_GPP_G22 0x01060016 +#define GPIO_SKL_H_GPP_G23 0x01060017 +#define GPIO_SKL_H_GPP_H0 0x01070000 +#define GPIO_SKL_H_GPP_H1 0x01070001 +#define GPIO_SKL_H_GPP_H2 0x01070002 +#define GPIO_SKL_H_GPP_H3 0x01070003 +#define GPIO_SKL_H_GPP_H4 0x01070004 +#define GPIO_SKL_H_GPP_H5 0x01070005 +#define GPIO_SKL_H_GPP_H6 0x01070006 +#define GPIO_SKL_H_GPP_H7 0x01070007 +#define GPIO_SKL_H_GPP_H8 0x01070008 +#define GPIO_SKL_H_GPP_H9 0x01070009 +#define GPIO_SKL_H_GPP_H10 0x0107000A +#define GPIO_SKL_H_GPP_H11 0x0107000B +#define GPIO_SKL_H_GPP_H12 0x0107000C +#define GPIO_SKL_H_GPP_H13 0x0107000D +#define GPIO_SKL_H_GPP_H14 0x0107000E +#define GPIO_SKL_H_GPP_H15 0x0107000F +#define GPIO_SKL_H_GPP_H16 0x01070010 +#define GPIO_SKL_H_GPP_H17 0x01070011 +#define GPIO_SKL_H_GPP_H18 0x01070012 +#define GPIO_SKL_H_GPP_H19 0x01070013 +#define GPIO_SKL_H_GPP_H20 0x01070014 +#define GPIO_SKL_H_GPP_H21 0x01070015 +#define GPIO_SKL_H_GPP_H22 0x01070016 +#define GPIO_SKL_H_GPP_H23 0x01070017 +#define GPIO_SKL_H_GPP_I0 0x01080000 +#define GPIO_SKL_H_GPP_I1 0x01080001 +#define GPIO_SKL_H_GPP_I2 0x01080002 +#define GPIO_SKL_H_GPP_I3 0x01080003 +#define GPIO_SKL_H_GPP_I4 0x01080004 +#define GPIO_SKL_H_GPP_I5 0x01080005 +#define GPIO_SKL_H_GPP_I6 0x01080006 +#define GPIO_SKL_H_GPP_I7 0x01080007 +#define GPIO_SKL_H_GPP_I8 0x01080008 +#define GPIO_SKL_H_GPP_I9 0x01080009 +#define GPIO_SKL_H_GPP_I10 0x0108000A +#define GPIO_SKL_H_GPP_J0 0x01090000 +#define GPIO_SKL_H_GPP_J1 0x01090001 +#define GPIO_SKL_H_GPP_J2 0x01090002 +#define GPIO_SKL_H_GPP_J3 0x01090003 +#define GPIO_SKL_H_GPP_J4 0x01090004 +#define GPIO_SKL_H_GPP_J5 0x01090005 +#define GPIO_SKL_H_GPP_J6 0x01090006 +#define GPIO_SKL_H_GPP_J7 0x01090007 +#define GPIO_SKL_H_GPP_J8 0x01090008 +#define GPIO_SKL_H_GPP_J9 0x01090009 +#define GPIO_SKL_H_GPP_J10 0x0109000A +#define GPIO_SKL_H_GPP_J11 0x0109000B +#define GPIO_SKL_H_GPP_J12 0x0109000C +#define GPIO_SKL_H_GPP_J13 0x0109000D +#define GPIO_SKL_H_GPP_J14 0x0109000E +#define GPIO_SKL_H_GPP_J15 0x0109000F +#define GPIO_SKL_H_GPP_J16 0x01090010 +#define GPIO_SKL_H_GPP_J17 0x01090011 +#define GPIO_SKL_H_GPP_J18 0x01090012 +#define GPIO_SKL_H_GPP_J19 0x01090013 +#define GPIO_SKL_H_GPP_J20 0x01090014 +#define GPIO_SKL_H_GPP_J21 0x01090015 +#define GPIO_SKL_H_GPP_J22 0x01090016 +#define GPIO_SKL_H_GPP_J23 0x01090017 +#define GPIO_SKL_H_GPP_K0 0x010A0000 +#define GPIO_SKL_H_GPP_K1 0x010A0001 +#define GPIO_SKL_H_GPP_K2 0x010A0002 +#define GPIO_SKL_H_GPP_K3 0x010A0003 +#define GPIO_SKL_H_GPP_K4 0x010A0004 +#define GPIO_SKL_H_GPP_K5 0x010A0005 +#define GPIO_SKL_H_GPP_K6 0x010A0006 +#define GPIO_SKL_H_GPP_K7 0x010A0007 +#define GPIO_SKL_H_GPP_K8 0x010A0008 +#define GPIO_SKL_H_GPP_K9 0x010A0009 +#define GPIO_SKL_H_GPP_K10 0x010A000A +#define GPIO_SKL_H_GPP_L2 0x010B0002 +#define GPIO_SKL_H_GPP_L3 0x010B0003 +#define GPIO_SKL_H_GPP_L4 0x010B0004 +#define GPIO_SKL_H_GPP_L5 0x010B0005 +#define GPIO_SKL_H_GPP_L6 0x010B0006 +#define GPIO_SKL_H_GPP_L7 0x010B0007 +#define GPIO_SKL_H_GPP_L8 0x010B0008 +#define GPIO_SKL_H_GPP_L9 0x010B0009 +#define GPIO_SKL_H_GPP_L10 0x010B000A +#define GPIO_SKL_H_GPP_L11 0x010B000B +#define GPIO_SKL_H_GPP_L12 0x010B000C +#define GPIO_SKL_H_GPP_L13 0x010B000D +#define GPIO_SKL_H_GPP_L14 0x010B000E +#define GPIO_SKL_H_GPP_L15 0x010B000F +#define GPIO_SKL_H_GPP_L16 0x010B0010 +#define GPIO_SKL_H_GPP_L17 0x010B0011 +#define GPIO_SKL_H_GPP_L18 0x010B0012 +#define GPIO_SKL_H_GPP_L19 0x010B0013 +#define GPIO_SKL_H_GPD0 0x010C0000 +#define GPIO_SKL_H_GPD1 0x010C0001 +#define GPIO_SKL_H_GPD2 0x010C0002 +#define GPIO_SKL_H_GPD3 0x010C0003 +#define GPIO_SKL_H_GPD4 0x010C0004 +#define GPIO_SKL_H_GPD5 0x010C0005 +#define GPIO_SKL_H_GPD6 0x010C0006 +#define GPIO_SKL_H_GPD7 0x010C0007 +#define GPIO_SKL_H_GPD8 0x010C0008 +#define GPIO_SKL_H_GPD9 0x010C0009 +#define GPIO_SKL_H_GPD10 0x010C000A +#define GPIO_SKL_H_GPD11 0x010C000B + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/GpioLib.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/GpioLib.h new file mode 100644 index 0000000000..17b433ac78 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/GpioLib.h @@ -0,0 +1,1016 @@ +/** @file + Header file for GpioLib. + All function in this library is available for PEI, DXE, and SMM + + @copyright + Copyright 2013 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_LIB_H_ +#define _GPIO_LIB_H_ + +#include +#include + +typedef struct { + GPIO_PAD GpioPad; + GPIO_CONFIG GpioConfig; +} GPIO_INIT_CONFIG; +/** + This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure. + Structure contains fields that can be used to configure each pad. + Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values. + Separate fields could be set to hardware default if it does not matter, except + GpioPad and PadMode. + Some GpioPads are configured and switched to native mode by RC, those include: + SerialIo pins, ISH pins, ClkReq Pins + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] NumberofItem Number of GPIO pads to be updated + @param[in] GpioInitTableAddress GPIO initialization table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioConfigurePadsByPchId ( + IN UINT8 PchId, + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress + ); + +/** + This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure. + Structure contains fields that can be used to configure each pad. + Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values. + Separate fields could be set to hardware default if it does not matter, except + GpioPad and PadMode. + Some GpioPads are configured and switched to native mode by RC, those include: + SerialIo pins, ISH pins, ClkReq Pins + + @param[in] NumberofItem Number of GPIO pads to be updated + @param[in] GpioInitTableAddress GPIO initialization table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioConfigurePads ( + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress + ); + +// +// Functions for setting/getting multiple GpioPad settings +// + +/** + This procedure will read multiple GPIO settings + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO Pad + @param[out] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadConfigByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT GPIO_CONFIG *GpioData + ); + +/** + This procedure will read multiple GPIO settings + + @param[in] GpioPad GPIO Pad + @param[out] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadConfig ( + IN GPIO_PAD GpioPad, + OUT GPIO_CONFIG *GpioData + ); + +/** + This procedure will configure multiple GPIO settings + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO Pad + @param[in] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadConfigByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + IN GPIO_CONFIG *GpioData + ); + +/** + This procedure will configure multiple GPIO settings + + @param[in] GpioPad GPIO Pad + @param[in] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_CONFIG *GpioData + ); + +// +// Functions for setting/getting single GpioPad properties +// + +/** + This procedure will set GPIO output level + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[in] Value Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetOutputValueByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +/** + This procedure will set GPIO output level + + @param[in] GpioPad GPIO pad + @param[in] Value Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetOutputValue ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +/** + This procedure will get GPIO output level + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] OutputVal GPIO Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetOutputValueByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINT32 *OutputVal + ); + +/** + This procedure will get GPIO output level + + @param[in] GpioPad GPIO pad + @param[out] OutputVal GPIO Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetOutputValue ( + IN GPIO_PAD GpioPad, + OUT UINT32 *OutputVal + ); + +/** + This procedure will get GPIO input level + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] InputVal GPIO Input value + 0: InputLow, 1: InputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetInputValueByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINT32 *InputVal + ); + +/** + This procedure will get GPIO input level + + @param[in] GpioPad GPIO pad + @param[out] InputVal GPIO Input value + 0: InputLow, 1: InputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetInputValue ( + IN GPIO_PAD GpioPad, + OUT UINT32 *InputVal + ); + + /** + This procedure will get GPIO IOxAPIC interrupt number + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] IrqNum IRQ number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadIoApicIrqNumber ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINT32 *IrqNum + ); + +/** + This procedure will configure GPIO input inversion + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[in] Value Value for GPIO input inversion + 0: No input inversion, 1: Invert input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetInputInversionByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +/** + This procedure will configure GPIO input inversion + + @param[in] GpioPad GPIO pad + @param[in] Value Value for GPIO input inversion + 0: No input inversion, 1: Invert input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetInputInversion ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +/** + This procedure will get GPIO pad input inversion value + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] InvertState GPIO inversion state + 0: No input inversion, 1: Inverted input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetInputInversionByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINT32 *InvertState + ); + +/** + This procedure will get GPIO pad input inversion value + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] InvertState GPIO inversion state + 0: No input inversion, 1: Inverted input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetInputInversion ( + IN GPIO_PAD GpioPad, + OUT UINT32 *InvertState + ); + +/** + This procedure will set GPIO interrupt settings + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[in] Value Value of Level/Edge + use GPIO_INT_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadInterruptConfig ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + IN GPIO_INT_CONFIG Value + ); + +/** + This procedure will set GPIO electrical settings + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[in] Value Value of termination + use GPIO_ELECTRICAL_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadElectricalConfig ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + IN GPIO_ELECTRICAL_CONFIG Value + ); + +/** + This procedure will set GPIO Reset settings + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[in] Value Value for Pad Reset Configuration + use GPIO_RESET_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadResetConfig ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + IN GPIO_RESET_CONFIG Value + ); + +/** + This procedure will get GPIO Reset settings + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[in] Value Value of Pad Reset Configuration + based on GPIO_RESET_CONFIG + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadResetConfig ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + IN GPIO_RESET_CONFIG *Value + ); + +/** + This procedure will get GPIO Host Software Pad Ownership for certain group + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] Group GPIO group + @param[in] DwNum Host Ownership register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[out] HostSwRegVal Value of Host Software Pad Ownership register + Bit position - PadNumber + Bit value - 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetHostSwOwnershipForGroupDw ( + IN UINT8 PchId, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *HostSwRegVal + ); + +/** + This procedure will get GPIO Host Software Pad Ownership for certain group + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] Group GPIO group + @param[in] DwNum Host Ownership register number for current group + For group which has less then 32 pads per group DwNum must be 0. + @param[in] HostSwRegVal Value of Host Software Pad Ownership register + Bit position - PadNumber + Bit value - 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioSetHostSwOwnershipForGroupDw ( + IN UINT8 PchId, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 HostSwRegVal + ); + +/** + This procedure will get Gpio Pad Host Software Ownership + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] PadHostSwOwn Value of Host Software Pad Owner + 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetHostSwOwnershipForPad ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINT32 *PadHostSwOwn + ); + +/** + This procedure will set Gpio Pad Host Software Ownership + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[in] PadHostSwOwn Pad Host Software Owner + 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetHostSwOwnershipForPad ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + IN UINT32 PadHostSwOwn + ); + +// +// Possible values of Pad Ownership +// +typedef enum { + GpioPadOwnHost = 0x0, + GpioPadOwnCsme = 0x1, + GpioPadOwnIsh = 0x2, +} GPIO_PAD_OWN; + +/** + This procedure will get Gpio Pad Ownership + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] PadOwnVal Value of Pad Ownership + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadOwnership ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT GPIO_PAD_OWN *PadOwnVal + ); + +/** + This procedure will check state of Pad Config Lock for pads within one group + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[out] PadCfgLockRegVal Value of PadCfgLock register + Bit position - PadNumber + Bit value - 0: NotLocked, 1: Locked + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetPadCfgLockForGroupDw ( + IN UINT8 PchId, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *PadCfgLockRegVal + ); + +/** + This procedure will check state of Pad Config Lock for selected pad + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] PadCfgLock PadCfgLock for selected pad + 0: NotLocked, 1: Locked + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadCfgLock ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINT32 *PadCfgLock + ); + +/** + This procedure will check state of Pad Config Tx Lock for pads within one group + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] Group GPIO group + @param[in] DwNum PadCfgLockTx register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register + Bit position - PadNumber + Bit value - 0: NotLockedTx, 1: LockedTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetPadCfgLockTxForGroupDw ( + IN UINT8 PchId, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *PadCfgLockTxRegVal + ); + +/** + This procedure will check state of Pad Config Tx Lock for selected pad + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] PadCfgLock PadCfgLockTx for selected pad + 0: NotLockedTx, 1: LockedTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadCfgLockTx ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINT32 *PadCfgLockTx + ); + +/** + This procedure will clear PadCfgLock for selected pads within one group. + This function should be used only inside SMI. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[in] PadsToUnlock Bitmask for pads which are going to be unlocked, + Bit position - PadNumber + Bit value - 0: DoNotUnlock, 1: Unlock + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgForGroupDw ( + IN UINT8 PchId, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToUnlock + ); + +/** + This procedure will clear PadCfgLock for selected pad. + This function should be used only inside SMI. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad + ); + +/** + This procedure will clear PadCfgLock for selected pad. + This function should be used only inside SMI. + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfg ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will set PadCfgLock for selected pads within one group + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[in] PadsToLock Bitmask for pads which are going to be locked, + Bit position - PadNumber + Bit value - 0: DoNotLock, 1: Lock + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioLockPadCfgForGroupDw ( + IN UINT8 PchId, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToLock + ); + +/** + This procedure will set PadCfgLock for selected pad + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioLockPadCfg ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad + ); + +/** + This procedure will clear PadCfgLockTx for selected pads within one group. + This function should be used only inside SMI. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] Group GPIO group + @param[in] DwNum PadCfgLockTx register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[in] PadsToUnlockTx Bitmask for pads which are going to be unlocked, + Bit position - PadNumber + Bit value - 0: DoNotUnLockTx, 1: LockTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgTxForGroupDw ( + IN UINT8 PchId, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToUnlockTx + ); + +/** + This procedure will clear PadCfgLockTx for selected pad. + This function should be used only inside SMI. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgTx ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad + ); + +/** + This procedure will set PadCfgLockTx for selected pads within one group + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[in] PadsToLockTx Bitmask for pads which are going to be locked, + Bit position - PadNumber + Bit value - 0: DoNotLockTx, 1: LockTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioLockPadCfgTxForGroupDw ( + IN UINT8 PchId, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToLockTx + ); + +/** + This procedure will set PadCfgLockTx for selected pad + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioLockPadCfgTx ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad + ); + +/** + This procedure will get Group to GPE mapping. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[out] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 + @param[out] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 + @param[out] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGroupToGpeDwX ( + IN UINT8 PchId, + IN GPIO_GROUP *GroupToGpeDw0, + IN GPIO_GROUP *GroupToGpeDw1, + IN GPIO_GROUP *GroupToGpeDw2 + ); + +/** + This procedure will set Group to GPE mapping. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 + @param[in] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 + @param[in] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGroupToGpeDwX ( + IN UINT8 PchId, + IN GPIO_GROUP GroupToGpeDw0, + IN GPIO_GROUP GroupToGpeDw1, + IN GPIO_GROUP GroupToGpeDw2 + ); + +/** + This procedure will get GPE number for provided GpioPad. + PCH allows to configure mapping between GPIO groups and related GPE (GpioSetGroupToGpeDwX()) + what results in the fact that certain Pad can cause different General Purpose Event. Only three + GPIO groups can be mapped to cause unique GPE (1-tier), all others groups will be under one common + event (GPE_111 for 2-tier). + + 1-tier: + Returned GpeNumber is in range <0,95>. GpioGetGpeNumber() can be used + to determine what _LXX ACPI method would be called on event on selected GPIO pad + + 2-tier: + Returned GpeNumber is 0x6F (111). All GPIO pads which are not mapped to 1-tier GPE + will be under one master GPE_111 which is linked to _L6F ACPI method. If it is needed to determine + what Pad from 2-tier has caused the event, _L6F method should check GPI_GPE_STS and GPI_GPE_EN + registers for all GPIO groups not mapped to 1-tier GPE. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] GpeNumber GPE number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGpeNumber ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINT32 *GpeNumber + ); + +/** + This procedure is used to clear SMI STS for a specified Pad + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearGpiSmiStsByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad + ); + +/** + This procedure is used to clear SMI STS for a specified Pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearGpiSmiSts ( + IN GPIO_PAD GpioPad + ); + +// +// Extended interface for Server RAS usage +// +/** + This procedure is used to get SMI STS for a specified Pad + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] SmiStsReg Smi status register for given pad + The bit position is set for given Pad number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetGpiSmiStsByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT BOOLEAN *SmiSts + ); + +/** + This procedure is used to get SMI STS for a specified Pad + + @param[in] GpioPad GPIO pad + @param[out] SmiStsReg Smi status register for given pad + The bit position is set for given Pad number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetGpiSmiSts ( + IN GPIO_PAD GpioPad, + OUT BOOLEAN *SmiSts + ); + +/** + This procedure is used by Smi Dispatcher and will clear + all GPI SMI Status bits + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearAllGpiSmiSts ( + IN UINT8 PchId + ); + +/** + This procedure is used to disable all GPI SMI + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioDisableAllGpiSmi ( + IN UINT8 PchId + ); + +/** + This procedure is used to register GPI SMI dispatch function. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] GpiNum GPI number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGpiSmiNumByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINTN *GpiNum + ); + +/** + This procedure is used to register GPI SMI dispatch function. + + @param[in] GpioPad GPIO pad + @param[out] GpiNum GPI number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGpiSmiNum ( + IN GPIO_PAD GpioPad, + OUT UINTN *GpiNum + ); + +/** + This procedure is used to check GPIO inputs belongs to 2 tier or 1 tier architecture + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + + @retval Data 0 means 1-tier, 1 means 2-tier +**/ +BOOLEAN +GpioCheckFor2Tier ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad + ); + +/** + This procedure is used to clear GPE STS for a specified GpioPad + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearGpiGpeSts ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad + ); + +/** + This procedure is used to read GPE STS for a specified Pad + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] Data GPE STS data + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGpiGpeSts ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINT32* Data + ); + + +/** + Locks GPIO pads according to GPIO_INIT_CONFIG array from + gPlatformGpioConfigGuid HOB. Only locking is applied and no other GPIO pad + configuration is changed. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_NOT_FOUND gPlatformGpioConfigGuid not found +**/ +EFI_STATUS +GpioLockGpios ( + IN UINT8 PchId + ); + +/** + Unlocks all PCH GPIO pads + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + + @retval None +**/ +VOID +GpioUnlockAllGpios ( + IN UINT8 PchId + ); + +#endif // _GPIO_LIB_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/PchMultiPchBase.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/PchMultiPchBase.h new file mode 100644 index 0000000000..546d7e3212 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/PchMultiPchBase.h @@ -0,0 +1,37 @@ +/** @file + Prototype of the MultiPch library - Base definitions. + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_MULTI_PCH_BASE_H_ +#define _PCH_MULTI_PCH_BASE_H_ + + +#define PCH_LEGACY_ID 0 +#define PCH_MAX 4 + +/** + Function returns PchId for devices of passed Segment and Bus. + PchId is an index in PCH_IP_INFO table + + @param [in] Segment Segment to look for + @param [in] Bus Bas to look for + @param [in, out] PchId pointer to variable to return PchId + + @retval EFI_SUCCESS Function returned valid PchId + @retval EFI_INVALID_PARAMETER Passed pointer is invalid + @retval EFI_DEVICE_ERROR Not found valid PchInfo + @retval EFI_NOT_FOUND For given input parameters not found valid PchId +**/ +EFI_STATUS +FindMultiPchInfo ( + IN UINTN HeciSegment, + IN UINTN HeciBus, + IN OUT UINTN *PchId + ); + +#endif // _PCH_MULTI_PCH_BASE_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/PchPcieRpLib.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/PchPcieRpLib.h new file mode 100644 index 0000000000..26b2f8fbaf --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/PchPcieRpLib.h @@ -0,0 +1,145 @@ +/** @file + Header file for PchPcieRpLib. + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PCIERP_LIB_H_ +#define _PCH_PCIERP_LIB_H_ + +/** + PCIe controller bifurcation configuration. +**/ +typedef enum { + PcieBifurcation4x1 = 0, + PcieBifurcation1x2_2x1 = 1, + PcieBifurcation2x2 = 2, + PcieBifurcation1x4 = 3, + PcieUnknownConfig +} PCIE_BIFURCATION_CONFIG; + +typedef struct { + UINT8 DevNum; + UINT8 Pid; + UINT8 RpNumBase; +} PCH_PCIE_CONTROLLER_INFO; + +/** + Get Pch Pcie Root Port Device and Function Number by Root Port physical Number + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] RpNumber Root port physical number. (0-based) + @param[out] RpDev Return corresponding root port device number. + @param[out] RpFun Return corresponding root port function number. + + @retval EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +GetPchPcieRpDevFunByPchId ( + IN UINT8 PchId, + IN UINTN RpNumber, + OUT UINTN *RpDev, + OUT UINTN *RpFun + ); + +/** + Get Pch Pcie Root Port Device and Function Number by Root Port physical Number + + @param[in] RpNumber Root port physical number. (0-based) + @param[out] RpDev Return corresponding root port device number. + @param[out] RpFun Return corresponding root port function number. + + @retval EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +GetPchPcieRpDevFun ( + IN UINTN RpNumber, + OUT UINTN *RpDev, + OUT UINTN *RpFun + ); + +/** + Get Root Port physical Number by Pch Pcie Root Port Device and Function Number + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] RpDev Root port device number. + @param[in] RpFun Root port function number. + @param[out] RpNumber Return corresponding physical Root Port index (0-based) + + @retval EFI_SUCCESS Physical root port is retrieved + @retval EFI_INVALID_PARAMETER RpDev and/or RpFun are invalid + @retval EFI_UNSUPPORTED Root port device and function is not assigned to any physical root port +**/ +EFI_STATUS +EFIAPI +GetPchPcieRpNumber ( + IN UINT8 PchId, + IN UINTN RpDev, + IN UINTN RpFun, + OUT UINTN *RpNumber + ); + +/** + Gets base address of PCIe root port. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param RpIndex Root Port Index (0 based) + @return PCIe port base address. +**/ +UINTN +PchPcieBase ( + IN UINT8 PchId, + IN UINT32 RpIndex + ); + +/** + Determines whether L0s is supported on current stepping. + + @return TRUE if L0s is supported, FALSE otherwise +**/ +BOOLEAN +PchIsPcieL0sSupported ( + VOID + ); + +/** + Some early SKL PCH steppings require Native ASPM to be disabled due to hardware issues: + - RxL0s exit causes recovery + - Disabling PCIe L0s capability disables L1 + Use this function to determine affected steppings. + + @return TRUE if Native ASPM is supported, FALSE otherwise +**/ +BOOLEAN +PchIsPcieNativeAspmSupported ( + VOID + ); + +/** + Returns the maximum value of the "Payload" parameter of all available PchPcie Ports. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @retval INT16 The value to assign in field max payload size field +**/ +UINT16 +PchPcieGetMaxPayloadSizeForAllPortsByPchId ( + IN UINT8 PchId + ); + +/** + Returns the maximum value of the "Payload" parameter of all available PchPcie Ports. + + @param VOID + @retval INT16 The value to assign in field max payload size field +**/ +UINT16 +PchPcieGetMaxPayloadSizeForAllPorts ( + VOID + ); + +#endif // _PCH_PCIERP_LIB_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchAccess.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchAccess.h new file mode 100644 index 0000000000..ec020651fb --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchAccess.h @@ -0,0 +1,629 @@ +/** @file + Macros that simplify accessing PCH devices's PCI registers. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_ACCESS_H_ +#define _PCH_ACCESS_H_ + +#include "PchLimits.h" +#include "PchReservedResources.h" + +#ifndef STALL_ONE_MICRO_SECOND +#define STALL_ONE_MICRO_SECOND 1 +#endif +#ifndef STALL_ONE_SECOND +#define STALL_ONE_SECOND 1000000 +#endif + +/// +/// The default PCH PCI bus number +/// +#define DEFAULT_PCI_BUS_NUMBER_PCH 0 + + +// +// SKX defines to get to sspad7 +// +#define UBOX_SCRATCH_DEVICE 0x8 +#define UBOX_SCRATCH_FUNC2 0x2 +#define UBOX_BIOS_SCRATCHPAD7 0xBC + +/// +/// The default PCH PCI segment and bus number +/// +#define DEFAULT_PCI_SEGMENT_NUMBER_PCH 0 +#define DEFAULT_PCI_BUS_NUMBER_PCH 0 + +// +// Default Vendor ID and Subsystem ID +// +#define V_PCH_INTEL_VENDOR_ID 0x8086 ///< Default Intel PCH Vendor ID +#define V_PCH_DEFAULT_SID 0x7270 ///< Default Intel PCH Subsystem ID +#define V_PCH_DEFAULT_SVID_SID (V_INTEL_VENDOR_ID + (V_PCH_DEFAULT_SID << 16)) ///< Default INTEL PCH Vendor ID and Subsystem ID + +// +// Generic definitions for device enabling/disabling used by PCH code. +// +#define PCH_DEVICE_ENABLE 1 +#define PCH_DEVICE_DISABLE 0 +#define PCH_DEVICE_DEFAULT 2 + +// +// Include device register definitions +// +#include "PcieRegs.h" +#include "Register/PchRegsPcr.h" +#include "Register/PchRegsP2sb.h" +#include "Register/PchRegsHda.h" +#include "Register/PchRegsHsio.h" +#include "Register/PchRegsLan.h" +#include "Register/PchRegsLpc.h" +#include "Register/PchRegsPmc.h" +#include "Register/PchRegsPcie.h" +#include "Register/PchRegsSata.h" +#include "Register/PchRegsSmbus.h" +#include "Register/PchRegsSpi.h" +#include "Register/PchRegsThermal.h" +#include "Register/PchRegsUsb.h" +#include "Register/PchRegsGpio.h" +#include "Register/PchRegsTraceHub.h" +#include "Register/PchRegsDmi.h" +#include "Register/PchRegsItss.h" +#include "Register/PchRegsPsth.h" +#include "Register/PchRegsPsf.h" +#include "Register/PchRegsFia.h" +#include "Register/PchRegsDci.h" +#include "Register/PchRegsEva.h" + +// +// LPC Device ID macros +// +// +// Device IDs that are PCH-H Desktop specific +// +#define IS_PCH_H_LPC_DEVICE_ID_DESKTOP(DeviceId) \ + ( \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_DT_0) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_DT_1) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_DT_2) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_DT_3) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_DT_4) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_DT_5) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_DT_6) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_UNFUSE) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_DT_SUPER_SKU) \ + ) + +#define IS_PCH_LPC_DEVICE_ID_DESKTOP(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID_DESKTOP(DeviceId) \ + ) + +// +// Device IDs that are PCH-H Mobile specific +// + +#define IS_PCH_H_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ( \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_MB_0) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_MB_1) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_MB_2) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_MB_SUPER_SKU) \ + ) + + +// +// Device IDs that are PCH-LP Mobile specific +// +#define IS_PCH_LP_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ( \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_UNFUSE) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_SUPER_SKU) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_0) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_1) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_2) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_3) \ + ) + +#define IS_PCH_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID_MOBILE(DeviceId) || \ + IS_PCH_LP_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ) + +// +// Device IDS that are PCH Server\Workstation specific +#define IS_PCH_H_LPC_DEVICE_ID_SERVER(DeviceId) \ + ( \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_SVR_0) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_SVR_1) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_SVR_2) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_A14B) \ + ) + + +#define IS_PCH_LPC_DEVICE_ID_SERVER(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID_SERVER(DeviceId) \ + ) + +#define IS_PCH_H_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID_DESKTOP (DeviceId) || \ + IS_PCH_H_LPC_DEVICE_ID_MOBILE (DeviceId) || \ + IS_PCH_H_LPC_DEVICE_ID_SERVER (DeviceId) \ + ) + +#define IS_PCH_LP_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LP_LPC_DEVICE_ID_MOBILE (DeviceId) \ + ) + +#define IS_PCH_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_LPC_DEVICE_ID(DeviceId) \ + ) + +#define IS_PCH_LBG_PROD_LPC_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId >= V_PCH_LBG_PROD_LPC_DEVICE_ID_0) && \ + (DeviceId <= V_PCH_LBG_PROD_LPC_DEVICE_ID_RESERVED_MAX) \ + ) + +#define IS_PCH_LBG_SSKU_LPC_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId >= V_PCH_LBG_LPC_DEVICE_ID_UNFUSED) && \ + (DeviceId <= V_PCH_LBG_LPC_DEVICE_ID_RESERVED_SS_MAX ) \ + ) + +#define IS_PCH_LBG_NS_LPC_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_LPC_DEVICE_ID_SS_T80_NS) || \ + (DeviceId == V_PCH_LBG_PROD_LPC_DEVICE_ID_T) || \ + (DeviceId == V_PCH_LBG_PROD_LPC_DEVICE_ID_C) \ + ) + +#define IS_PCH_LBG_WS_LPC_DEVICE_ID(DeviceId) \ + ( \ + FALSE \ + ) + +#define IS_PCH_LBG_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_PROD_LPC_DEVICE_ID(DeviceId) || \ + IS_PCH_LBG_NS_LPC_DEVICE_ID(DeviceId) || \ + IS_PCH_LBG_WS_LPC_DEVICE_ID(DeviceId) || \ + IS_PCH_LBG_SSKU_LPC_DEVICE_ID(DeviceId) \ + ) + + +// +// SATA AHCI Device ID macros +// +#define IS_PCH_LBG_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_PROD_SATA_DEVICE_ID_D_AHCI) || \ + (DeviceId == V_PCH_LBG_SATA_DEVICE_ID_D_AHCI) \ + ) + +#define IS_PCH_LBG_SSATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_AHCI) || \ + (DeviceId == V_PCH_LBG_SSATA_DEVICE_ID_D_AHCI) \ + ) + + +#define IS_PCH_H_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_H_SATA_DEVICE_ID_D_AHCI_A0) || \ + (DeviceId == V_PCH_H_SATA_DEVICE_ID_D_AHCI) \ + ) + +#define IS_PCH_LP_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LP_SATA_DEVICE_ID_M_AHCI) \ + ) + +#define IS_PCH_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SSATA_AHCI_DEVICE_ID (DeviceId) \ + ) + + + +// +// SATA RAID Device ID macros +// +#define IS_PCH_LBG_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_SATA_DEVICE_ID_D_RAID) || \ + (DeviceId == V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM) || \ + (DeviceId == V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM_DSEL0) || \ + (DeviceId == V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM_DSEL1) || \ + (DeviceId == V_PCH_LBG_SATA_DEVICE_ID_D_RAID1) || \ + (DeviceId == V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID) || \ + (DeviceId == V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID_PREMIUM) || \ + (DeviceId == V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID1) \ + ) + +#define IS_PCH_LBG_SSATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_SSATA_DEVICE_ID_D_RAID) || \ + (DeviceId == V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM) || \ + (DeviceId == V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM_DSEL0) || \ + (DeviceId == V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM_DSEL1) || \ + (DeviceId == V_PCH_LBG_SSATA_DEVICE_ID_D_RAID1) || \ + (DeviceId == V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID) || \ + (DeviceId == V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID_PREMIUM) || \ + (DeviceId == V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID1) \ + ) + + +#define IS_PCH_H_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_H_SATA_DEVICE_ID_D_RAID) || \ + (DeviceId == V_PCH_H_SATA_DEVICE_ID_D_RAID_PREM) || \ + (DeviceId == V_PCH_H_SATA_DEVICE_ID_D_RAID_ALTDIS) || \ + (DeviceId == V_PCH_H_SATA_DEVICE_ID_D_RAID_RSTE) || \ + (DeviceId == V_PCH_H_SATA_DEVICE_ID_D_RAID_RRT) \ + ) + + +#define IS_PCH_LP_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LP_SATA_DEVICE_ID_M_RAID) || \ + (DeviceId == V_PCH_LP_SATA_DEVICE_ID_M_RAID_ALTDIS) || \ + (DeviceId == V_PCH_LP_SATA_DEVICE_ID_M_RAID_PREM) || \ + (DeviceId == V_PCH_LP_SATA_DEVICE_ID_M_RAID_RRT) \ + ) + +#define IS_PCH_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SATA_RAID_DEVICE_ID(DeviceId) || \ + IS_PCH_LBG_SSATA_RAID_DEVICE_ID(DeviceId) \ + ) + +// +// Combined SATA IDE/AHCI/RAID Device ID macros +// +#define IS_PCH_LBG_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SATA_RAID_DEVICE_ID (DeviceId) \ + ) +#define IS_PCH_LBG_SSATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SSATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SSATA_RAID_DEVICE_ID (DeviceId) \ + ) +#define IS_PCH_LBG_RAID_AVAILABLE(DeviceId) (TRUE) + +#define IS_PCH_H_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_SATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_H_SATA_RAID_DEVICE_ID (DeviceId) \ + ) + +#define IS_PCH_LP_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LP_SATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_LP_SATA_RAID_DEVICE_ID (DeviceId) \ + ) + +#define IS_PCH_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SATA_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SSATA_DEVICE_ID (DeviceId) \ + ) + +#define IS_PCH_H_RAID_AVAILABLE(DeviceId) (TRUE) +#define IS_PCH_LP_RAID_AVAILABLE(DeviceId) (TRUE) + +#define IS_PCH_RAID_AVAILABLE(DeviceId) \ + ( \ + IS_PCH_LBG_RAID_AVAILABLE(DeviceId) \ + ) + +// +// SPI Device ID macros +// +#define IS_PCH_LBG_SPI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_SPI_DEVICE_ID) || \ + (DeviceId == V_PCH_LBG_PROD_SPI_DEVICE_ID) \ + ) + +#define IS_PCH_H_SPI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_H_SPI_DEVICE_ID) || \ + FALSE \ + ) + +#define IS_PCH_LP_SPI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LP_SPI_DEVICE_ID) || \ + FALSE \ + ) + +#define IS_PCH_SPI_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SPI_DEVICE_ID(DeviceId) \ + ) + +// +// USB Device ID macros +// +#define IS_PCH_LBG_USB_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_USB_DEVICE_ID_XHCI_1) || \ + (DeviceId == V_PCH_LBG_PROD_USB_DEVICE_ID_XHCI_1) \ + ) + +#define IS_PCH_H_USB_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_H_USB_DEVICE_ID_XHCI_1) \ + ) + +#define IS_PCH_LP_USB_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LP_USB_DEVICE_ID_XHCI_1) \ + ) +#define IS_PCH_USB_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_USB_DEVICE_ID(DeviceId) \ + ) + +// +// PCIE Device ID macros +// +#define IS_PCH_LBG_PCIE_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT1) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT2) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT3) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT4) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT5) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT6) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT7) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT8) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT9) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT10) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT11) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT12) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT13) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT14) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT15) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT16) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT17) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT18) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT19) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT20) \ + ) + +#define IS_PCH_LBG_PROD_PCIE_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT1) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT2) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT3) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT4) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT5) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT6) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT7) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT8) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT9) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT10) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT11) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT12) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT13) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT14) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT15) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT16) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT17) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT18) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT19) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT20) \ + ) + + + +#define IS_PCH_H_PCIE_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT1) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT2) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT3) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT4) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT5) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT6) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT7) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT8) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT9) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT10) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT11) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT12) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT13) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT14) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT15) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT16) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT17) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT18) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT19) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT20) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_MB_SUBD) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_DT_SUBD) \ + ) + +#define IS_PCH_LP_PCIE_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT1) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT2) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT3) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT4) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT5) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT6) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT7) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT8) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT9) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT10) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT11) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT12) \ + ) + +#define IS_PCH_PCIE_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_PCIE_DEVICE_ID(DeviceId) || \ + IS_PCH_LBG_PROD_PCIE_DEVICE_ID(DeviceId) \ + ) + + +// +// HD Audio Device ID macros +// +#define IS_PCH_LBG_HDA_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_HDA_DEVICE_ID_0) || \ + (DeviceId == V_PCH_LBG_HDA_DEVICE_ID_1) || \ + (DeviceId == V_PCH_LBG_HDA_DEVICE_ID_2) || \ + (DeviceId == V_PCH_LBG_HDA_DEVICE_ID_3) || \ + (DeviceId == V_PCH_LBG_HDA_DEVICE_ID_4) || \ + (DeviceId == V_PCH_LBG_HDA_DEVICE_ID_5) || \ + (DeviceId == V_PCH_LBG_HDA_DEVICE_ID_6) || \ + (DeviceId == V_PCH_LBG_HDA_DEVICE_ID_7) || \ + (DeviceId == V_PCH_LBG_PROD_HDA_DEVICE_ID_0) || \ + (DeviceId == V_PCH_LBG_PROD_HDA_DEVICE_ID_1) || \ + (DeviceId == V_PCH_LBG_PROD_HDA_DEVICE_ID_2) || \ + (DeviceId == V_PCH_LBG_PROD_HDA_DEVICE_ID_3) || \ + (DeviceId == V_PCH_LBG_PROD_HDA_DEVICE_ID_4) || \ + (DeviceId == V_PCH_LBG_PROD_HDA_DEVICE_ID_5) || \ + (DeviceId == V_PCH_LBG_PROD_HDA_DEVICE_ID_6) || \ + (DeviceId == V_PCH_LBG_PROD_HDA_DEVICE_ID_7) \ + ) + +#define IS_PCH_H_HDA_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_H_HDA_DEVICE_ID_0) || \ + (DeviceId == V_PCH_H_HDA_DEVICE_ID_1) || \ + (DeviceId == V_PCH_H_HDA_DEVICE_ID_2) || \ + (DeviceId == V_PCH_H_HDA_DEVICE_ID_3) || \ + (DeviceId == V_PCH_H_HDA_DEVICE_ID_4) || \ + (DeviceId == V_PCH_H_HDA_DEVICE_ID_5) || \ + (DeviceId == V_PCH_H_HDA_DEVICE_ID_6) || \ + (DeviceId == V_PCH_H_HDA_DEVICE_ID_7) \ + ) + +#define IS_PCH_LP_HDA_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LP_HDA_DEVICE_ID_0) || \ + (DeviceId == V_PCH_LP_HDA_DEVICE_ID_1) || \ + (DeviceId == V_PCH_LP_HDA_DEVICE_ID_2) || \ + (DeviceId == V_PCH_LP_HDA_DEVICE_ID_3) || \ + (DeviceId == V_PCH_LP_HDA_DEVICE_ID_4) || \ + (DeviceId == V_PCH_LP_HDA_DEVICE_ID_5) || \ + (DeviceId == V_PCH_LP_HDA_DEVICE_ID_6) || \ + (DeviceId == V_PCH_LP_HDA_DEVICE_ID_7) \ + ) +#define IS_PCH_HDA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_HDA_DEVICE_ID(DeviceId) \ + ) + + +/// +/// Any device ID that is PCH-LBG +/// +#define IS_PCH_LBG_SMBUS_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_SMBUS_DEVICE_ID) || \ + (DeviceId == V_PCH_LBG_PROD_SMBUS_DEVICE_ID) \ + ) + +#define IS_PCH_LBG_DEVICE_ID(DeviceId) \ + (\ + IS_PCH_LBG_LPC_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SATA_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_USB_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_PCIE_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_PROD_PCIE_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SMBUS_DEVICE_ID (DeviceId) || \ + (DeviceId == V_PCH_LBG_MROM_DEVICE_ID_0) || \ + (DeviceId == V_PCH_LBG_PROD_MROM_DEVICE_ID_0) || \ + (DeviceId == V_PCH_LBG_MROM_DEVICE_ID_1) || \ + (DeviceId == V_PCH_LBG_PROD_MROM_DEVICE_ID_1) || \ + (DeviceId == V_PCH_LBG_THERMAL_DEVICE_ID) || \ + (DeviceId == V_PCH_LBG_PROD_THERMAL_DEVICE_ID) || \ + (DeviceId == V_PCH_LBG_LAN_DEVICE_ID) || \ + (DeviceId == V_PCH_LBG_PROD_LAN_DEVICE_ID) \ + ) + +/// +/// Any device ID that is PCH-H +/// +#define IS_PCH_H_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID (DeviceId) || \ + IS_PCH_H_SATA_DEVICE_ID (DeviceId) || \ + IS_PCH_H_USB_DEVICE_ID (DeviceId) || \ + IS_PCH_H_PCIE_DEVICE_ID (DeviceId) || \ + IS_PCH_H_SPI_DEVICE_ID (DeviceId) || \ + IS_PCH_H_HDA_DEVICE_ID (DeviceId) || \ + (DeviceId) == V_PCH_H_THERMAL_DEVICE_ID || \ + (DeviceId) == V_PCH_H_SMBUS_DEVICE_ID || \ + (DeviceId) == V_PCH_H_LAN_DEVICE_ID \ + ) + +/// +/// Any device ID that is PCH-Lp +/// +#define IS_PCH_LP_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LP_LPC_DEVICE_ID (DeviceId) || \ + IS_PCH_LP_SATA_DEVICE_ID (DeviceId) || \ + IS_PCH_LP_USB_DEVICE_ID (DeviceId) || \ + IS_PCH_LP_PCIE_DEVICE_ID (DeviceId) || \ + IS_PCH_LP_HDA_DEVICE_ID (DeviceId) || \ + (DeviceId == V_PCH_LP_THERMAL_DEVICE_ID) || \ + (DeviceId == V_PCH_LP_SMBUS_DEVICE_ID) || \ + (DeviceId == V_PCH_LP_SPI_DEVICE_ID) || \ + (DeviceId == V_PCH_LP_LAN_DEVICE_ID) || \ + (DeviceId == V_PCH_LP_SERIAL_IO_DMA_DEVICE_ID) || \ + (DeviceId == V_PCH_LP_SERIAL_IO_I2C0_DEVICE_ID) || \ + (DeviceId == V_PCH_LP_SERIAL_IO_I2C1_DEVICE_ID) || \ + (DeviceId == V_PCH_LP_SERIAL_IO_SPI0_DEVICE_ID) || \ + (DeviceId == V_PCH_LP_SERIAL_IO_SPI1_DEVICE_ID) || \ + (DeviceId == V_PCH_LP_SERIAL_IO_UART0_DEVICE_ID) || \ + (DeviceId == V_PCH_LP_SERIAL_IO_UART1_DEVICE_ID ) || \ + (DeviceId == V_PCH_LP_SERIAL_IO_SDIO_DEVICE_ID) \ + ) + +/// +/// Combined any device ID that is PCH-H or PCH-LP +/// +/// +/// And any device that is PCH LBG +/// +#define IS_PCH_DEVICE_ID(DeviceId) \ + (\ + IS_PCH_LBG_DEVICE_ID(DeviceId) \ + ) + + +/** + PCH PCR boot script accessing macro + Those macros are only available for DXE phase. +**/ +#define PCH_PCR_BOOT_SCRIPT_WRITE(Width, SbMmioBaseAddress, Pid, Offset, Count, Buffer) \ + S3BootScriptSaveMemWrite (Width, PCH_PCR_ADDRESS_BASE (SbMmioBaseAddress, Pid, Offset), Count, Buffer); \ + S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS_BASE (SbMmioBaseAddress, Pid, Offset), Buffer, Buffer, 1, 1); + +#define PCH_PCR_BOOT_SCRIPT_READ_WRITE(Width, SbMmioBaseAddress, Pid, Offset, DataOr, DataAnd) \ + S3BootScriptSaveMemReadWrite (Width, PCH_PCR_ADDRESS_BASE (SbMmioBaseAddress, Pid, Offset), DataOr, DataAnd); \ + S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS_BASE (SbMmioBaseAddress, Pid, Offset), DataOr, DataOr, 1, 1); + +#endif + diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchLimits.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchLimits.h new file mode 100644 index 0000000000..fc5e0f2516 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchLimits.h @@ -0,0 +1,108 @@ +/** @file + Build time limits of PCH resources. + + @copyright + Copyright 2013 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_LIMITS_H_ +#define _PCH_LIMITS_H_ + +// +// PCIe limits +// +#define PCH_MAX_PCIE_ROOT_PORTS PCH_H_PCIE_MAX_ROOT_PORTS +#define PCH_H_PCIE_MAX_ROOT_PORTS 20 +#define PCH_LP_PCIE_MAX_ROOT_PORTS 12 + +#define PCH_MAX_PCIE_CONTROLLERS PCH_H_PCIE_MAX_CONTROLLERS +#define PCH_PCIE_CONTROLLER_PORTS 4 +#define PCH_H_PCIE_MAX_CONTROLLERS (PCH_H_PCIE_MAX_ROOT_PORTS / PCH_PCIE_CONTROLLER_PORTS) +#define PCH_LP_PCIE_MAX_CONTROLLERS (PCH_LP_PCIE_MAX_ROOT_PORTS / PCH_PCIE_CONTROLLER_PORTS) + +#define PCH_MAX_WM20_LANES_NUMBER 20 + +// +// PCIe clocks limits +// +#define PCH_MAX_PCIE_CLOCKS PCH_H_PCIE_MAX_ROOT_PORTS +#define PCH_LP_PCIE_MAX_CLK_REQ 6 +#define PCH_H_PCIE_MAX_CLK_REQ 16 + +// +// RST PCIe Storage Cycle Router limits +// +#define PCH_MAX_RST_PCIE_STORAGE_CR 3 + +// +// SATA limits +// +#define SATA_1_CONTROLLER_INDEX 0 +#define SATA_2_CONTROLLER_INDEX 1 +#define SATA_3_CONTROLLER_INDEX 2 +#define PCH_MAX_SATA_CONTROLLERS 2 +#define PCH_MAX_SATA_PORTS PCH_H_AHCI_MAX_PORTS +#define PCH_MAX_SSATA_PORTS 6 +#define PCH_H_AHCI_MAX_PORTS 8 ///< Max number of sata ports in SKL PCH H +#define PCH_LP_AHCI_MAX_PORTS 3 ///< Max number of sata ports in SKL PCH LP +#define PCH_SATA_MAX_DEVICES_PER_PORT 1 ///< Max support device numner per port, Port Multiplier is not support. + +// +// USB limits +// +#define PCH_MAX_USB2_PORTS PCH_H_XHCI_MAX_USB2_PORTS + +#define PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS 14 ///< Max Physical Connector XHCI, not counting virtual ports like USB-R. +#define PCH_LP_XHCI_MAX_USB2_PHYSICAL_PORTS 10 ///< Max Physical Connector XHCI, not counting virtual ports like USB-R. + +#define PCH_H_XHCI_MAX_USB2_PORTS 16 ///< 14 High Speed lanes + Including two ports reserved for USBr +#define PCH_LP_XHCI_MAX_USB2_PORTS 12 ///< 10 High Speed lanes + Including two ports reserved for USBr + +#define PCH_MAX_USB3_PORTS PCH_H_XHCI_MAX_USB3_PORTS + +#define PCH_H_XHCI_MAX_USB3_PORTS 10 ///< 10 Super Speed lanes +#define PCH_LP_XHCI_MAX_USB3_PORTS 6 ///< 6 Super Speed lanes + +#define PCH_XHCI_MAX_SSIC_PORT_COUNT 2 ///< 2 SSIC ports in SKL PCH-LP and SKL PCH-H + +// +// SerialIo limits +// +#define PCH_SERIALIO_MAX_CONTROLLERS 11 ///< Number of SerialIo controllers, this includes I2C, SPI and UART +#define PCH_SERIALIO_MAX_I2C_CONTROLLERS 6 ///< Number of SerialIo I2C controllers +#define PCH_LP_SERIALIO_MAX_I2C_CONTROLLERS 6 ///< Number of SerialIo I2C controllers for PCH-LP +#define PCH_H_SERIALIO_MAX_I2C_CONTROLLERS 4 ///< Number of SerialIo I2C controllers for PCH-H +#define PCH_SERIALIO_MAX_SPI_CONTROLLERS 2 ///< Number of SerialIo SPI controllers +#define PCH_SERIALIO_MAX_UART_CONTROLLERS 3 ///< Number of SerialIo UART controllers + +// +// ISH limits +// +#define PCH_ISH_MAX_GP_PINS 8 +#define PCH_ISH_MAX_UART_CONTROLLERS 2 +#define PCH_ISH_MAX_I2C_CONTROLLERS 3 +#define PCH_ISH_MAX_SPI_CONTROLLERS 1 + +// +// SCS limits +// +#define PCH_SCS_MAX_CONTROLLERS 3 ///< Number of Storage and Communication Subsystem controllers, this includes eMMC, SDIO, SDCARD + +// +// Flash Protection Range Register +// +#define PCH_FLASH_PROTECTED_RANGES 5 + +// +// Number of eSPI slaves +// +#define PCH_ESPI_MAX_SLAVE_ID 2 + +#define PCH_PCIE_SWEQ_COEFFS_MAX 5 + +#define LBG_A0 0x30 + +#endif // _PCH_LIMITS_H_ + diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchPolicyCommon.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchPolicyCommon.h new file mode 100644 index 0000000000..f5861ccafd --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchPolicyCommon.h @@ -0,0 +1,2161 @@ +/** @file + PCH configuration based on PCH policy + + @copyright + Copyright 2009 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_POLICY_COMMON_H_ +#define _PCH_POLICY_COMMON_H_ + +#include "PchLimits.h" +#include +#include +#include + +#define FLASH_PROTECTION_CONFIG_REVISION 1 +extern EFI_GUID gFlashProtectionConfigGuid; + +#pragma pack (push,1) +// +// ---------------------------- PCH General Config ------------------------------- +// + +typedef struct { + /** + Subsystem Vendor ID and Subsystem ID of the PCH devices. + This fields will be ignored if the value of SubSystemVendorId and SubSystemId + are both 0. + **/ + UINT16 SubSystemVendorId; ///< Default Subsystem Vendor ID of the PCH devices. Default is 0x8086 + UINT16 SubSystemId; ///< Default Subsystem ID of the PCH devices. Default is 0x7270 + /** + This member describes whether or not the Compatibility Revision ID (CRID) feature + of PCH should be enabled. 0: Disable; 1: Enable + **/ + UINT32 Crid : 1; + UINT32 EnableClockSpreadSpec : 1; + UINT32 Serm : 1; + UINT32 RsvdBits0 : 29; ///< Reserved bits + UINT32 Rsvd0[2]; ///< Reserved bytes +} PCH_GENERAL_CONFIG; + + +#define FORCE_ENABLE 1 +#define FORCE_DISABLE 2 +#define PLATFORM_POR 0 +#define AUTO 0 +#define DCI_DISABLE 0 +// +// ---------------------------- Reserved Page Config ----------------------------- +// + +enum PCH_RESERVED_PAGE_ROUTE { + PchReservedPageToLpc, ///< Port 80h cycles are sent to LPC. + PchReservedPageToPcie ///< Port 80h cycles are sent to PCIe. +}; + +// +// ---------------------------- PCI Express Config ---------------------- +// + +enum PCH_PCIE_SPEED { + PchPcieAuto, + PchPcieGen1, + PchPcieGen2, + PchPcieGen3 +}; + +/// +/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature +/// +typedef enum { + PchPcieAspmDisabled, + PchPcieAspmL0s, + PchPcieAspmL1, + PchPcieAspmL0sL1, + PchPcieAspmAutoConfig, + PchPcieAspmMax +} PCH_PCIE_ASPM_CONTROL; + +/** + Refer to PCH EDS for the PCH implementation values corresponding + to below PCI-E spec defined ranges +**/ +typedef enum { + PchPcieL1SubstatesDisabled, + PchPcieL1SubstatesL1_1, + PchPcieL1SubstatesL1_2, + PchPcieL1SubstatesL1_1_2, + PchPcieL1SubstatesMax +} PCH_PCIE_L1SUBSTATES_CONTROL; + +enum PCH_PCIE_MAX_PAYLOAD { + PchPcieMaxPayload128 = 0, + PchPcieMaxPayload256, + PchPcieMaxPayloadMax +}; + +enum PCH_PCIE_COMPLETION_TIMEOUT { + PchPcieCompletionTO_Default, + PchPcieCompletionTO_50_100us, + PchPcieCompletionTO_1_10ms, + PchPcieCompletionTO_16_55ms, + PchPcieCompletionTO_65_210ms, + PchPcieCompletionTO_260_900ms, + PchPcieCompletionTO_1_3P5s, + PchPcieCompletionTO_4_13s, + PchPcieCompletionTO_17_64s, + PchPcieCompletionTO_Disabled +}; + +enum PCH_PCIE_MPL { + PchPcieMaxPayLoad128B, + PchPcieMaxPayLoad256B, + PchPcieMaxPayLoad512B, +}; + +typedef enum { + PchPcieEqDefault = 0, ///< Use reference code default (software margining) + PchPcieEqHardware = 1, ///< Hardware equalization (experimental), note this requires PCH-LP C0 or PCH-H D0 or newer + PchPcieEqSoftware = 2, ///< Use software margining flow + PchPcieEqStaticCoeff = 4 ///< Fixed equalization (requires Coefficient settings per lane) +} PCH_PCIE_EQ_METHOD; + +/** + Represent lane specific PCIe Gen3 equalization parameters. +**/ +typedef struct { + UINT8 Cm; ///< Coefficient C-1 + UINT8 Cp; ///< Coefficient C+1 + UINT8 Rsvd0[2]; ///< Reserved bytes +} PCH_PCIE_EQ_LANE_PARAM, PCH_PCIE_EQ_PARAM; + +/** + The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port. +**/ +typedef struct { + UINT32 Enable : 1; ///< Root Port enabling, 0: Disable; 1: Enable. + UINT32 HotPlug : 1; ///< Indicate whether the root port is hot plug available. 0: Disable; 1: Enable. + UINT32 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled. 0: Disable; 1: Enable. + UINT32 ExtSync : 1; ///< Indicate whether the extended synch is enabled. 0: Disable; 1: Enable. + UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled. 0: Disable; 1: Enable. + UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is enabled. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 5; ///< Reserved bits. + UINT32 ClkReqSupported : 1; ///< Indicate whether dedicated CLKREQ# is supported by the port. + /** + The ClkReq Signal mapped to this root port. Default is zero. Valid if ClkReqSupported is TRUE. + This Number should not exceed the Maximum Available ClkReq Signals for LP and H. + **/ + UINT32 ClkReqNumber : 4; + /** + Probe CLKREQ# signal before enabling CLKREQ# based power management. + Conforming device shall hold CLKREQ# low until CPM is enabled. This feature attempts + to verify CLKREQ# signal is connected by testing pad state before enabling CPM. + In particular this helps to avoid issues with open-ended PCIe slots. + This is only applicable to non hot-plug ports. + 0: Disable; 1: Enable. + **/ + UINT32 ClkReqDetect : 1; + // + // Error handlings + // + UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled. 0: Disable; 1: Enable. + UINT32 RsvdBits1 : 3; ///< Reserved fields for future expansion w/o protocol change + UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled. 0: Disable; 1: Enable. + UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled. 0: Disable; 1: Enable. + UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled. 0: Disable; 1: Enable. + UINT32 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled. 0: Disable; 1: Enable. + /** + Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD + Changes Max Payload Size Supported field in Device Capabilities of the root port. + **/ + UINT32 MaxPayload : 2; + + /** + Indicates how this root port is connected to endpoint. + 0: built-in device; + 1: slot + Built-in is incompatible with hotplug-capable ports + **/ + UINT32 SlotImplemented : 1; + + UINT32 DeviceResetPadActiveHigh : 1; ///< Indicated whether PERST# is active 0: Low; 1: High, See: DeviceResetPad + /** + Determines each PCIE Port speed capability. + 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED) + **/ + UINT8 PcieSpeed; + /** + PCIe Gen3 Equalization Phase 3 Method (see PCH_PCIE_EQ_METHOD). + 0: Default; 2: Software Search; 4: Fixed Coeficients + **/ + UINT8 Gen3EqPh3Method; + + UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index. + UINT8 CompletionTimeout; ///< The completion timeout configuration of the root port (see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. + /** + The PCH pin assigned to device PERST# signal if available, zero otherwise. + This entry is used mainly in Gen3 software equalization flow. It is necessary for some devices + (mainly some graphic adapters) to successfully complete the software equalization flow. + See also DeviceResetPadActiveHigh + **/ + UINT32 DeviceResetPad; + UINT32 Rsvd1; ///< Reserved bytes + // + // Power Management + // + UINT8 Aspm; ///< The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig. + UINT8 L1Substates; ///< The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2. + UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. 0: Disable; 1: Enable. + UINT8 LtrConfigLock; ///< 0: Disable; 1: Enable. + UINT16 LtrMaxSnoopLatency; ///< (Test) Latency Tolerance Reporting, Max Snoop Latency. + UINT16 LtrMaxNoSnoopLatency; ///< (Test) Latency Tolerance Reporting, Max Non-Snoop Latency. + UINT8 SnoopLatencyOverrideMode; ///< (Test) Latency Tolerance Reporting, Snoop Latency Override Mode. + UINT8 SnoopLatencyOverrideMultiplier; ///< (Test) Latency Tolerance Reporting, Snoop Latency Override Multiplier. + UINT16 SnoopLatencyOverrideValue; ///< (Test) Latency Tolerance Reporting, Snoop Latency Override Value. + UINT8 NonSnoopLatencyOverrideMode; ///< (Test) Latency Tolerance Reporting, Non-Snoop Latency Override Mode. + UINT8 NonSnoopLatencyOverrideMultiplier; ///< (Test) Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. + UINT16 NonSnoopLatencyOverrideValue; ///< (Test) Latency Tolerance Reporting, Non-Snoop Latency Override Value. + UINT32 SlotPowerLimitScale : 2; ///< (Test) Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is zero. + UINT32 SlotPowerLimitValue : 12; ///< (Test) Specifies upper limit on power supplie by slot. Leave as 0 to set to default. Default is zero. + + UINT32 HsioRxSetCtleEnable : 1; ///< @deprecated, please use HsioRxSetCtleEnable from PCH_HSIO_PCIE_LANE_CONFIG + UINT32 HsioRxSetCtle : 6; ///< @deprecated, please use HsioRxSetCtle from PCH_HSIO_PCIE_LANE_CONFIG + // + // Gen3 Equaliztion settings + // + UINT32 Uptp : 4; ///< (Test) Upstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. Default is 5. + UINT32 Dptp : 4; ///< (Test) Downstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. Default is 7. + UINT32 RsvdBits3 : 3; ///< Reserved Bits + UINT32 Rsvd2[16]; ///< Reserved bytes +} PCH_PCIE_ROOT_PORT_CONFIG; + +/// +/// The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers +/// +typedef struct { + /// + /// These members describe the configuration of each PCH PCIe root port. + /// + PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS]; + /// + /// Pci Delay (Latency) Optimization ECR - Engineering Change Request + /// + UINT8 PciDelayOptimizationEcr; + /// + /// Pch Pcie Max Read Request Size + /// + UINT8 MaxReadRequestSize; + /// + /// Gen3 Equalization settings for physiacal PCIe lane, index 0 represents PCIe lane 1, etc. + /// Correstponding entries are used when root port EqPh3Method is PchPcieEqStaticCoeff (default). + /// + PCH_PCIE_EQ_LANE_PARAM EqPh3LaneParam[PCH_MAX_PCIE_ROOT_PORTS]; + /// + /// (Test) This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable. + /// + UINT32 EnablePort8xhDecode : 1; + /// + /// (Test) The Index of PCIe Port that is selected for Port8xh Decode (0 Based) + /// + UINT32 PchPciePort8xhDecodePortIndex : 5; + /// + /// This member describes whether the PCI Express Clock Gating for each root port + /// is enabled by platform modules. 0: Disable; 1: Enable. + /// + UINT32 DisableRootPortClockGating : 1; + /// + /// This member describes whether Peer Memory Writes are enabled on the platform. 0: Disable; 1: Enable. + /// + UINT32 EnablePeerMemoryWrite : 1; + /** + This member allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable + or leaving untouched. + - 0: Disable, ICC PLL Shutdown is determined by PCIe device LTR capablility. + - To allow ICC PLL shutdown if all present PCIe devices are LTR capable or if no PCIe devices are + presented for maximum power savings where possible. + - To disable ICC PLL shutdown when BIOS detects any non-LTR capable PCIe device for ensuring device + functionality. + - 1: Enable, To allow ICC PLL shutdown even if some devices do not support LTR capability. + **/ + UINT32 AllowNoLtrIccPllShutdown : 1; + /** + Compliance Test Mode shall be enabled when using Compliance Load Board. + 0: Disable, 1: Enable + **/ + UINT32 ComplianceTestMode : 1; + /** + RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled. + A PCIE device can have higher functions only when Function0 exists. To satisfy this requirement, + BIOS will always enable Function0 of a device that contains more than 0 enabled root ports. + - Enabled: One of enabled root ports get assigned to Function0. + This offers no guarantee that any particular root port will be available at a specific DevNr:FuncNr location + - Disabled: Root port that corresponds to Function0 will be kept visible even though it might be not used. + That way rootport - to - DevNr:FuncNr assignment is constant. This option will impact ports 1, 9, 17. + NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage + NOTE: Disabling function swap may have adverse impact on power management. This option should ONLY + be used when each one of root ports 1, 9, 17: + - is configured as PCIe and has correctly configured ClkReq signal, or + - does not own any mPhy lanes (they are configured as SATA or USB) + **/ + UINT32 RpFunctionSwap : 1; + + UINT32 RsvdBits0 : 21; + /** + The number of milliseconds reference code will wait for link to exit Detect state for enabled ports + before assuming there is no device and potentially disabling the port. + It's assumed that the link will exit detect state before root port initialization (sufficient time + elapsed since PLTRST de-assertion) therefore default timeout is zero. However this might be useful + if device power-up seqence is controlled by BIOS or a specific device requires more time to detect. + I case of non-common clock enabled the default timout is 15ms. + Default: 0 + **/ + UINT16 DetectTimeoutMs; + + /// + /// These are Competions Timeout settings for Uplink ports in Server PCH + /// + UINT8 PchPcieUX16CompletionTimeout; + UINT8 PchPcieUX8CompletionTimeout; + + /// + /// Max Payload Size settings for Upling ports in Server PCH + /// + UINT8 PchPcieUX16MaxPayload; + UINT8 PchPcieUX8MaxPayload; + + /// + /// Intel+ Virtual Technology for Directed I/O (VT-d) Support + /// + UINT8 VTdSupport; + UINT16 Rsvd0; ///< Reserved bytes + UINT32 Rsvd1[2]; ///< Reserved bytes +} PCH_PCIE_CONFIG; + + +/// +/// The PCH_PCIE_CONFIG2 block describes the additional configuration of the PCH PCI Express controllers +/// +typedef struct { + PCH_PCIE_EQ_PARAM SwEqCoeffList[PCH_PCIE_SWEQ_COEFFS_MAX]; ///< List of coefficients used during equalization (applicable to both software and hardware EQ) + PCH_PCIE_EQ_PARAM Rsvd0[3]; + UINT32 Rsvd1[4]; +} PCH_PCIE_CONFIG2; + +typedef struct { + UINT8 PchAdrEn; + UINT8 AdrTimerEn; + UINT8 AdrTimerVal; + UINT8 AdrMultiplierVal; + UINT8 AdrGpioSel; + UINT8 AdrHostPartitionReset; + UINT8 AdrSysPwrOk; + UINT8 AdrOverClockingWdt; + UINT8 AdrCpuThermalWdt; + UINT8 AdrPmcParityError; +} PCH_ADR_CONFIG; + +/** + The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane +**/ +typedef struct { + // + // HSIO Rx Eq + // Refer to the EDS for recommended values. + // Note that these setting are per-lane and not per-port + // + UINT32 HsioRxSetCtleEnable : 1; ///< 0: Disable; 1: Enable PCH PCIe Gen 3 Set CTLE Value + UINT32 HsioRxSetCtle : 6; ///< PCH PCIe Gen 3 Set CTLE Value + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< 0: Disable; 1: Enable PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value override + UINT32 HsioTxGen1DownscaleAmp : 6; ///< PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< 0: Disable; 1: Enable PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value override + UINT32 HsioTxGen2DownscaleAmp : 6; ///< PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value + UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< 0: Disable; 1: Enable PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value override + UINT32 HsioTxGen3DownscaleAmp : 6; ///< PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value + UINT32 RsvdBits0 : 4; ///< Reserved Bits + + UINT32 HsioTxGen1DeEmphEnable : 1; ///< 0: Disable; 1: Enable PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting value override + UINT32 HsioTxGen1DeEmph : 6; ///< PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting + UINT32 HsioTxGen2DeEmph3p5Enable : 1; ///< 0: Disable; 1: Enable PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting value override + UINT32 HsioTxGen2DeEmph3p5 : 6; ///< PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting + UINT32 HsioTxGen2DeEmph6p0Enable : 1; ///< 0: Disable; 1: Enable PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting value override + UINT32 HsioTxGen2DeEmph6p0 : 6; ///< PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting + UINT32 RsvdBits1 : 11; ///< Reserved Bits + + // + // Server specific offsets + // + UINT32 HsioIcfgAdjLimitLoEnable : 1; /// < 0: Disable; 1: Enable Set the floor on how many ticks the autovref can take. + UINT32 HsioIcfgAdjLimitLo : 5; /// < Set the floor on how many ticks the autovref can take. (offset 0x9c) + UINT32 HsioSampOffstEvenErrSpEnable : 1; /// < 0: Disable; 1: Enable EVEN ERR P sampler manual offset. + UINT32 HsioSampOffstEvenErrSp : 8; /// < EVEN ERR P sampler manual offset. (offset 0xA0) + UINT32 RsvdBits2 : 17; ///< Reserved Bits + + UINT32 HsioRemainingSamplerOffEnable : 1; /// < 0: Disable; 1: Enable Remaining EVEN/ODD ERR P and N sampler manual offset. + UINT32 HsioRemainingSamplerOff : 24; /// < Remaining EVEN/ODD ERR P and N sampler manual offset. (offset 0xA4) + UINT32 HsioVgaGainCalEnable : 1; /// < 0: Disable; 1: Enable VGA Gain CAL + UINT32 HsioVgaGainCal : 5; /// < VGA Gain Calibration Value (offset 0x1C) + UINT32 RsvdBits3 : 1; ///< Reserved Bits + + UINT32 Rsvd4[12]; ///< Reserved bytes + +} PCH_HSIO_PCIE_LANE_CONFIG; + +/// +/// The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO for PCIe lanes +/// +typedef struct { + /// + /// These members describe the configuration of HSIO for PCIe lanes. + /// + PCH_HSIO_PCIE_LANE_CONFIG Lane[PCH_MAX_PCIE_ROOT_PORTS]; + UINT32 Rsvd0[3]; ///< Reserved bytes + +} PCH_HSIO_PCIE_CONFIG; + + +/// +/// The PCH_HSIO_PCIE_WM20_CONFIG block describes the configuration of the HSIO for PCIe lanes +/// +typedef struct { + /// + /// These members describe the configuration of HSIO for PCIe lanes. + /// + PCH_HSIO_PCIE_LANE_CONFIG Lane[PCH_MAX_WM20_LANES_NUMBER]; + UINT32 Rsvd0[3]; ///< Reserved bytes + +} PCH_HSIO_PCIE_WM20_CONFIG; + +// +// ---------------------------- EVA Config ----------------------------- +// + +// EVA port function hide registers. + +typedef union { + UINT32 FuncHideVal; + struct _FuncHideBits { + UINT32 PchEvaMROM0Enable : 1; ///< MROM is never hidden + UINT32 PchEvaMROM1Hidden : 1; ///< Enable/disable MROM1 funcion, 1 - hidden + UINT32 RsvdBits1 : 3; + UINT32 PchEvasSata1Hidden : 1; ///< Enable/disable sSata1, 1 - hidden + UINT32 RsvdBits2 : 25; + UINT32 PchEvaLock : 1; ///< Lock registers in EVA + + } FuncHideBits; +} +PCH_EVA_DNDEVFUNCHIDE; + + +typedef struct { + PCH_EVA_DNDEVFUNCHIDE FuncHide; + UINT8 LockDown; +} +PCH_EVA_CONFIG; +// +// ---------------------------- SATA Config ----------------------------- +// + +typedef enum { + PchSataModeAhci, + PchSataModeRaid, + PchSataModeMax +} PCH_SATA_MODE; + +typedef enum { + PchSataOromDelay2sec, + PchSataOromDelay4sec, + PchSataOromDelay6sec, + PchSataOromDelay8sec +} PCH_SATA_OROM_DELAY; + +typedef enum { + PchSataSpeedDefault, + PchSataSpeedGen1, + PchSataSpeedGen2, + PchSataSpeedGen3 +} PCH_SATA_SPEED; + +/** + This structure configures the features, property, and capability for each SATA port. +**/ +typedef struct { + /** + Enable SATA port. + It is highly recommended to disable unused ports for power savings + **/ + UINT32 Enable : 1; ///< 0: Disable; 1: Enable + UINT32 HotPlug : 1; ///< 0: Disable; 1: Enable + UINT32 InterlockSw : 1; ///< 0: Disable; 1: Enable + UINT32 External : 1; ///< 0: Disable; 1: Enable + UINT32 SpinUp : 1; ///< 0: Disable; 1: Enable the COMRESET initialization Sequence to the device + UINT32 SolidStateDrive : 1; ///< 0: HDD; 1: SSD + UINT32 DevSlp : 1; ///< 0: Disable; 1: Enable DEVSLP on the port + UINT32 EnableDitoConfig : 1; ///< 0: Disable; 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal) + UINT32 DmVal : 4; ///< DITO multiplier. Default is 15. + UINT32 DitoVal : 10; ///< DEVSLP Idle Timeout (DITO), Default is 625. + /** + Support zero power ODD 0: Disable, 1: Enable. + This is also used to disable ModPHY dynamic power gate. + **/ + UINT32 ZpOdd : 1; + UINT32 RsvdBits0 : 9; ///< Reserved fields for future expansion w/o protocol change + + UINT32 HsioRxEqBoostMagAdEnable : 1; ///< @deprecated, please use HsioRxGen3EqBoostMagEnable + UINT32 HsioRxEqBoostMagAd : 6; ///< @deprecated, please use HsioRxGen3EqBoostMag + + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< @deprecated, please use HsioTxGen1DownscaleAmpEnable in PCH_HSIO_SATA_PORT_LANE + UINT32 HsioTxGen1DownscaleAmp : 6; ///< @deprecated, please use HsioTxGen1DownscaleAmp in PCH_HSIO_SATA_PORT_LANE + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< @deprecated, please use HsioTxGen2DownscaleAmpEnable in PCH_HSIO_SATA_PORT_LANE + UINT32 HsioTxGen2DownscaleAmp : 6; ///< @deprecated, please use HsioTxGen2DownscaleAmp in PCH_HSIO_SATA_PORT_LANE + UINT32 Rsvd0 : 11; ///< Reserved bits + +} PCH_SATA_PORT_CONFIG; + +/** + Rapid Storage Technology settings. +**/ +typedef struct { + UINT32 RaidAlternateId : 1; ///< 0: Disable; 1: Enable RAID Alternate ID + UINT32 Raid0 : 1; ///< 0: Disable; 1: Enable RAID0 + UINT32 Raid1 : 1; ///< 0: Disable; 1: Enable RAID1 + UINT32 Raid10 : 1; ///< 0: Disable; 1: Enable RAID10 + UINT32 Raid5 : 1; ///< 0: Disable; 1: Enable RAID5 + UINT32 Irrt : 1; ///< 0: Disable; 1: Enable Intel Rapid Recovery Technology + UINT32 OromUiBanner : 1; ///< 0: Disable; 1: Enable OROM UI and BANNER + UINT32 OromUiDelay : 2; ///< 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY) + UINT32 HddUnlock : 1; ///< 0: Disable; 1: Enable. Indicates that the HDD password unlock in the OS is enabled + UINT32 LedLocate : 1; ///< 0: Disable; 1: Enable. Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS + UINT32 IrrtOnly : 1; ///< 0: Disable; 1: Enable. Allow only IRRT drives to span internal and external ports + UINT32 SmartStorage : 1; ///< 0: Disable; 1: Enable RST Smart Storage caching Bit + UINT32 EfiRaidDriverLoad :1; ///< 0: Dont load EFI RST/RSTe driver; 1: Load EFI RST/RSTe driver + UINT32 Resvdbits : 18; ///< Reserved Bits +} PCH_SATA_RST_CONFIG; + +/** + This structure describes the details of Intel RST for PCIe Storage remapping + Note: In order to use this feature, Intel RST Driver is required +**/ +typedef struct { + /** + This member describes whether or not the Intel RST for PCIe Storage remapping should be enabled. 0: Disable; 1: Enable. + Note 1: If Sata Controller is disabled, PCIe Storage Remapping should be disabled as well + Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHCI controllers Class Code is configured as RAID + **/ + UINT32 Enable : 1; + /** + Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect) + The supported ports for PCIe Storage remapping is different depend on the platform and cycle router, the assignments are as below: + SKL PCH-LP RST PCIe Storage Cycle Router Assignment: + i.) RST PCIe Storage Cycle Router 2 -> RP5 - RP8 + ii.) RST PCIe Storage Cycle Router 3 -> RP9 - RP12 + + SKL PCH-H RST PCIe Storage Cycle Router Assignment: + i.) RST PCIe Storage Cycle Router 1 -> RP9 - RP12 + ii.) RST PCIe Storage Cycle Router 2 -> RP13 - RP16 + iii.) RST PCIe Storage Cycle Router 3 -> RP17 - RP20 + **/ + UINT32 RstPcieStoragePort : 5; + UINT32 RsvdBits0 : 2; ///< Reserved bit + /** + PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees such delay gap is fulfilled + before PCIe Storage Device configuration space is accessed after an reset caused by the link disable and enable step. + Default value is 100ms. + **/ + UINT32 DeviceResetDelay : 8; + UINT32 RsvdBits1 : 16; ///< Reserved bits + + UINT32 Rsvd0[2]; ///< Reserved bytes +} PCH_RST_PCIE_STORAGE_CONFIG; + +/// +/// The PCH_SATA_CONFIG block describes the expected configuration of the SATA controllers. +/// +typedef struct { + /// + /// This member describes whether or not the SATA controllers should be enabled. 0: Disable; 1: Enable. + /// + UINT32 Enable : 1; + UINT32 TestMode : 1; ///< (Test) 0: Disable; 1: Allow entrance to the PCH SATA test modes + UINT32 SalpSupport : 1; ///< 0: Disable; 1: Enable Aggressive Link Power Management + UINT32 PwrOptEnable : 1; ///< 0: Disable; 1: Enable SATA Power Optimizer on PCH side. + /** + eSATASpeedLimit + When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. + Please be noted, this setting could be cleared by HBA reset, which might be issued + by EFI AHCI driver when POST time, or by SATA inbox driver/RST driver after POST. + To support the Speed Limitation when POST, the EFI AHCI driver should preserve the + setting before and after initialization. For support it after POST, it's dependent on + driver's behavior. + 0: Disable; 1: Enable + **/ + UINT32 eSATASpeedLimit : 1; + UINT32 EnclosureSupport : 1; ///< 0: Disable; 1: Enable Enclosure Management Support + UINT32 Rsvdbits : 26; ///< Reserved bits + + /** + Determines the system will be configured to which SATA mode (PCH_SATA_MODE). Default is PchSataModeAhci. + **/ + PCH_SATA_MODE SataMode; + /** + Indicates the maximum speed the SATA controller can support + 0h: PchSataSpeedDefault; 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2); 3h: 6 Gb/s (Gen 1) + **/ + PCH_SATA_SPEED SpeedLimit; + /** + This member configures the features, property, and capability for each SATA port. + **/ + PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS]; + PCH_SATA_RST_CONFIG Rst; ///< Setting applicable to Rapid Storage Technology + /** + This member describes the details of implementation of Intel RST for PCIe Storage remapping (Intel RST Driver is required) + **/ + PCH_RST_PCIE_STORAGE_CONFIG RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORAGE_CR]; + UINT32 Rsvd0[4]; ///< Reserved fields for future expansion +} PCH_SATA_CONFIG; + + +/** + The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane +**/ +typedef struct { + + // + // HSIO Rx Eq + // + UINT32 HsioRxGen1EqBoostMagEnable : 1; ///< 0: Disable; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override + UINT32 HsioRxGen1EqBoostMag : 6; ///< SATA 1.5 Gb/sReceiver Equalization Boost Magnitude Adjustment value + UINT32 HsioRxGen2EqBoostMagEnable : 1; ///< 0: Disable; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override + UINT32 HsioRxGen2EqBoostMag : 6; ///< SATA 3.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value + UINT32 HsioRxGen3EqBoostMagEnable : 1; ///< 0: Disable; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override + UINT32 HsioRxGen3EqBoostMag : 6; ///< SATA 6.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value + + // + // HSIO Tx Eq + // + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< 0: Disable; 1: Enable SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override + UINT32 HsioTxGen1DownscaleAmp : 6; ///< SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value + UINT32 RsvdBits0 : 4; ///< Reserved bits + + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< 0: Disable; 1: Enable SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override + UINT32 HsioTxGen2DownscaleAmp : 6; ///< SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment + UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< 0: Disable; 1: Enable SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override + UINT32 HsioTxGen3DownscaleAmp : 6; ///< SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment + UINT32 HsioTxGen1DeEmphEnable : 1; ///< 0: Disable; 1: Enable SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override + UINT32 HsioTxGen1DeEmph : 6; ///< SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting + + UINT32 HsioTxGen2DeEmphEnable : 1; ///< 0: Disable; 1: Enable SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + UINT32 HsioTxGen2DeEmph : 6; ///< SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting + UINT32 RsvdBits1 : 4; ///< Reserved bits + + UINT32 HsioTxGen3DeEmphEnable : 1; ///< 0: Disable; 1: Enable SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + UINT32 HsioTxGen3DeEmph : 6; ///< SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + UINT32 RsvdBits2 : 25; ///< Reserved bits + + UINT32 Rsvd0[8]; ///< Reserved bytes +} PCH_HSIO_SATA_PORT_LANE; + + +/// +/// The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the SATA controller. +/// +typedef struct { + /// + /// These members describe the configuration of HSIO for SATA lanes. + /// + PCH_HSIO_SATA_PORT_LANE PortLane[PCH_MAX_SATA_PORTS]; + UINT32 Rsvd0[8]; ///< Reserved bytes + +} PCH_HSIO_SATA_CONFIG; + +// +// --------------------------- IO APIC Config ------------------------------ +// +/** + The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH + IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is + not TRUE. Bus:device:function fields will be programmed to the register + P2SB IBDF(P2SB PCI offset R6Ch-6Dh), it's using for the following purpose: + As the Requester ID when initiating Interrupt Messages to the processor. + As the Completer ID when responding to the reads targeting the IOxAPI's + Memory-Mapped I/O registers. + This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can + program this field to provide a unique Bus:Device:Function number for the + internal IOxAPIC. + The address resource range of IOAPIC must be reserved in E820 and ACPI as + system resource. +**/ +typedef struct { + UINT32 BdfValid : 1; ///< Set to 1 if BDF value is valid, PCH code will not program these fields if this bit is not TRUE. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 7; ///< Reserved bits + UINT32 BusNumber : 8; ///< Bus/Device/Function used as Requestor / Completer ID. Default is 0xF0. + UINT32 DeviceNumber : 5; ///< Bus/Device/Function used as Requestor / Completer ID. Default is 0x1F. + UINT32 FunctionNumber : 3; ///< Bus/Device/Function used as Requestor / Completer ID. Default is 0x00. + UINT32 IoApicEntry24_119 : 1; ///< 0: Disable; 1: Enable IOAPIC Entry 24-119 + UINT32 RsvdBits1 : 7; ///< Reserved bits + UINT8 IoApicId; ///< This member determines IOAPIC ID. Default is 0x02. + UINT8 ApicRangeSelect; ///< Define address bits 19:12 for the IOxAPIC range. Default is 0 + UINT8 Rsvd0[2]; ///< Reserved bytes +} PCH_IOAPIC_CONFIG; + +// +// ---------------------------- HPET Config ----------------------------- +// + +/** + The PCH_HPET_CONFIG block passes the bus/device/function value for HPET. + The address resource range of HPET must be reserved in E820 and ACPI as + system resource. +**/ +typedef struct { + /** + Determines if enable HPET timer. 0: Disable; 1: Enable. + The HPET timer address decode is always enabled. + This policy is used to configure the HPET timer count, and also the _STA of HPET device in ACPI. + While enabled, the HPET timer is started, else the HPET timer is halted. + **/ + UINT32 Enable : 1; + UINT32 BdfValid : 1; ///< Whether the BDF value is valid. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 6; ///< Reserved bits + UINT32 BusNumber : 8; ///< Bus Number HPETn used as Requestor / Completer ID. Default is 0xF0. + UINT32 DeviceNumber : 5; ///< Device Number HPETn used as Requestor / Completer ID. Default is 0x1F. + UINT32 FunctionNumber : 3; ///< Function Number HPETn used as Requestor / Completer ID. Default is 0x00. + UINT32 RsvdBits1 : 8; ///< Reserved bits + UINT32 Base; ///< The HPET base address. Default is 0xFED00000. +} PCH_HPET_CONFIG; + +// +// --------------------------- HD-Audio Config ------------------------------ +// +/// +/// The PCH_HDAUDIO_CONFIG block describes the expected configuration of the Intel HD Audio feature. +/// +#define PCH_HDAUDIO_AUTO 2 + +enum PCH_HDAUDIO_IO_BUFFER_OWNERSHIP { + PchHdaIoBufOwnerHdaLink = 0, ///< HD-Audio link owns all the I/O buffers. + PchHdaIoBufOwnerHdaLinkI2sPort = 1, ///< HD-Audio link owns 4 and I2S port owns 4 of the I/O buffers. + PchHdaIoBufOwnerI2sPort = 3 ///< I2S0 and I2S1 ports own all the I/O buffers. +}; + +enum PCH_HDAUDIO_IO_BUFFER_VOLTAGE { + PchHdaIoBuf33V = 0, + PchHdaIoBuf18V = 1 +}; + +enum PCH_HDAUDIO_VC_TYPE { + PchHdaVc0 = 0, + PchHdaVc1 = 1 +}; + +enum PCH_HDAUDIO_DMIC_TYPE { + PchHdaDmicDisabled = 0, + PchHdaDmic2chArray = 1, + PchHdaDmic4chArray = 2, + PchHdaDmic1chArray = 3 +}; + +typedef enum { + PchHdaLinkFreq6MHz = 0, + PchHdaLinkFreq12MHz = 1, + PchHdaLinkFreq24MHz = 2, + PchHdaLinkFreq48MHz = 3, + PchHdaLinkFreq96MHz = 4, + PchHdaLinkFreqInvalid +} PCH_HDAUDIO_LINK_FREQUENCY; + +typedef enum { + PchHdaIDispMode2T = 0, + PchHdaIDispMode1T = 1 +} PCH_HDAUDIO_IDISP_TMODE; + +typedef struct { + /** + This member describes whether or not Intel HD Audio (Azalia) should be enabled. + If enabled (in Auto mode) and no codec exists the reference code will automatically disable + the HD Audio device. + 0: Disable, 1: Enable, 2: Auto (enabled if codec detected and initialized, disabled otherwise) + **/ + UINT32 Enable : 2; + UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; 1: Enable + UINT32 Pme : 1; ///< Azalia wake-on-ring, 0: Disable; 1: Enable + UINT32 IoBufferOwnership : 2; ///< I/O Buffer Ownership Select: 0: HD-A Link; 1: Shared, HD-A Link and I2S Port; 3: I2S Ports + UINT32 IoBufferVoltage : 1; ///< I/O Buffer Voltage Mode Select: 0: 3.3V; 1: 1.8V + UINT32 VcType : 1; ///< Virtual Channel Type Select: 0: VC0, 1: VC1 + UINT32 HdAudioLinkFrequency : 4; ///< HDA-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): 2: 24MHz, 1: 12MHz, 0: 6MHz + UINT32 IDispLinkFrequency : 4; ///< iDisp-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz + UINT32 IDispLinkTmode : 1; ///< iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T + /** + Universal Audio Architecture compliance for DSP enabled system: + 0: Not-UAA Compliant (Intel SST driver supported only), + 1: UAA Compliant (HDA Inbox driver or SST driver supported) + **/ + UINT32 DspUaaCompliance : 1; + UINT32 IDispCodecDisconnect : 1; ///< iDisplay Audio Codec disconnection, 0: Not disconnected, enumerable; 1: Disconnected SDI, not enumerable + UINT32 RsvdBits0 : 13; ///< Reserved bits 1 + /** + Bitmask of supported DSP endpoint configuration exposed via NHLT ACPI table: + **/ + UINT32 DspEndpointDmic : 2; ///< DMIC Select (PCH_HDAUDIO_DMIC_TYPE enum): 0: Disable; 1: 2ch array; 2: 4ch array; 3: 1ch array + UINT32 DspEndpointBluetooth : 1; ///< Bluetooth enablement: 0: Disable; 1: Enable + UINT32 DspEndpointI2s : 1; ///< I2S enablement: 0: Disable; 1: Enable + UINT32 RsvdBits1 : 28; ///< Reserved bits 2 + /** + Bitmask of supported DSP features: + [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6] - BT Intel A2DP + [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel WoV, 1: Windows Voice Activation + Default is zero. + **/ + UINT32 DspFeatureMask; + /** + Bitmask of supported DSP Pre/Post-Processing Modules. + Specific pre/post-processing module bit position must be coherent with the ACPI implementation: + \_SB.PCI0.HDAS._DSM Function 3: Query Pre/Post Processing Module Support. + DspPpModuleMask is passed to ACPI as 'ADPM' NVS variable + Default is zero. + **/ + UINT32 DspPpModuleMask; + UINT16 ResetWaitTimer; ///< (Test) The delay timer after Azalia reset, the value is number of microseconds. Default is 600. + UINT8 Rsvd0[2]; ///< Reserved bytes, align to multiple 4 +} PCH_HDAUDIO_CONFIG; + +// +// ------------------------------ LAN Config --------------------------------- +// + +/** + PCH intergrated LAN controller configuration settings. +**/ +typedef struct { + /** + Determines if enable PCH internal LAN, 0: Disable; 1: Enable. + When Enable is changed (from disabled to enabled or from enabled to disabled), + it needs to set LAN Disable regsiter, which might be locked by FDSWL register. + So it's recommendated to issue a global reset when changing the status for PCH Internal LAN. + **/ + UINT32 Enable : 1; + UINT32 K1OffEnable : 1; ///< Use CLKREQ for GbE power management; 1: Enabled, 0: Disabled; + UINT32 RsvdBits0 : 4; ///< Reserved bits + UINT32 ClkReqSupported : 1; ///< Indicate whether dedicated CLKREQ# is supported; 1: Enabled, 0: Disabled; + UINT32 ClkReqNumber : 4; ///< CLKREQ# used by GbE. Valid if ClkReqSupported is TRUE. + UINT32 RsvdBits1 : 21; ///< Reserved bits + UINT32 Rsvd0; ///< Reserved bytes +} PCH_LAN_CONFIG; + +// +// --------------------------- SMBUS Config ------------------------------ +// + +#define PCH_MAX_SMBUS_RESERVED_ADDRESS 128 + +/// +/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform. +/// +typedef struct { + /** + This member describes whether or not the SMBus controller of PCH should be enabled. + 0: Disable; 1: Enable. + **/ + UINT32 Enable : 1; + UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, 0: Disable; 1: Enable. + UINT32 DynamicPowerGating : 1; ///< (Test) Disable or Enable Smbus dynamic power gating. + UINT32 RsvdBits0 : 29; ///< Reserved bits + UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space). Default is 0xEFA0. + UINT8 Rsvd0; ///< Reserved bytes + UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbusAddressTable. + /** + Array of addresses reserved for non-ARP-capable SMBus devices. + **/ + UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS]; +} PCH_SMBUS_CONFIG; + +// +// --------------------------- Lock Down Config ------------------------------ +// +/** + The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH + for security requirement. +**/ +typedef struct { + /** + (Test) Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0: Disable; 1: Enable. + **/ + UINT32 GlobalSmi : 1; + /** + (Test) Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register + Top Swap bit and the General Control and Status Registers Boot BIOS Straps. 0: Disable; 1: Enable. + **/ + UINT32 BiosInterface : 1; + /** + (Test) Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper + and lower 128-byte bank of RTC RAM. 0: Disable; 1: Enable. + **/ + UINT32 RtcLock : 1; + /** + Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:RegDCh[5]) + for the BIOS region protection. When it is enabled, the BIOS Region can only be + modified from SMM after EndOfDxe protocol is installed. + Note: When BiosLock is enabled, platform code also needs to update to take care + of BIOS modification (including SetVariable) in DXE or runtime phase after + EndOfDxe protocol is installed. 0: Disable; 1: Enable. + **/ + UINT32 BiosLock : 1; + /** + Enable InSMM.STS (EISS) in SPI + If this bit is set, then WPD must be a '1' and InSMM.STS must be '1' also + in order to write to BIOS regions of SPI Flash. If this bit is clear, + then the InSMM.STS is a don't care. + The BIOS must set the EISS bit while BIOS Guard support is enabled. + In recovery path, platform can temporary disable EISS for SPI programming in + PEI phase or early DXE phase. + 0: Clear EISS bit; 1: Set EISS bit. + **/ + UINT32 SpiEiss : 1; + /** + Lock configuration and/or state of vendor-defined set of GPIOs. + 0: Don't lock; 1: Lock + **/ + UINT32 GpioLockDown : 1; + /** + Lock TCO Base Address. + D31:F4 (SMBus Controller) Offset 54h: TCOCTL (TCO Control Register) Bit 0: TCO_BASE_LOCK (TCO Base Lock) + 0: Don't lock; 1: Lock + **/ + UINT32 TcoLock : 1; + + /** + (Test) Enable Lock bit for Device Function Hide Register in + MS Unit Device Function Hide Control Register (MSDEVFUNCHIDE) + 0: Disable; 1: Enable. + **/ + UINT32 EvaLockDown : 1; + UINT32 RsvdBits0 : 24; ///< Reserved bits +} PCH_LOCK_DOWN_CONFIG; + +// +// --------------------------- Thermal Config ------------------------------------ +// +/** + This structure lists PCH supported throttling register setting for custimization. + When the SuggestedSetting is enabled, the customized values are ignored. +**/ +typedef struct { + UINT32 T0Level : 9; ///< Custimized T0Level value. If SuggestedSetting is used, this setting is ignored. + UINT32 T1Level : 9; ///< Custimized T1Level value. If SuggestedSetting is used, this setting is ignored. + UINT32 T2Level : 9; ///< Custimized T2Level value. If SuggestedSetting is used, this setting is ignored. + UINT32 TTEnable : 1; ///< Enable the thermal throttle function. If SuggestedSetting is used, this settings is ignored. + /** + When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. + If SuggestedSetting is used, this setting is ignored. + **/ + UINT32 TTState13Enable : 1; + /** + When set to 1, this entire register (TL) is locked and remains locked until the next platform reset. + If SuggestedSetting is used, this setting is ignored. + **/ + UINT32 TTLock : 1; + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable suggested representative values. + /** + ULT processors support thermal management and cross thermal throttling between the processor package + and LP PCH. The PMSYNC message from PCH to CPU includes specific bit fields to update the PCH + thermal status to the processor which is factored into the processor throttling. + Enable/Disable PCH Cross Throttling; 0: Disabled, 1: Enabled. + **/ + UINT32 PchCrossThrottling : 1; + UINT32 Rsvd0; ///< Reserved bytes +} THERMAL_THROTTLE_LEVELS; + +/** + This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design. + When the SuggestedSetting is enabled, the customized values are ignored. +**/ +typedef struct { + UINT32 DmiTsawEn : 1; ///< DMI Thermal Sensor Autonomous Width Enable + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable suggested representative values + UINT32 RsvdBits0 : 6; ///< Reserved bits + UINT32 TS0TW : 2; ///< Thermal Sensor 0 Target Width + UINT32 TS1TW : 2; ///< Thermal Sensor 1 Target Width + UINT32 TS2TW : 2; ///< Thermal Sensor 2 Target Width + UINT32 TS3TW : 2; ///< Thermal Sensor 3 Target Width + UINT32 RsvdBits1 : 16; ///< Reserved bits +} DMI_HW_WIDTH_CONTROL; + +/** + This structure lists PCH supported SATA thermal throttling register setting for custimization. + The settings is programmed through SATA Index/Data registers. + When the SuggestedSetting is enabled, the customized values are ignored. +**/ +typedef struct { + UINT32 P0T1M : 2; ///< Port 0 T1 Multipler + UINT32 P0T2M : 2; ///< Port 0 T2 Multipler + UINT32 P0T3M : 2; ///< Port 0 T3 Multipler + UINT32 P0TDisp : 2; ///< Port 0 Tdispatch + + UINT32 P1T1M : 2; ///< Port 1 T1 Multipler + UINT32 P1T2M : 2; ///< Port 1 T2 Multipler + UINT32 P1T3M : 2; ///< Port 1 T3 Multipler + UINT32 P1TDisp : 2; ///< Port 1 Tdispatch + + UINT32 P0Tinact : 2; ///< Port 0 Tinactive + UINT32 P0TDispFinit : 1; ///< Port 0 Alternate Fast Init Tdispatch + UINT32 P1Tinact : 2; ///< Port 1 Tinactive + UINT32 P1TDispFinit : 1; ///< Port 1 Alternate Fast Init Tdispatch + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable suggested representative values + UINT32 RsvdBits0 : 9; ///< Reserved bits +} SATA_THERMAL_THROTTLE; + +/** + This structure decides the settings of PCH Thermal throttling. When the Suggested Setting + is enabled, PCH RC will use the suggested representative values. +**/ +typedef struct { + THERMAL_THROTTLE_LEVELS TTLevels; + DMI_HW_WIDTH_CONTROL DmiHaAWC; + SATA_THERMAL_THROTTLE SataTT; + SATA_THERMAL_THROTTLE sSataTT; +} PCH_THERMAL_THROTTLING; + +/** + This structure configures PCH memory throttling thermal sensor GPIO PIN settings +**/ +typedef struct { + /** + GPIO PM_SYNC enable, 0:Diabled, 1:Enabled + When enabled, RC will overrides the selected GPIO native mode. + For GPIO_C, PinSelection 0: CPU_GP_0 (default) or 1: CPU_GP_1 + For GPIO_D, PinSelection 0: CPU_GP_3 (default) or 1: CPU_GP_2 + For SKL: CPU_GP_0 is GPP_E3, CPU_GP_1 is GPP_E7, CPU_GP_2 is GPP_B3, CPU_GP_3 is GPP_B4. + **/ + UINT32 PmsyncEnable : 1; + UINT32 C0TransmitEnable : 1; ///< GPIO Transmit enable in C0 state, 0:Disabled, 1:Enabled + UINT32 PinSelection : 1; ///< GPIO Pin assignment selection, 0: default, 1: secondary + UINT32 RsvdBits0 : 29; +} TS_GPIO_PIN_SETTING; + +enum PCH_PMSYNC_GPIO_X_SELECTION { + TsGpioC, + TsGpioD, + MaxTsGpioPin +}; + +/** + This structure supports an external memory thermal sensor (TS-on-DIMM or TS-on-Board). +**/ +typedef struct { + /** + This will enable PCH memory throttling. + While this policy is enabled, must also enable EnableExtts in SA policy. + 0: Disable; 1: Enable + **/ + UINT32 Enable : 1; + UINT32 RsvdBits0 : 31; + /** + GPIO_C and GPIO_D selection for memory throttling. + It's strongly recommended to choose GPIO_C and GPIO_D for memory throttling feature, + and route EXTTS# accordingly. + **/ + TS_GPIO_PIN_SETTING TsGpioPinSetting[2]; +} PCH_MEMORY_THROTTLING; + +/** + The PCH_THERMAL_CONFIG block describes the expected configuration of the PCH for Thermal. +**/ +typedef struct { + /** + This field reports the status of Thermal Device. When it reports ThermalDevice + is disabled, the PCI configuration space of thermal device will be hidden by + setting TCFD and PCR[PSF2] TRH PCIEN[8] prior to end of POST. + **/ + UINT32 ThermalDeviceEnable : 2; ///< 0: Disabled, 1: Enabled in PCI mode, 2: Enabled in ACPI mode + UINT32 TsmicLock : 1; ///< This locks down "SMI Enable on Alert Thermal Sensor Trip". 0: Disabled, 1: Enabled. + UINT32 RsvdBits0 : 29; + /** + This field decides the settings of Thermal throttling. When the Suggested Setting + is enabled, PCH RC will use the suggested representative values. + **/ + PCH_THERMAL_THROTTLING ThermalThrottling; + /** + Memory Thermal Management settings + **/ + PCH_MEMORY_THROTTLING MemoryThrottling; + /** + This field decides the temperature, default is zero. + - 0x00 is the hottest + - 0x1FF is the lowest temperature + **/ + UINT16 PchHotLevel; + UINT8 Rsvd0[6]; +} PCH_THERMAL_CONFIG; + +enum PCH_THERMAL_DEVICE { + PchThermalDeviceDisabled, + PchThermalDeviceEnabledPci, + PchThermalDeviceEnabledAcpi, + PchThermalDeviceAuto +}; + +// +// ---------------------- Power Management Config -------------------------- +// +/** + This PCH_POWER_RESET_STATUS Specifies which Power/Reset bits need to be cleared by the PCH Init Driver. + Usually platform drivers take care of these bits, but if not, let PCH Init driver clear the bits. +**/ +typedef struct { + UINT32 MeWakeSts : 1; ///< Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable. + UINT32 MeHrstColdSts : 1; ///< Clear the ME_HRST_COLD_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable. + UINT32 MeHrstWarmSts : 1; ///< Clear the ME_HRST_WARM_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable. + UINT32 MeHostPowerDn : 1; ///< Clear the ME_HOST_PWRDN bit in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable. + UINT32 WolOvrWkSts : 1; ///< Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 27; +} PCH_POWER_RESET_STATUS; + +/** + This PCH_GBL2HOST_EN specifes enable bits related to the "Convert Global Resets to Host Resets" (G2H) feature +**/ +typedef union { + struct { + UINT32 G2H_FEA : 1; ///< G2H Feature Enable: 0: Disable; 1: Enable. + UINT32 LTRESET : 1; ///< LT RESET G2H Enable: 0: Disable; 1: Enable. + UINT32 PMCGBL : 1; ///< PMC FW-Initiated Global Reset G2H Enable: 0: Disable; 1: Enable. + UINT32 CPUTHRM : 1; ///< CPU Thermal Trip G2H Enable: 0: Disable; 1: Enable. + UINT32 PCHTHRM : 1; ///< PCH Internal Thermal Trip G2H Enable: Disable; 1: Enable. + UINT32 PBO : 1; ///< Power Button Override G2H Enable: 0: Disable; 1: Enable. + UINT32 MEPBO : 1; ///< ME-Initiated Power Button Override G2H: 0: Disable; 1: Enable. + UINT32 MEWDT : 1; ///< ME FW Watchdog Timer G2H Enable: 0: Disable; 1: Enable. + UINT32 MEGBL : 1; ///< ME-Initiated Global Reset G2H Enable: Disable; 1: Enable. + UINT32 CTWDT : 1; ///< CPU Thermal Watchdog Timer G2H Enable: Disable; 1: Enable. + UINT32 PMCWDT : 1; ///< PMC FW Watchdog Timer G2H Enable: Disable; 1: Enable. + UINT32 ME_UERR : 1; ///< ME Uncorrectable Error G2H Enable: Disable; 1: Enable. + UINT32 SYSPWR : 1; ///< SYS_PWROK Failure G2H Enable: Disable; 1: Enable. + UINT32 OCWDT : 1; ///< Over-Clocking WDT G2H Enable: Disable; 1: Enable. + UINT32 PMC_PARERR : 1; ///< PMC Parity Error G2H Enable: 0: Disable; 1: Enable. + UINT32 Reserved : 1; ///< Reserved + UINT32 IEPBO : 1; ///< IE-Initiated Power Button Override G2H: 0: Disable; 1: Enable. + UINT32 IEWDT : 1; ///< IE FW Watchdog Timer G2H Enable: 0: Disable; 1: Enable. + UINT32 IEGBLN : 1; ///< IE-Initiated Global Reset G2H Enable: 0: Disable; 1: Enable. + UINT32 IE_UERRN : 1; ///< IE Uncorrectable Error G2H Enable: 0: Disable; 1: Enable. + UINT32 ACRU_ERR_2H_EN : 1; ///< AC RU Error G2H Enable: 0: Disable; 1: Enable. + } Bits; + UINT32 Value; +} PCH_GBL2HOST_EN; + +/** + This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events. +**/ +typedef struct { + /** + Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. + When set to 1, this bit blocks wake events from PME_B0_STS in S5, regardless of the state of PME_B0_EN. + When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. 0: Disable; 1: Enable. + **/ + UINT32 PmeB0S5Dis : 1; + UINT32 WolEnableOverride : 1; ///< Corresponds to the "WOL Enable Override" bit in the General PM Configuration B (GEN_PMCON_B) register. 0: Disable; 1: Enable. + UINT32 Gp27WakeFromDeepSx : 1; ///< @deprecated + UINT32 PcieWakeFromDeepSx : 1; ///< Determine if enable PCIe to wake from deep Sx. 0: Disable; 1: Enable. + UINT32 WoWlanEnable : 1; ///< Determine if WLAN wake from Sx, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register. 0: Disable; 1: Enable. + UINT32 WoWlanDeepSxEnable : 1; ///< Determine if WLAN wake from DeepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register. 0: Disable; 1: Enable. + UINT32 LanWakeFromDeepSx : 1; ///< Determine if enable LAN to wake from deep Sx. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 25; +} PCH_WAKE_CONFIG; + +typedef enum { + PchDeepSxPolDisable, + PchDpS5BatteryEn, + PchDpS5AlwaysEn, + PchDpS4S5BatteryEn, + PchDpS4S5AlwaysEn, + PchDpS3S4S5BatteryEn, + PchDpS3S4S5AlwaysEn +} PCH_DEEP_SX_CONFIG; + +typedef enum { + PchSlpS360us, + PchSlpS31ms, + PchSlpS350ms, + PchSlpS32s +} PCH_SLP_S3_MIN_ASSERT; + +typedef enum { + PchSlpS4PchTime, ///< The time defined in PCH EDS Power Sequencing and Reset Signal Timings table + PchSlpS41s, + PchSlpS42s, + PchSlpS43s, + PchSlpS44s +} PCH_SLP_S4_MIN_ASSERT; + +typedef enum { + PchSlpSus0ms, + PchSlpSus500ms, + PchSlpSus1s, + PchSlpSus4s +} PCH_SLP_SUS_MIN_ASSERT; + +typedef enum { + PchSlpA0ms, + PchSlpA4s, + PchSlpA98ms, + PchSlpA2s +} PCH_SLP_A_MIN_ASSERT; + +typedef enum { + PchPmGrPfetDur1us, + PchPmGrPfetDur2us, + PchPmGrPfetDur5us, + PchPmGrPfetDur20us +} PCH_PM_GR_PFET_DUR; + +/** + The PCH_PM_CONFIG block describes expected miscellaneous power management settings. + The PowerResetStatusClear field would clear the Power/Reset status bits, please + set the bits if you want PCH Init driver to clear it, if you want to check the + status later then clear the bits. +**/ +typedef struct { + /** + Specify which Power/Reset bits need to be cleared by + the PCH Init Driver. + Usually platform drivers take care of these bits, but if + not, let PCH Init driver clear the bits. + **/ + PCH_POWER_RESET_STATUS PowerResetStatusClear; + PCH_WAKE_CONFIG WakeConfig; ///< Specify Wake Policy + PCH_DEEP_SX_CONFIG PchDeepSxPol; ///< Deep Sx Policy. Default is PchDeepSxPolDisable. + PCH_SLP_S3_MIN_ASSERT PchSlpS3MinAssert; ///< SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. + PCH_SLP_S4_MIN_ASSERT PchSlpS4MinAssert; ///< SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. + PCH_SLP_SUS_MIN_ASSERT PchSlpSusMinAssert; ///< SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. + PCH_SLP_A_MIN_ASSERT PchSlpAMinAssert; ///< SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. + /** + This member describes whether or not the PCI ClockRun feature of PCH should + be enabled. 0: Disable; 1: Enable + **/ + UINT32 PciClockRun : 1; + UINT32 SlpStrchSusUp : 1; ///< 0: Disable; 1: Enable SLP_X Stretching After SUS Well Power Up + /** + Enable/Disable SLP_LAN# Low on DC Power. 0: Disable; 1: Enable. + Configure On DC PHY Power Diable according to policy SlpLanLowDc. + When this is enabled, SLP_LAN# will be driven low when ACPRESENT is low. + This indicates that LAN PHY should be powered off on battery mode. + This will override the DC_PP_DIS setting by WolEnableOverride. + **/ + UINT32 SlpLanLowDc : 1; + /** + PCH power button override period. + 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s + Default is 0: 4s + **/ + UINT32 PwrBtnOverridePeriod : 3; + /** + (Test) + Disable/Enable PCH to CPU enery report feature. 0: Disable; 1: Enable. + Enery Report is must have feature. Wihtout Energy Report, the performance report + by workloads/benchmarks will be unrealistic because PCH's energy is not being accounted + in power/performance management algorithm. + If for some reason PCH energy report is too high, which forces CPU to try to reduce + its power by throttling, then it could try to disable Energy Report to do first debug. + This might be due to energy scaling factors are not correct or the LPM settings are not + kicking in. + **/ + UINT32 DisableEnergyReport : 1; + /** + When set to Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. + When set to Enable, PCH will not pull down AC_PRESENT. + This setting is ignored when DeepSx is not supported. + Default is 0:Disable + **/ + UINT32 DisableDsxAcPresentPulldown : 1; + /** + (Test) + When set to true, this bit disallows Host reads to PMC XRAM. + BIOS must set this bit (to disable and lock the feature) prior to passing control to OS + 0:Disable, 1:Enable + **/ + UINT32 PmcReadDisable : 1; + /** + This determines the type of reset issued during the capsule update process by UpdateCapsule(). + The default is 0:S3 Resume, 1:Warm reset. + **/ + UINT32 CapsuleResetType : 1; + /** + Power button native mode disable. + While FALSE, the PMC's power button logic will act upon the input value from the GPIO unit, as normal. + While TRUE, this will result in the PMC logic constantly seeing the power button as de-asserted. + Default is FALSE. + **/ + UINT32 DisableNativePowerButton : 1; + /** + Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. + When set to one SLP_S0# will be asserted in idle state. + When set to zero SLP_S0# will not toggle and is always drivern high. + 0:Disable, 1:Enable + + Warning: In SKL PCH VCCPRIM_CORE must NOT be reduced based on SLP_S0# being asserted. + If a platform is using SLP_S0 to lower PCH voltage the below policy must be disabled. + **/ + UINT32 SlpS0Enable : 1; + UINT32 DirtyWarmReset : 1; ///< DirtyWarmReset enable + UINT32 StallDirtyWarmReset : 1; ///< Stall during DWR + UINT32 GrPfetDurOnDef : 2; ///< Global Reset PFET duration + UINT32 Dwr_MeResetPrepDone : 1; ///< ME Reset Prep Done + UINT32 Dwr_IeResetPrepDone : 1; ///< IE Reset Prep Done + UINT32 Dwr_BmcRootPort : 8; ///< Root port where BMC is connected to + UINT32 RsvdBits0 : 6; ///< @todo ADD DESCRIPTION + + PCH_GBL2HOST_EN PchGbl2HostEn; + /** + Reset Power Cycle Duration could be customized in the unit of second. Please refer to EDS + for all support settings. PCH HW default is 4 seconds, and range is 1~4 seconds, where + 0 is default, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 seconds. + And make sure the setting correct, which never less than the following register. + - GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH + - GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH + - PWRM_CFG.SLP_A_MIN_ASST_WDTH + - PWRM_CFG.SLP_LAN_MIN_ASST_WDTH + **/ + UINT8 PchPwrCycDur; + /** + Specifies the Pcie Pll Spread Spectrum Percentage + The value of this policy is in 1/10th percent units. + Valid spread range is 0-20. A value of 0xFF is reserved for AUTO. + A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0% + The default is 0xFF: AUTO - No BIOS override. + **/ + UINT8 PciePllSsc; + UINT8 Rsvd0[2]; ///< Reserved bytes + +} PCH_PM_CONFIG; + +// +// ---------------------------- DMI Config ----------------------------- +// + +/// +/// The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI. +/// +typedef struct { + /** + 0: Disable; 1: Enable ASPM on PCH side of the DMI Link. + While DmiAspm is enabled, DMI ASPM will be set to Intel recommended value. + **/ + UINT32 DmiAspm : 1; + UINT32 PwrOptEnable : 1; ///< 0: Disable; 1: Enable DMI Power Optimizer on PCH side. + BOOLEAN DmiStopAndScreamEnable : 1; + UINT32 DmiLinkDownHangBypass : 1; + UINT32 Rsvdbits : 29; + UINT32 Rsvd0[6]; ///< Reserved bytes +} PCH_DMI_CONFIG; + +// +// --------------------------- Serial IRQ Config ------------------------------ +// + +typedef enum { + PchQuietMode, + PchContinuousMode +} PCH_SIRQ_MODE; +/// +/// Refer to PCH EDS for the details of Start Frame Pulse Width in Continuous and Quiet mode +/// +typedef enum { + PchSfpw4Clk, + PchSfpw6Clk, + PchSfpw8Clk +} PCH_START_FRAME_PULSE; + +/// +/// The PCH_LPC_SIRQ_CONFIG block describes the expected configuration of the PCH for Serial IRQ. +/// +typedef struct { + UINT32 SirqEnable : 1; ///< Determines if enable Serial IRQ. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 31; ///< Reserved bits + PCH_SIRQ_MODE SirqMode; ///< Serial IRQ Mode Select. 0: quiet mode 1: continuous mode. + PCH_START_FRAME_PULSE StartFramePulse; ///< Start Frame Pulse Width. Default is PchSfpw4Clk. + UINT32 Rsvd0; ///< Reserved bytes +} PCH_LPC_SIRQ_CONFIG; + + +// +// --------------------------- Port 61h Emulation in SMM ------------------------------ +// +/** + This structure is used for the emulation feature for Port61h read. The port is trapped + and the SMI handler will toggle bit4 according to the handler's internal state. +**/ +typedef struct { + UINT32 Enable : 1; ///< 0: Disable; 1: Enable the emulation + UINT32 RsvdBits0 : 31; ///< Reserved bits +} PCH_PORT61H_SMM_CONFIG; + +// +// --------------------- Interrupts Config ------------------------------ +// +typedef enum { + PchNoInt, ///< No Interrupt Pin + PchIntA, + PchIntB, + PchIntC, + PchIntD +} PCH_INT_PIN; + +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} PCH_DEVICE_INTERRUPT_CONFIG; + +#define PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices +#define PCH_MAX_PXRC_CONFIG 8 ///< Number of PXRC registers in ITSS + +/// +/// The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH. +/// +typedef struct { + UINT8 NumOfDevIntConfig; ///< Number of entries in DevIntConfig table + UINT8 Rsvd0[2]; ///< Reserved bytes, align to multiple 4. + PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG]; ///< Array which stores PCH devices interrupts settings + UINT8 PxRcConfig[PCH_MAX_PXRC_CONFIG]; ///< Array which stores interrupt routing for 8259 controller + UINT8 GpioIrqRoute; ///< Interrupt routing for GPIO. Default is 14. + UINT8 SciIrqSelect; ///< Interrupt select for SCI. Default is 9. + UINT8 TcoIrqSelect; ///< Interrupt select for TCO. Default is 9. + UINT8 TcoIrqEnable; ///< Enable IRQ generation for TCO. 0: Disable; 1: Enable. + UINT8 ShutdownPolicySelect; ///< Shutdown mode 0: PCH will drive INIT#; 1: PCH will drive PLTRST# active +} PCH_INTERRUPT_CONFIG; + +// +// --------------------- TraceHub Config ------------------------------ +// +/// +/// The PCH_TRACE_HUB_CONFIG block describes TraceHub settings for PCH. +/// +typedef struct { + TRACE_HUB_CONFIG TraceHub; + UINT32 AetEnableMode : 2; + UINT32 PchTraceHubHide : 1; +} PCH_TRACE_HUB_CONFIG; + + +// +// ------------------- CIO2 FLIS registers Config -------------------- +// + +/// +/// The PCH_SKYCAM_CIO2_FLS_CONFIG block describes SkyCam CIO2 FLS registers configuration. +/// +typedef struct { + UINT32 PortATrimEnable : 1; ///< 0: Disable; 1: Enable - Enable Port A Clk Trim + UINT32 PortBTrimEnable : 1; ///< 0: Disable; 1: Enable - Enable Port B Clk Trim + UINT32 PortCTrimEnable : 1; ///< 0: Disable; 1: Enable - Enable Port C Clk Trim + UINT32 PortDTrimEnable : 1; ///< 0: Disable; 1: Enable - Enable Port D Clk Trim + UINT32 PortACtleEnable : 1; ///< 0: Disable; 1: Enable - Enable Port A Ctle + UINT32 PortBCtleEnable : 1; ///< 0: Disable; 1: Enable - Enable Port B Ctle + UINT32 PortCDCtleEnable : 1; ///< 0: Disable; 1: Enable - Enable Port C/D Ctle + UINT32 RsvdBits0 : 25; + + UINT32 PortACtleCapValue : 4; /// Port A Ctle Cap Value + UINT32 PortBCtleCapValue : 4; /// Port B Ctle Cap Value + UINT32 PortCDCtleCapValue : 4; /// Port C/D Ctle Cap Value + UINT32 PortACtleResValue : 5; /// Port A Ctle Res Value + UINT32 PortBCtleResValue : 5; /// Port B Ctle Res Value + UINT32 PortCDCtleResValue : 5; /// Port C/D Ctle Res Value + UINT32 RsvdBits1 : 5; + + UINT32 PortAClkTrimValue : 4; /// Port A Clk Trim Value + UINT32 PortBClkTrimValue : 4; /// Port B Clk Trim Value + UINT32 PortCClkTrimValue : 4; /// Port C Clk Trim Value + UINT32 PortDClkTrimValue : 4; /// Port D Clk Trim Value + UINT32 PortADataTrimValue : 16; /// Port A Data Trim Value + + UINT32 PortBDataTrimValue : 16; /// Port B Data Trim Value + UINT32 PortCDDataTrimValue : 16; /// Port C/D Data Trim Value + +} PCH_SKYCAM_CIO2_FLS_CONFIG; +// +// ---------------------------- USB Config ----------------------------- +// + +/// +/// The location of the USB connectors. This information is use to decide eye diagram tuning value for Usb 2.0 motherboard trace. +/// +enum PCH_USB_PORT_LOCATION{ + PchUsbPortLocationBackPanel = 0, + PchUsbPortLocationFrontPanel, + PchUsbPortLocationDock, + PchUsbPortLocationMiniPciE, + PchUsbPortLocationFlex, + PchUsbPortLocationInternalTopology, + PchUsbPortLocationSkip, + PchUsbPortLocationMax +}; + +/** + This structure configures per USB2 port physical settings. + It allows to setup the port location and port length, and configures the port strength accordingly. +**/ +typedef struct { + UINT32 Enable : 1; ///< 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 31; ///< Reserved bits + /** + These members describe the specific over current pin number of USB 2.0 Port N. + It is SW's responsibility to ensure that a given port's bit map is set only for + one OC pin Description. USB2 and USB3 on the same combo Port must use the same + OC pin (see: USB_OVERCURRENT_PIN). + **/ + UINT8 OverCurrentPin; + UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4. + USB2_PHY_PARAMETERS Afe; ///< USB2 AFE settings + UINT32 Rsvd1[1]; ///< Reserved bytes +} PCH_USB20_PORT_CONFIG; + +/** + This structure describes whether the USB3 Port N of PCH is enabled by platform modules. +**/ +typedef struct { + UINT32 Enable : 1; ///< 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 31; ///< Reserved bits + /** + These members describe the specific over current pin number of USB 3.0 Port N. + It is SW's responsibility to ensure that a given port's bit map is set only for + one OC pin Description. USB2 and USB3 on the same combo Port must use the same + OC pin (see: USB_OVERCURRENT_PIN). + **/ + UINT8 OverCurrentPin; + UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4 + + UINT32 HsioTxDeEmphEnable : 1; ///< Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment, 0: Disable; 1: Enable. + /** + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2deemph3p5) + HSIO_TX_DWORD5[21:16] + Default = 29h (approximately -3.5dB De-Emphasis) + **/ + UINT32 HsioTxDeEmph : 6; + + UINT32 HsioTxDownscaleAmpEnable : 1; ///< Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, 0: Disable; 1: Enable. + /** + USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin) + HSIO_TX_DWORD8[21:16] + Default = 00h + **/ + UINT32 HsioTxDownscaleAmp : 6; + + UINT32 RsvdBits1 : 18; ///< Reserved bits + UINT32 Rsvd1[1]; ///< Reserved bytes +} PCH_USB30_PORT_CONFIG; + +#define PCH_XHCI_MODE_OFF 0 +#define PCH_XHCI_MODE_ON 1 + +/** + These members describe some settings which are related to the SSIC ports. +**/ +typedef struct { + /** + 0: Disable; 1: Enable SSIC support. + **/ + UINT32 Enable : 1; + UINT32 RsvdBits1 : 31; +} PCH_XHCI_SSIC_PORT; +/** + These members describe some settings which are related to the SSIC ports. +**/ +typedef struct { + PCH_XHCI_SSIC_PORT SsicPort[PCH_XHCI_MAX_SSIC_PORT_COUNT]; +} PCH_SSIC_CONFIG; + +/** + The PCH_XDCI_CONFIG block describes the configurations + of the xDCI Usb Device controller. +**/ +typedef struct { + /** + This member describes whether or not the xDCI controller should be enabled. + 0: Disable; 1: Enable. + **/ + UINT32 Enable : 1; + UINT32 RsvdBits0 : 31; ///< Reserved bits +} PCH_XDCI_CONFIG; + +/** + This member describes the expected configuration of the PCH USB controllers, + Platform modules may need to refer Setup options, schematic, BIOS specification + to update this field. + The Usb20OverCurrentPins and Usb30OverCurrentPins field must be updated by referring + the schematic. +**/ +typedef struct { + /** + This feature intends to reduce the necessary initialization time for USB HC + and devices on root ports. It is assembled by PCHInit drivers in PEI and DXE phase. + In PEI phase, the feature resets all USB HCs on PCH bus, including Intel EHCI + and XHCI. After reset USB HC, continue the system initialization without waiting + for the USB XHC reset ready. After running to DXE phase, the feature resets + those USB devices installed on each USB HC root port in parallel, including + any non USB3 speed devices on XHCI root port if XHCI is enabled. + For USB3 protocol root port, USB3 speed devices will be advanced to + enable state if link training succeeds after XHC reset. + + UsbPrecondition = Enable , Force USB Init happen in PEI as part of 2Sec Fast Boot bios optimization. + UsbPrecondition = Disable, USB Init happen in DXE just like traditionally where it happen. + Remark: With Precondition Enabled some USB2 devices which are not compliant with usb2 specification + are not being detected if installed in the system during S4/S5. + + + 0: Disable; 1: Enable. + **/ + UINT32 UsbPrecondition : 1; + /** + This policy will disable XHCI compliance mode on all ports. Complicance Mode should be default enabled. + For the platform that support USB Type-C, it can disable Compliance Mode, and enable Compliance Mode when testing. + 0:Disable , 1: Enable + **/ + UINT32 DisableComplianceMode : 1; + // Following option is now exposed since there are no restricted registers used. + UINT32 XhciOcMapEnabled : 1; ///< 0: To disable OC mapping for USB XHCI ports 1: Set Xhci OC registers, Set Xhci OCCDone bit, XHCI Access Control Bit. + UINT32 XhciWakeOnUsb : 1; ///< 0: To disable Wake on USB connect/Disconnect 1: Enables Wake on USB connect/disconnect event. + UINT32 XhciDisMSICapability : 1; + UINT32 RsvdBits0 : 27; ///< Reserved bits + + /** + These members describe whether the USB2 Port N of PCH is enabled by platform modules. + Panel and Dock are used to describe the layout of USB port. Panel is only available for Desktop PCH. + Dock is only available for Mobile LPT. + **/ + PCH_USB20_PORT_CONFIG PortUsb20[PCH_MAX_USB2_PORTS]; + /** + These members describe whether the USB3 Port N of PCH is enabled by platform modules. + **/ + PCH_USB30_PORT_CONFIG PortUsb30[PCH_MAX_USB3_PORTS]; + /** + This member describes whether or not the xDCI controller should be enabled. + **/ + PCH_XDCI_CONFIG XdciConfig; + /** + These members describe some settings which are related to the SSIC ports. + **/ + PCH_SSIC_CONFIG SsicConfig; + + UINT32 Rsvd0[6]; ///< Reserved bytes +} PCH_USB_CONFIG; + +// +// --------------------------- Flash Protection Range Registers ------------------------------ +// +/** + The PCH provides a method for blocking writes and reads to specific ranges + in the SPI flash when the Protected Ranges are enabled. + PROTECTED_RANGE is used to specify if flash protection are enabled, + the write protection enable bit and the read protection enable bit, + and to specify the upper limit and lower base for each register + Platform code is responsible to get the range base by PchGetSpiRegionAddresses routine, + and set the limit and base accordingly. +**/ +typedef struct { + UINT32 WriteProtectionEnable : 1; ///< Write or erase is blocked by hardware. 0: Disable; 1: Enable. + UINT32 ReadProtectionEnable : 1; ///< Read is blocked by hardware. 0: Disable; 1: Enable. + UINT32 RsvdBits : 30; ///< Reserved + /** + The address of the upper limit of protection + This is a left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison + **/ + UINT16 ProtectedRangeLimit; + /** + The address of the upper limit of protection + This is a left shifted address by 12 bits with address bits 11:0 are assumed to be 0 + **/ + UINT16 ProtectedRangeBase; +} PROTECTED_RANGE; + +typedef struct { + PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; +} PCH_FLASH_PROTECTION_CONFIG; + +// +// --------------------- WatchDog (WDT) Configuration ------------------------------ +// +/** + This policy clears status bits and disable watchdog, then lock the + WDT registers. + while WDT is designed to be disabled and locked by Policy, + bios should not enable WDT by WDT PPI. In such case, bios shows the + warning message but not disable and lock WDT register to make sure + WDT event trigger correctly. +**/ +typedef struct { + UINT32 DisableAndLock : 1; ///< (Test) Set 1 to clear WDT status, then disable and lock WDT registers. 0: Disable; 1: Enable. + UINT32 RsvdBits : 31; +} PCH_WDT_CONFIG; + +// +// --------------------- P2SB Configuration ------------------------------ +// +/** + This structure contains the policies which are related to P2SB device. +**/ +typedef struct { + /** + (Test) + This unlock the SBI lock bit to allow SBI after post time. 0: Disable; 1: Enable. + NOTE: Do not set this policy "SbiUnlock" unless necessary. + **/ + UINT32 SbiUnlock : 1; + /** + (Test) + The PSF registers will be locked before 3rd party code execution. + This policy unlock the PSF space. 0: Disable; 1: Enable. + NOTE: Do not set this policy "PsfUnlock" unless necessary. + **/ + UINT32 PsfUnlock : 1; + /** + Debug + The P2SB PCIe device will be hidden at end of PEI stage. + This policy reveal P2SB PCIe device at end of EXE. 0: Disable (hidden); 1: Enable (visible). + NOTE: Do not set this policy "P2SbReveal" unless necessary. + **/ + UINT32 P2SbReveal : 1; + UINT32 RsvdBits : 29; +} PCH_P2SB_CONFIG; + +// +// --------------------- DCI Configuration ------------------------------ +// +/** + This structure contains the policies which are related to Direct Connection Interface (DCI). +**/ +typedef struct { + /** + (Test) DCI enable (HDCIEN bit) + when Enabled, allow DCI to be enabled. When Disabled, the Host control is not enabling DCI feature. + BIOS provides policy to enable or disable DCI, and user would be able to use BIOS option to change this policy. + The user changing the setting from disable to enable, is taken as a consent from the user to enable this DCI feature. + 0:Disabled; 1:Enabled + **/ + UINT32 DciEn : 1; + /** + (Test) When set to Auto detect mode, it detects DCI being connected during BIOS post time and enable DCI. + Else it disable DCI. This policy only apply when DciEn is disabled. + NOTE: this policy should not be visible to end customer. + 0: Disable AUTO mode, 1: Enable AUTO mode + **/ + UINT32 DciAutoDetect : 1; + UINT32 RsvdBits : 30; ///< Reserved bits +} PCH_DCI_CONFIG; + +// +// --------------------- LPC Configuration ------------------------------ +// +/** + This structure contains the policies which are related to LPC. +**/ +typedef struct { + /** + Enhance the port 8xh decoding. + Original LPC only decodes one byte of port 80h, with this enhancement LPC can decode word or dword of port 80h-83h. + @note: this will occupy one LPC generic IO range register. While this is enabled, read from port 80h always return 0x00. + 0: Disable, 1: Enable + **/ + UINT32 EnhancePort8xhDecoding : 1; + UINT32 RsvdBits : 30; ///< Reserved bits +} PCH_LPC_CONFIG; + +// +// --------------------- SPI Configuration ------------------------------ +// +/** + This structure contains the policies which are related to SPI. +**/ +typedef struct { + /** + Force to show SPI controller. + 0: FALSE, 1: TRUE + NOTE: For Windows OS, it MUST BE false. It's optional for other OSs. + **/ + UINT32 ShowSpiController : 1; + UINT32 RsvdBits : 31; ///< Reserved bits +} PCH_SPI_CONFIG; + +// +// --------------------------------------------------------------------- +// + +/** + PCH Policy revision number + Any backwards compatible changes to this structure will result in an update in the revision number +**/ +#define PCH_POLICY_REVISION 15 + +/** + The PCH Policy allows the platform code to publish a set of + configuration information that the PCH drivers will use to configure the PCH hardware. + The Revision field is used to accommodate backward compatible changes to the PPI/protocol. + The Revision should be initialized to PCH_POLICY_REVISION_X + by the PPI producer. + The BusNumber field is used for platform to assign Bus number with multiple instances. + + All reserved/unused fields must be initialized with zeros. +**/ +struct _PCH_POLICY { + /** + This member specifies the revision of the PCH policy PPI. This field is used to + indicate backwards compatible changes to the protocol. Platform code that produces + this PPI must fill with the correct revision value for the PCH reference code + to correctly interpret the content of the PPI fields. + + Revision 1: Original version + - Add DciAutoDetect policy in PCH_GENERAL_CONFIG. + - Add SbiUnlock policy in PCH_P2SB_CONFIG. + - Add the following policies in PCH_ISH_CONFIG: + - SpiGpioAssign + - Uart0GpioAssign + - Uart1GpioAssign + - I2c0GpioAssign + - I2c1GpioAssign + - I2c2GpioAssign + - Gp0GpioAssign + - Gp1GpioAssign + - Gp2GpioAssign + - Gp3GpioAssign + - Gp4GpioAssign + - Gp5GpioAssign + - Gp6GpioAssign + - Gp7GpioAssign + - Add ClkReqSupported and ClkReqDetect in PCH_PCIE_ROOT_PORT_CONFIG. + - Add the following in PCH_SKYCAM_CIO2_CONFIG + - SkyCamPortATermOvrEnable + - SkyCamPortBTermOvrEnable + - SkyCamPortCTermOvrEnable + - SkyCamPortDTermOvrEnable + - Add UartHwFlowCtrl in PCH_SERIAL_IO + - Move DciEn and DciAutoDetect to PCH_DCI_CONFIG + + + + Revision 2: Updated version + - Add Enable policy in PCH_SSIC_CONFIG + - Deprecated Target Debugger option of EnableMode in PCH_TRACE_HUB_CONFIG + - Deprecated the following policies in PCH_TRACE_HUB_CONFIG + - MemReg0WrapEnable + - MemReg1WrapEnable + - TraceDestination + - PtiMode + - PtiSpeed + - PtiTraining + - Deprecated the Usb3PinsTermination and ManualModeUsb30PerPinEnable in PCH_XHCI_CONFIG + - Redefine the Enable policy in PCH_HPET_CONFIG + - Add EnhancePort8xhDecoding in PCH_LPC_CONFIG + - Add PsfUnlock in PCH_P2SB_CONFIG + - Add AllowNoLtrIccPllShutdown in PCH_PCIE_CONFIG + - Add PdtUnlock in PCH_ISH_CONFIG + - Remove PwrmBase from policy since the base address is predefined. + - Add DspEndpointDmic, DspEndpointBluetooth, DspEndpointI2s in PCH_HDAUDIO_CONFIG + - Add Gen3EqPh3Method abd EqPh3LaneParam in PCH_PCIE_ROOT_PORT_CONFIG/PCH_PCIE_CONFIG + - Remove SlotImplemented and PmeInterrupt from PCH_PCIE_ROOT_PORT_CONFIG + + + + Revision 3: Updated version + - Add PwrBtnOverridePeriod policy in PCH_PM_CONFIG + - Add USB20_AFE in PCH_USB20_PORT_CONFIG + - Add ClkReqSupported in PCH_LAN_CONFIG + + + + Revision 4: Updated version + - Add DeviceResetPad and DeviceResetPadActiveHigh in PCH_PCIE_ROOT_PORT_CONFIG + + + Revision 5: Updated version + - Deprecated ScsSdioMode in PCH_SCS_CONFIG + - Deprecated PchScsSdioMode (PCH_SCS_DEV_SD_MODE enum) for ScsSdSwitch in PCH_SCS_CONFIG + - Add HSIO RX and TX EQ policy for PCIe and SATA + - Add ComplianceTestMode in PCH_PCIE_CONFIG + + Revision 6: Updated version + - Add DisableEnergyReport in PCH_PM_CONFIG + + + Revision 7: Updated version + - Deprecated Enabled as Acpi device option of DeviceEnable in PCH_SKYCAM_CIO2_CONFIG + - Add PCH_SKYCAM_CIO2_FLS_CONFIG with the following elements: + - PortACtleEnable + - PortBCtleEnable + - PortCCtleEnable + - PortDCtleEnable + - PortACtleCapValue + - PortBCtleCapValue + - PortCCtleCapValue + - PortDCtleCapValue + - PortACtleResValue + - PortBCtleResValue + - PortCCtleResValue + - PortDCtleResValue + - PortATrimEnable + - PortBTrimEnable + - PortCTrimEnable + - PortDTrimEnable + - PortADataTrimValue + - PortBDataTrimValue + - PortCDataTrimValue + - PortDDataTrimValue + - PortAClkTrimValue + - PortBClkTrimValue + - PortCClkTrimValue + - PortDClkTrimValue + - Rename and reorder the policies for better understanding. + - HsioTxOutDownscaleAmpAd3GbsEnable to HsioTxGen1DownscaleAmpEnable + - HsioTxOutDownscaleAmpAd6GbsEnable to HsioTxGen2DownscaleAmpEnable + - HsioTxOutDownscaleAmpAd3Gbs to HsioTxGen2DownscaleAmp + - HsioTxOutDownscaleAmpAd6Gbs to HsioTxGen2DownscaleAmp + - Update SerialIo DevMode default to PCI mode. + + + Revision 8: Updated version + - Deprecate GP27WakeFromDeepSx and add LanWakeFromDeepSx to align EDS naming + - Add ShowSpiController policy and PCH_SPI_CONFIG. + - Add DspUaaCompliance in PCH_HDAUDIO_CONFIG + - Add PchPcieEqHardware support in PCH_PCIE_EQ_METHOD + + + Revision 9: Updated version + - Add DebugUartNumber and EnableDebugUartAfterPost in PCH_SERIAL_IO_CONFIG + - Add DetectTimeoutMs in PCH_PCIE_CONFIG + - Add PciePllSsc in PCH_PM_CONFIG + + + Revision 10: Updated version + - Add HsioTxDeEmph in PCH_USB30_PORT_CONFIG + - Add HsioTxDownscaleAmp in PCH_USB30_PORT_CONFIG + - Add HsioTxDeEmphEnable in PCH_USB30_PORT_CONFIG + - Add HsioTxDownscaleAmpEnable in PCH_USB30_PORT_CONFIG + + - Deprecated PCH_SATA_PORT_CONFIG.HsioRxEqBoostMagAdEnable + - Deprecated PCH_SATA_PORT_CONFIG.HsioRxEqBoostMagAd + - Deprecated PCH_SATA_PORT_CONFIG.HsioTxGen1DownscaleAmpEnable + - Deprecated PCH_SATA_PORT_CONFIG.HsioTxGen1DownscaleAmp + - Deprecated PCH_SATA_PORT_CONFIG.HsioTxGen2DownscaleAmpEnable + - Deprecated PCH_SATA_PORT_CONFIG.HsioTxGen2DownscaleAmp + + - Add PCH_HSIO_SATA_CONFIG HsioSataConfig in PCH_POLICY + - Add HsioRxGen1EqBoostMagEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioRxGen1EqBoostMag in PCH_HSIO_SATA_PORT_LANE + - Add HsioRxGen2EqBoostMagEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioRxGen2EqBoostMag in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen1DeEmphEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen1DeEmph in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen2DeEmphEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen2DeEmph in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen3DeEmphEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen3DeEmph in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen3DownscaleAmpEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen3DownscaleAmp in PCH_HSIO_SATA_PORT_LANE + + - Add PCH_HSIO_PCIE_CONFIG HsioPcieConfig in PCH_POLICY + - Deprecated PCH_PCIE_ROOT_PORT_CONFIG.HsioRxSetCtleEnable + - Deprecated PCH_PCIE_ROOT_PORT_CONFIG.HsioRxSetCtle + - Add HsioRxSetCtleEnable in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioRxSetCtle in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen1DownscaleAmpEnable in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen1DownscaleAmp in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen2DownscaleAmpEnable in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen2DownscaleAmp in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen3DownscaleAmpEnable in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen3DownscaleAmp in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen1DeEmphEnable in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen1DeEmph in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen2DeEmph3p5Enable in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen2DeEmph3p5 in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen2DeEmph6p0Enable in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen2DeEmph6p0 in PCH_HSIO_PCIE_LANE_CONFIG + + - Add DisableDsxAcPresentPulldown in PCH_PM_CONFIG + - Add DynamicPowerGating in PCH_SMBUS_CONFIG + - Add ZpOdd in PCH_SATA_PORT_CONFIG + - Add Uptp and Dptp in PCH_PCIE_ROOT_PORT_CONFIG + - Add PCH_PCIE_CONFIG2 PcieConfig2 in PCH_POLICY + + + Revision 11: Updated version + - Add DisableComplianceMode in PCH_USB_CONFIG + + + Revision 12: Updated version + - Add PmcReadDisable in PCH_PM_CONFIG + - Add CapsuleResetType in PCH_PM_CONFIG + - Add RpFunctionSwap in PCH_PCIE_CONFIG + + + Revision 13: Update version + - Add DisableNativePowerButton in PCH_PM_CONFIG + - Add MaxPayload in PCH_PCIE_ROOT_PORT_CONFIG + - Add IDispCodecDisconnect in PCH_HDAUDIO_CONFIG + Revision 13a: Server updates + - Add HsioIcfgAdjLimitLoEnable + - Add HsioIcfgAdjLimitLo + - Add HsioSampOffstEvenErrSpEnable + - Add HsioSampOffstEvenErrSp + - Add HsioRemainingSamplerOffEnable + - Add HsioRemainingSamplerOff + - Add HsioVgaGainCal + in PCH_HSIO_PCIE_LANE_CONFIG + + **/ + UINT8 Revision; + + UINT8 Port80Route; ///< Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. + UINT16 AcpiBase; ///< Power management I/O base address. Default is 0x1800. + UINT32 Rsvd; + /// + /// PCH General configuration + /// + PCH_GENERAL_CONFIG PchConfig; + /// + /// This member describes PCI Express controller's related configuration. + /// + PCH_PCIE_CONFIG PcieConfig; + /** + SATA controller's related configuration. + SATA configuration that decides which Mode the SATA controller should operate in + and whether PCH SATA TEST mode is enabled. + **/ + PCH_SATA_CONFIG SataConfig; + /// + /// This member describes USB controller's related configuration. + /// + PCH_USB_CONFIG UsbConfig; + /** + This member describes IOAPIC related configuration. + Determines IO APIC ID and IO APIC Range. + **/ + PCH_IOAPIC_CONFIG IoApicConfig; + /// + /// This member describes HPET related configuration. + /// + PCH_HPET_CONFIG HpetConfig; + /// + /// This member describes the Intel HD Audio (Azalia) related configuration. + /// + PCH_HDAUDIO_CONFIG HdAudioConfig; + /// + /// LAN controller settings + /// + PCH_LAN_CONFIG LanConfig; + /// + /// This member describes SMBus related configuration. + /// + PCH_SMBUS_CONFIG SmbusConfig; + /// + /// This member describes LockDown related configuration. + /// + PCH_LOCK_DOWN_CONFIG LockDownConfig; + /// + /// This member describes Thermal related configuration. + /// + PCH_THERMAL_CONFIG ThermalConfig; + /// + /// This member describes miscellaneous platform power management configurations. + /// + PCH_PM_CONFIG PmConfig; + /// + /// This member describes DMI related configuration. + /// + PCH_DMI_CONFIG DmiConfig; + /// + /// This member describes the expected configuration of the PCH for Serial IRQ. + /// + PCH_LPC_SIRQ_CONFIG SerialIrqConfig; + /// + /// This member describes interrupt settings for PCH. + /// + PCH_INTERRUPT_CONFIG PchInterruptConfig; + /// + /// This member describes TraceHub settings for PCH. + /// + PCH_TRACE_HUB_CONFIG PchTraceHubConfig; + /// + /// This member describes the enabling of emulation for port 61h + /// + PCH_PORT61H_SMM_CONFIG Port61hSmmConfig; + /// + /// This member describes the Flash Protection related configuration + /// + PCH_FLASH_PROTECTION_CONFIG FlashProtectConfig; + /// + /// This member describes the sSata related configuration + /// + PCH_SATA_CONFIG sSataConfig; + /// + /// This member contains WDT enable configuration. + /// + PCH_WDT_CONFIG WdtConfig; + /// + /// This member contains P2SB configuration. + /// + PCH_P2SB_CONFIG P2sbConfig; + /// + /// This member contains DCI configuration. + /// + PCH_DCI_CONFIG DciConfig; + + /// + /// Platform specific common policies that used by several silicon components. + /// + /// + /// Temp Bus Number range available to be assigned to each root port and its downstream + /// devices for initialization of these devices before PCI Bus enumeration. + /// + UINT8 TempPciBusMin; + UINT8 TempPciBusMax; + /// + /// Temporary Memory Base Address for PCI devices to be used to initialize MMIO registers. + /// Minimum size is 2MB bytes + /// + UINT32 TempMemBaseAddr; + /// + /// This member contains LPC configuration. + /// + PCH_LPC_CONFIG LpcConfig; + /// + /// This member describes SkyCam CIO2 FLS registers configuration. + /// + PCH_SKYCAM_CIO2_FLS_CONFIG PchCio2FlsConfig; + /// + /// This member contains SPI configuration. + /// + PCH_SPI_CONFIG SpiConfig; + /// + /// This member describes HSIO settings for SATA controller + /// + PCH_HSIO_SATA_CONFIG HsioSataConfig; + /// + /// This member describes HSIO settings for second SATA controller + /// + PCH_HSIO_SATA_CONFIG HsiosSataConfig; + /// + /// This member describes HSIO settings for PCIe controller + /// + PCH_HSIO_PCIE_CONFIG HsioPcieConfig; + /// + /// This member describes HSIO settings for FIA WM20 PCIe + /// + PCH_HSIO_PCIE_WM20_CONFIG HsioPcieConfigFIAWM20; + /// + /// This is the extension of PCIE CONFIG + /// + PCH_PCIE_CONFIG2 PcieConfig2; + + PCH_ADR_CONFIG AdrConfig; + + +}; + +#pragma pack (pop) + +#endif // _PCH_POLICY_COMMON_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchReservedResources.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchReservedResources.h new file mode 100644 index 0000000000..df9762365f --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchReservedResources.h @@ -0,0 +1,82 @@ +/** @file + PCH preserved MMIO resource definitions. + + @copyright + Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PRESERVED_RESOURCES_H_ +#define _PCH_PRESERVED_RESOURCES_H_ + +/** +#ifdef SERVER_BIOS_FLAG + SKX map: +#endif //SERVER_BIOS_FLAG + PCH preserved MMIO range, 24 MB, from 0xFD000000 to 0xFE7FFFFF + + Detailed recommended static allocation + +-------------------------------------------------------------------------+ + | Size | Start | End | Usage | + | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG | + | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR | + | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 | + | 88 KB | 0xFE020000 | 0xFE035FFF | SerialIo BAR in ACPI mode | + | 24 KB | 0xFE036000 | 0xFE03BFFF | Unused | + | 4 KB | 0xFE03C000 | 0xFE03CFFF | Thermal Device in ACPI mode | + | 524 KB | 0xFE03D000 | 0xFE0BFFFF | Unused | + | 256 KB | 0xFE0C0000 | 0xFE0FFFFF | TraceHub FW BAR | + | 1 MB | 0xFE100000 | 0xFE1FFFFF | TraceHub MTB BAR | + | 2 MB | 0xFE200000 | 0xFE3FFFFF | TraceHub SW BAR | + | 64 KB | 0xFE400000 | 0xFE40FFFF | CIO2 MMIO BAR in ACPI mode | + | 2 MB - 64KB | 0xFE410000 | 0xFE5FFFFF | Unused | + | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address | + +-------------------------------------------------------------------------+ + +#ifdef SERVER_BIOS_FLAG + HSX map: + PCH preserved MMIO range, from 0xFC000000 to 0xFE7FFFFF + + Detailed recommended static allocation + +-------------------------------------------------------------------------+ + | Size | Start | End | Usage | + | 256 KB | 0xFC0C0000 | 0xFC0FFFFF | TraceHub FW BAR | + | 1 MB | 0xFC100000 | 0xFC1FFFFF | TraceHub MTB BAR | + | 2 MB | 0xFC200000 | 0xFC3FFFFF | TraceHub SW BAR | + | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG | + | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR | + | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 | + | 88 KB | 0xFE020000 | 0xFE035FFF | SerialIo BAR in ACPI mode | + | 24 KB | 0xFE036000 | 0xFE03BFFF | Unused | + | 4 KB | 0xFE03C000 | 0xFE03CFFF | Thermal Device in ACPI mode | + | 524 KB | 0xFE03D000 | 0xFE0BFFFF | Unused | + | 64 KB | 0xFE400000 | 0xFE40FFFF | CIO2 MMIO BAR in ACPI mode | + | 2 MB - 64KB | 0xFE410000 | 0xFE5FFFFF | Unused | + | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address | + +-------------------------------------------------------------------------+ +#endif //SERVER_BIOS_FLAG +**/ +#define PCH_PRESERVED_BASE_ADDRESS 0xFD000000 ///< Pch preserved MMIO base address +#define PCH_PRESERVED_MMIO_SIZE 0x01800000 ///< 24MB +#define PCH_PCR_BASE_ADDRESS 0xFD000000 ///< SBREG MMIO base address +#define PCH_PCR_MMIO_SIZE 0x01000000 ///< 16MB +#define PCH_PWRM_BASE_ADDRESS 0xFE000000 ///< PMC MBAR MMIO base address +#define PCH_PWRM_MMIO_SIZE 0x00010000 ///< 64KB +#define PCH_SPI_BASE_ADDRESS 0xFE010000 ///< SPI BAR0 MMIO base address +#define PCH_SPI_MMIO_SIZE 0x00001000 ///< 4KB +#define PCH_THERMAL_BASE_ADDRESS 0xFE03C000 ///< Thermal Device in ACPI mode +#define PCH_THERMAL_MMIO_SIZE 0x00001000 ///< 4KB + +#define PCH_TRACE_HUB_FW_BASE_ADDRESS 0xFE0C0000 ///< TraceHub FW MMIO base address +#define PCH_TRACE_HUB_FW_MMIO_SIZE 0x00040000 ///< 256KB +#define PCH_TRACE_HUB_MTB_BASE_ADDRESS 0xFE100000 ///< TraceHub MTB MMIO base address +#define PCH_TRACE_HUB_MTB_MMIO_SIZE 0x00100000 ///< 1MB +#define PCH_TRACE_HUB_SW_BASE_ADDRESS 0xFE200000 ///< TraceHub SW MMIO base address +#define PCH_TRACE_HUB_SW_MMIO_SIZE 0x00200000 ///< 2MB +#define PCH_CIO2_BASE_ADDRESS 0xFE400000 ///< CIO2 MMIO BAR in ACPI mode +#define PCH_CIO2_MMIO_SIZE 0x00010000 ///< 64KB +#define PCH_TEMP_BASE_ADDRESS 0xFE600000 ///< preserved temp address for misc usage +#define PCH_TEMP_MMIO_SIZE 0x00200000 ///< 2MB + +#endif // _PCH_PRESERVED_RESOURCES_H_ + diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PcieRegs.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PcieRegs.h new file mode 100644 index 0000000000..9ee146b941 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PcieRegs.h @@ -0,0 +1,288 @@ +/** @file + Register names for PCIE standard register + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCIE_REGS_H_ +#define _PCIE_REGS_H_ + +#include + +// +// PCI type 0 Header +// +#define R_PCI_PI_OFFSET 0x09 +#define R_PCI_SCC_OFFSET 0x0A +#define R_PCI_BCC_OFFSET 0x0B + +// +// PCI type 1 Header +// +#define R_PCI_BRIDGE_BNUM 0x18 ///< Bus Number Register +#define B_PCI_BRIDGE_BNUM_SBBN 0x00FF0000 ///< Subordinate Bus Number +#define B_PCI_BRIDGE_BNUM_SCBN 0x0000FF00 ///< Secondary Bus Number +#define B_PCI_BRIDGE_BNUM_PBN 0x000000FF ///< Primary Bus Number +#define B_PCI_BRIDGE_BNUM_SBBN_SCBN (B_PCI_BRIDGE_BNUM_SBBN | B_PCI_BRIDGE_BNUM_SCBN) + +#define R_PCI_BRIDGE_IOBL 0x1C ///< I/O Base and Limit Register + +#define R_PCI_BRIDGE_MBL 0x20 ///< Memory Base and Limit Register +#define B_PCI_BRIDGE_MBL_ML 0xFFF00000 ///< Memory Limit +#define B_PCI_BRIDGE_MBL_MB 0x0000FFF0 ///< Memory Base + +#define R_PCI_BRIDGE_PMBL 0x24 ///< Prefetchable Memory Base and Limit Register +#define B_PCI_BRIDGE_PMBL_PML 0xFFF00000 ///< Prefetchable Memory Limit +#define B_PCI_BRIDGE_PMBL_I64L 0x000F0000 ///< 64-bit Indicator +#define B_PCI_BRIDGE_PMBL_PMB 0x0000FFF0 ///< Prefetchable Memory Base +#define B_PCI_BRIDGE_PMBL_I64B 0x0000000F ///< 64-bit Indicator + +#define R_PCI_BRIDGE_PMBU32 0x28 ///< Prefetchable Memory Base Upper 32-Bit Register +#define B_PCI_BRIDGE_PMBU32 0xFFFFFFFF + +#define R_PCI_BRIDGE_PMLU32 0x2C ///< Prefetchable Memory Limit Upper 32-Bit Register +#define B_PCI_BRIDGE_PMLU32 0xFFFFFFFF + +// +// PCIE capabilities register +// +#define R_PCIE_CAP_ID_OFFSET 0x00 ///< Capability ID +#define R_PCIE_CAP_NEXT_PRT_OFFSET 0x01 ///< Next Capability Capability ID Pointer + +// +// PCI Express Capability List Register (CAPID:10h) +// +#define R_PCIE_XCAP_OFFSET 0x02 ///< PCI Express Capabilities Register (Offset 02h) +#define S_PCIE_XCAP 2 +#define B_PCIE_XCAP_SI BIT8 ///< Slot Implemented +#define B_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | BIT4) ///< Device/Port Type +#define N_PCIE_XCAP_DT 4 + +#define R_PCIE_DCAP_OFFSET 0x04 ///< Device Capabilities Register (Offset 04h) +#define S_PCIE_DCAP 4 +#define B_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) ///< Endpoint L1 Acceptable Latency +#define N_PCIE_DCAP_E1AL 9 +#define B_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) ///< Endpoint L0s Acceptable Latency +#define N_PCIE_DCAP_E0AL 6 +#define B_PCIE_DCAP_MPS (BIT2 | BIT1 | BIT0) ///< Max_Payload_Size Supported + +#define R_PCIE_DCTL_OFFSET 0x08 ///< Device Control Register (Offset 08h) +#define B_PCIE_DCTL_MPS (BIT7 | BIT6 | BIT5) ///< Max_Payload_Size +#define N_PCIE_DCTL_MPS 5 +#define B_PCIE_DCTL_URE BIT3 ///< Unsupported Request Reporting Enable +#define B_PCIE_DCTL_FEE BIT2 ///< Fatal Error Reporting Enable +#define B_PCIE_DCTL_NFE BIT1 ///< Non-Fatal Error Reporting Enable +#define B_PCIE_DCTL_CEE BIT0 ///< Correctable Error Reporting Enable + +#define R_PCIE_DSTS_OFFSET 0x0A ///< Device Status Register (Offset 0Ah) +#define B_PCIE_DSTS_TDP BIT5 ///< Transactions Pending +#define B_PCIE_DSTS_APD BIT4 ///< AUX Power Detected +#define B_PCIE_DSTS_URD BIT3 ///< Unsupported Request Detected +#define B_PCIE_DSTS_FED BIT2 ///< Fatal Error Detected +#define B_PCIE_DSTS_NFED BIT1 ///< Non-Fatal Error Detected +#define B_PCIE_DSTS_CED BIT0 ///< Correctable Error Detected + +#define R_PCIE_LCAP_OFFSET 0x0C ///< Link Capabilities Register (Offset 0Ch) +#define B_PCIE_LCAP_ASPMOC BIT22 ///< ASPM Optionality Compliance +#define B_PCIE_LCAP_CPM BIT18 ///< Clock Power Management +#define B_PCIE_LCAP_EL1 (BIT17 | BIT16 | BIT15) ///< L1 Exit Latency +#define N_PCIE_LCAP_EL1 15 +#define B_PCIE_LCAP_EL0 (BIT14 | BIT13 | BIT12) ///< L0s Exit Latency +#define N_PCIE_LCAP_EL0 12 +#define B_PCIE_LCAP_APMS (BIT11 | BIT10) ///< Active State Power Management (ASPM) Support +#define B_PCIE_LCAP_APMS_L0S BIT10 +#define B_PCIE_LCAP_APMS_L1 BIT11 +#define N_PCIE_LCAP_APMS 10 +#define B_PCIE_LCAP_MLW 0x000003F0 ///< Maximum Link Width +#define N_PCIE_LCAP_MLW 4 +#define B_PCIE_LCAP_MLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Max Link Speed +#define V_PCIE_LCAP_MLS_GEN3 3 + +#define R_PCIE_LCTL_OFFSET 0x10 ///< Link Control Register (Offset 10h) +#define B_PCIE_LCTL_ECPM BIT8 ///< Enable Clock Power Management +#define B_PCIE_LCTL_ES BIT7 ///< Extended Synch +#define B_PCIE_LCTL_CCC BIT6 ///< Common Clock Configuration +#define B_PCIE_LCTL_RL BIT5 ///< Retrain Link +#define B_PCIE_LCTL_LD BIT4 ///< Link Disable +#define B_PCIE_LCTL_ASPM (BIT1 | BIT0) ///< Active State Power Management (ASPM) Control +#define V_PCIE_LCTL_ASPM_L0S 1 +#define V_PCIE_LCTL_ASPM_L1 2 +#define V_PCIE_LCTL_ASPM_L0S_L1 3 + +#define R_PCIE_LSTS_OFFSET 0x12 ///< Link Status Register (Offset 12h) +#define B_PCIE_LSTS_LA BIT13 ///< Data Link Layer Link Active +#define B_PCIE_LSTS_SCC BIT12 ///< Slot Clock Configuration +#define B_PCIE_LSTS_LT BIT11 ///< Link Training +#define B_PCIE_LSTS_NLW 0x03F0 ///< Negotiated Link Width +#define N_PCIE_LSTS_NLW 4 +#define V_PCIE_LSTS_NLW_1 0x0010 +#define V_PCIE_LSTS_NLW_2 0x0020 +#define V_PCIE_LSTS_NLW_4 0x0040 +#define B_PCIE_LSTS_CLS 0x000F ///< Current Link Speed +#define V_PCIE_LSTS_CLS_GEN1 1 +#define V_PCIE_LSTS_CLS_GEN2 2 +#define V_PCIE_LSTS_CLS_GEN3 3 + +#define R_PCIE_SLCAP_OFFSET 0x14 ///< Slot Capabilities Register (Offset 14h) +#define S_PCIE_SLCAP 4 +#define B_PCIE_SLCAP_PSN 0xFFF80000 ///< Physical Slot Number +#define B_PCIE_SLCAP_SLS 0x00018000 ///< Slot Power Limit Scale +#define B_PCIE_SLCAP_SLV 0x00007F80 ///< Slot Power Limit Value +#define B_PCIE_SLCAP_HPC BIT6 ///< Hot-Plug Capable +#define B_PCIE_SLCAP_HPS BIT5 ///< Hot-Plug Surprise + +#define R_PCIE_SLCTL_OFFSET 0x18 ///< Slot Control Register (Offset 18h) +#define S_PCIE_SLCTL 2 +#define B_PCIE_SLCTL_HPE BIT5 ///< Hot Plug Interrupt Enable +#define B_PCIE_SLCTL_PDE BIT3 ///< Presence Detect Changed Enable + +#define R_PCIE_SLSTS_OFFSET 0x1A ///< Slot Status Register (Offset 1Ah) +#define S_PCIE_SLSTS 2 +#define B_PCIE_SLSTS_PDS BIT6 ///< Presence Detect State +#define B_PCIE_SLSTS_PDC BIT3 ///< Presence Detect Changed + +#define R_PCIE_RCTL_OFFSET 0x1C ///< Root Control Register (Offset 1Ch) +#define S_PCIE_RCTL 2 +#define B_PCIE_RCTL_PIE BIT3 ///< PME Interrupt Enable +#define B_PCIE_RCTL_SFE BIT2 ///< System Error on Fatal Error Enable +#define B_PCIE_RCTL_SNE BIT1 ///< System Error on Non-Fatal Error Enable +#define B_PCIE_RCTL_SCE BIT0 ///< System Error on Correctable Error Enable + +#define R_PCIE_RSTS_OFFSET 0x20 ///< Root Status Register (Offset 20h) +#define S_PCIE_RSTS 4 + +#define R_PCIE_DCAP2_OFFSET 0x24 ///< Device Capabilities 2 Register (Offset 24h) +#define B_PCIE_DCAP2_OBFFS (BIT19 | BIT18) ///< OBFF Supported +#define B_PCIE_DCAP2_LTRMS BIT11 ///< LTR Mechanism Supported + +#define R_PCIE_DCTL2_OFFSET 0x28 ///< Device Control 2 Register (Offset 28h) +#define B_PCIE_DCTL2_OBFFEN (BIT14 | BIT13) ///< OBFF Enable +#define N_PCIE_DCTL2_OBFFEN 13 +#define V_PCIE_DCTL2_OBFFEN_DIS 0 ///< Disabled +#define V_PCIE_DCTL2_OBFFEN_WAKE 3 ///< Enabled using WAKE# signaling +#define B_PCIE_DCTL2_LTREN BIT10 ///< LTR Mechanism Enable +#define B_PCIE_DCTL2_CTD BIT4 ///< Completion Timeout Disable +#define B_PCIE_DCTL2_CTV (BIT3 | BIT2 | BIT1 | BIT0) ///< Completion Timeout Value +#define V_PCIE_DCTL2_CTV_DEFAULT 0x0 +#define V_PCIE_DCTL2_CTV_40MS_50MS 0x5 +#define V_PCIE_DCTL2_CTV_160MS_170MS 0x6 +#define V_PCIE_DCTL2_CTV_400MS_500MS 0x9 +#define V_PCIE_DCTL2_CTV_1P6S_1P7S 0xA + +#define R_PCIE_LCTL2_OFFSET 0x30 ///< Link Control 2 Register (Offset 30h) +#define B_PCIE_LCTL2_SD BIT6 ///< Selectable de-emphasis (0 = -6dB, 1 = -3.5dB) +#define B_PCIE_LCTL2_TLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Target Link Speed +#define V_PCIE_LCTL2_TLS_GEN1 1 +#define V_PCIE_LCTL2_TLS_GEN2 2 +#define V_PCIE_LCTL2_TLS_GEN3 3 + +#define R_PCIE_LSTS2_OFFSET 0x32 ///< Link Status 2 Register (Offset 32h) +#define B_PCIE_LSTS2_LER BIT5 ///< Link Equalization Request +#define B_PCIE_LSTS2_EQP3S BIT4 ///< Equalization Phase 3 Successful +#define B_PCIE_LSTS2_EQP2S BIT3 ///< Equalization Phase 2 Successful +#define B_PCIE_LSTS2_EQP1S BIT2 ///< Equalization Phase 1 Successful +#define B_PCIE_LSTS2_EC BIT1 ///< Equalization Complete +#define B_PCIE_LSTS2_CDL BIT0 ///< Current De-emphasis Level + +// +// PCI Power Management Capability (CAPID:01h) +// +#define R_PCIE_PMC_OFFSET 0x02 ///< Power Management Capabilities Register +#define S_PCIE_PMC 2 +#define B_PCIE_PMC_PMES (BIT15 | BIT14 | BIT13 | BIT12 | BIT11) ///< PME Support +#define B_PCIE_PMC_PMEC BIT3 ///< PME Clock + +#define R_PCIE_PMCS_OFFST 0x04 ///< Power Management Status/Control Register +#define S_PCIE_PMCS 4 +#define B_PCIE_PMCS_BPCE BIT23 ///< Bus Power/Clock Control Enable +#define B_PCIE_PMCS_B23S BIT22 ///< B2/B3 Support +#define B_PCIE_PMCS_PMES BIT15 ///< PME_Status +#define B_PCIE_PMCS_PMEE BIT8 ///< PME Enable +#define B_PCIE_PMCS_NSR BIT3 ///< No Soft Reset +#define B_PCIE_PMCS_PS (BIT1 | BIT0) ///< Power State +#define V_PCIE_PMCS_PS_D0 0 +#define V_PCIE_PMCS_PS_D3H 3 + +// +// PCIE Extension Capability Register +// +#define B_PCIE_EXCAP_NCO 0xFFF00000 ///< Next Capability Offset +#define N_PCIE_EXCAP_NCO 20 +#define V_PCIE_EXCAP_NCO_LISTEND 0 +#define B_PCIE_EXCAP_CV 0x000F0000 ///< Capability Version +#define N_PCIE_EXCAP_CV 16 +#define B_PCIE_EXCAP_CID 0x0000FFFF ///< Capability ID + +// +// Advanced Error Reporting Capability (CAPID:0001h) +// +#define V_PCIE_EX_AEC_CID 0x0001 ///< Capability ID +#define R_PCIE_EX_UEM_OFFSET 0x08 ///< Uncorrectable Error Mask Register +#define B_PCIE_EX_UEM_CT BIT14 ///< Completion Timeout Mask +#define B_PCIE_EX_UEM_UC BIT16 ///< Unexpected Completion + +// +// ACS Extended Capability (CAPID:000Dh) +// +#define V_PCIE_EX_ACS_CID 0x000D ///< Capability ID +#define R_PCIE_EX_ACSCAPR_OFFSET 0x04 ///< ACS Capability Register +//#define R_PCIE_EX_ACSCTLR_OFFSET 0x08 ///< ACS Control Register (NOTE: register size in PCIE spce is not match the PCH register size) + +// +// Secondary PCI Express Extended Capability Header (CAPID:0019h) +// +#define V_PCIE_EX_SPE_CID 0x0019 ///< Capability ID +#define R_PCIE_EX_LCTL3_OFFSET 0x04 ///< Link Control 3 Register +#define B_PCIE_EX_LCTL3_PE BIT0 ///< Perform Equalization +#define R_PCIE_EX_LES_OFFSET 0x08 ///< Lane Error Status +#define R_PCIE_EX_L01EC_OFFSET 0x0C ///< Lane 0 and Lan 1 Equalization Control Register (Offset 0Ch) +#define B_PCIE_EX_L01EC_UPL1TP 0x0F000000 ///< Upstream Port Lane 1 Transmitter Preset +#define N_PCIE_EX_L01EC_UPL1TP 24 +#define B_PCIE_EX_L01EC_DPL1TP 0x000F0000 ///< Downstream Port Lane 1 Transmitter Preset +#define N_PCIE_EX_L01EC_DPL1TP 16 +#define B_PCIE_EX_L01EC_UPL0TP 0x00000F00 ///< Upstream Port Transmitter Preset +#define N_PCIE_EX_L01EC_UPL0TP 8 +#define B_PCIE_EX_L01EC_DPL0TP 0x0000000F ///< Downstream Port Transmitter Preset +#define N_PCIE_EX_L01EC_DPL0TP 0 + +#define R_PCIE_EX_L23EC_OFFSET 0x10 ///< Lane 2 and Lane 3 Equalization Control Register (Offset 10h) +#define B_PCIE_EX_L23EC_UPL3TP 0x0F000000 ///< Upstream Port Lane 3 Transmitter Preset +#define N_PCIE_EX_L23EC_UPL3TP 24 +#define B_PCIE_EX_L23EC_DPL3TP 0x000F0000 ///< Downstream Port Lane 3 Transmitter Preset +#define N_PCIE_EX_L23EC_DPL3TP 16 +#define B_PCIE_EX_L23EC_UPL2TP 0x00000F00 ///< Upstream Port Lane 2 Transmitter Preset +#define N_PCIE_EX_L23EC_UPL2TP 8 +#define B_PCIE_EX_L23EC_DPL2TP 0x0000000F ///< Downstream Port Lane 2 Transmitter Preset +#define N_PCIE_EX_L23EC_DPL2TP 0 + + +// +// L1 Sub-States Extended Capability Register (CAPID:001Eh) +// +#define V_PCIE_EX_L1S_CID 0x001E ///< Capability ID +#define R_PCIE_EX_L1SCAP_OFFSET 0x04 ///< L1 Sub-States Capabilities +#define R_PCIE_EX_L1SCTL1_OFFSET 0x08 ///< L1 Sub-States Control 1 +#define R_PCIE_EX_L1SCTL2_OFFSET 0x0C ///< L1 Sub-States Control 2 +#define N_PCIE_EX_L1SCTL2_POWT 3 + +// +// Base Address Offset +// +#define R_BASE_ADDRESS_OFFSET_0 0x0010 ///< Base Address Register 0 +#define R_BASE_ADDRESS_OFFSET_1 0x0014 ///< Base Address Register 1 +#define R_BASE_ADDRESS_OFFSET_2 0x0018 ///< Base Address Register 2 +#define R_BASE_ADDRESS_OFFSET_3 0x001C ///< Base Address Register 3 +#define R_BASE_ADDRESS_OFFSET_4 0x0020 ///< Base Address Register 4 +#define R_BASE_ADDRESS_OFFSET_5 0x0024 ///< Base Address Register 5 + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchHsioPtssTable.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchHsioPtssTable.h new file mode 100644 index 0000000000..d0ade33035 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchHsioPtssTable.h @@ -0,0 +1,31 @@ +/** @file + PCH policy PPI produced by a platform driver specifying HSIO PTSS Table. + This PPI is consumed by the PCH PEI modules. This is deprecated. + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_HSIO_PTSS_TABLE_H_ +#define _PCH_HSIO_PTSS_TABLE_H_ + +/// +/// HSIO PTSS table PPI GUID. +/// +extern EFI_GUID gPchHsioPtssTablePpiGuid; + +/// +/// The PCH_SBI_PTSS_HSIO_TABLE block describes HSIO PTSS settings for PCH. +/// +typedef struct { + UINT8 SbPortID; + UINT8 LaneNum; + UINT8 PhyMode; + UINT16 Offset; + UINT32 Value; + UINT32 BitMask; +} PCH_SBI_PTSS_HSIO_TABLE; + +#endif // _PCH_HSIO_PTSS_TABLE_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchPcieDeviceTable.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchPcieDeviceTable.h new file mode 100644 index 0000000000..6766805f68 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchPcieDeviceTable.h @@ -0,0 +1,126 @@ +/** @file + PCH policy PPI produced by a platform driver specifying PCIe device overrides. + + @copyright + Copyright 2013 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PCIE_DEVICE_TABLE_H_ +#define _PCH_PCIE_DEVICE_TABLE_H_ + + +// +// PCIe device table PPI GUID. +// +extern EFI_GUID gPchPcieDeviceTablePpiGuid; + +typedef enum { + PchPcieOverrideDisabled = 0, + PchPcieL1L2Override = 0x01, + PchPcieL1SubstatesOverride = 0x02, + PchPcieL1L2AndL1SubstatesOverride = 0x03, + PchPcieLtrOverride = 0x04 +} PCH_PCIE_OVERRIDE_CONFIG; + +/** + PCIe device table entry entry + + The PCIe device table is being used to override PCIe device ASPM settings. + To take effect table consisting of such entries must be instelled as PPI + on gPchPcieDeviceTablePpiGuid. + Last entry VendorId must be 0. +**/ +typedef struct { + UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID + UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID + UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings + UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class + UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class + UINT8 EndPointAspm; ///< Override device ASPM (see: PCH_PCIE_ASPM_CONTROL) + ///< Bit 1 must be set in OverrideConfig for this field to take effect + UINT16 OverrideConfig; ///< The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG). + /** + The L1Substates Capability Offset Override. (applicable if bit 2 is set in OverrideConfig) + This field can be zero if only the L1 Substate value is going to be override. + **/ + UINT16 L1SubstatesCapOffset; + /** + L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideConfig) + Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s values are override. + Only bit [3:0] are applicable. Other bits are ignored. + **/ + UINT8 L1SubstatesCapMask; + /** + L1 Substate Port Common Mode Restore Time Override. (applicable if bit 2 is set in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sCommonModeRestoreTime; + /** + L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sTpowerOnScale; + /** + L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sTpowerOnValue; + + /** + SnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with + the scale in bits 12:10 + + This field takes effect only if bit 3 is set in OverrideConfig. + **/ + UINT16 SnoopLatency; + /** + NonSnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with + the scale in bits 12:10 + + This field takes effect only if bit 3 is set in OverrideConfig. + **/ + UINT16 NonSnoopLatency; + + UINT32 Reserved; +} PCH_PCIE_DEVICE_OVERRIDE; + +#endif // _PCH_PCIE_DEVICE_TABLE_H_ + diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchPolicy.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchPolicy.h new file mode 100644 index 0000000000..b75613a5c7 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchPolicy.h @@ -0,0 +1,23 @@ +/** @file + PCH policy PPI produced by a platform driver specifying various + expected PCH settings. This PPI is consumed by the PCH PEI modules + and carried over to PCH DXE modules. + + @copyright + Copyright 2009 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_POLICY_PPI_H_ +#define _PCH_POLICY_PPI_H_ + +#include +#include + +extern EFI_GUID gPchPlatformPolicyPpiGuid; + + +typedef struct _PCH_POLICY PCH_POLICY_PPI; + +#endif // PCH_POLICY_PPI_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchReset.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchReset.h new file mode 100644 index 0000000000..2b5afbb929 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchReset.h @@ -0,0 +1,95 @@ +/** @file + PCH Reset PPI + + @copyright + Copyright 2011 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_RESET_PPI_H_ +#define _PCH_RESET_PPI_H_ + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPchResetPpiGuid; +extern EFI_GUID gPchResetCallbackPpiGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_RESET_PPI PCH_RESET_PPI; +typedef struct _PCH_RESET_CALLBACK_PPI PCH_RESET_CALLBACK_PPI; + +// +// Related Definitions +// +// +// PCH Reset Types +// +typedef enum { + ColdReset, + WarmReset, + ShutdownReset, + PowerCycleReset, + GlobalReset, + GlobalResetWithEc, + PchResetTypeMax +} PCH_RESET_TYPE; + +// +// Member functions +// +/** + Execute Pch Reset from the Host controller. + + @param[in] This Pointer to the PCH_RESET_PPI instance. + @param[in] PchResetType Pch Reset Types which includes ColdReset, WarmReset, ShutdownReset, + PowerCycleReset, GlobalReset, GlobalResetWithEc + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER If ResetType is invalid. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_RESET_PPI_API) ( + IN PCH_RESET_PPI *This, + IN PCH_RESET_TYPE PchResetType + ); + +/** + Execute call back function for Pch Reset. + + @param[in] PchResetType Pch Reset Types which includes PowerCycle, Globalreset. + + @retval EFI_SUCCESS The callback function has been done successfully + @retval EFI_NOT_FOUND Failed to find Pch Reset Callback ppi. Or, none of + callback ppi is installed. + @retval Others Do not do any reset from PCH +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_RESET_CALLBACK) ( + IN EFI_RESET_TYPE ResetType + ); + +/** + Interface structure to execute Pch Reset from the Host controller. +**/ +struct _PCH_RESET_PPI { + PCH_RESET_PPI_API Reset; +}; + +/** + This ppi is used to execute PCH Reset from the Host controller. + The PCH Reset protocol and PCH Reset PPI implement the Intel (R) PCH Reset Interface + for DXE and PEI environments, respectively. If other drivers need to run their + callback function right before issuing the reset, they can install PCH Reset + Callback Protocol/PPI before PCH Reset DXE/PEI driver to achieve that. +**/ +struct _PCH_RESET_CALLBACK_PPI { + PCH_RESET_CALLBACK ResetCallback; +}; + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/Spi.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/Spi.h new file mode 100644 index 0000000000..c0f126ef41 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/Spi.h @@ -0,0 +1,28 @@ +/** @file + This file defines the PCH SPI PPI which implements the + Intel(R) PCH SPI Host Controller Compatibility Interface. + + @copyright + Copyright 2006 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SPI_PPI_H_ +#define _PCH_SPI_PPI_H_ + +#include + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPchSpiPpiGuid; + +/** + Reuse the PCH_SPI_PROTOCOL definitions + This is possible becaues the PPI implementation does not rely on a PeiService pointer, + as it uses EDKII Glue Lib to do IO accesses +**/ +typedef PCH_SPI_PROTOCOL PCH_SPI_PPI; + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Private/Library/PchSpiCommonLib.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Private/Library/PchSpiCommonLib.h new file mode 100644 index 0000000000..f93740f4f0 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Private/Library/PchSpiCommonLib.h @@ -0,0 +1,458 @@ +/** @file + Header file for the PCH SPI Common Driver. + + @copyright + Copyright 2008 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SPI_COMMON_LIB_H_ +#define _PCH_SPI_COMMON_LIB_H_ + +#include + +// +// Maximum time allowed while waiting the SPI cycle to complete +// Wait Time = 6 seconds = 6000000 microseconds +// Wait Period = 10 microseconds +// +#define SPI_WAIT_TIME 6000000 ///< Wait Time = 6 seconds = 6000000 microseconds +#define SPI_WAIT_PERIOD 10 ///< Wait Period = 10 microseconds + +/// +/// Flash cycle Type +/// +typedef enum { + FlashCycleRead, + FlashCycleWrite, + FlashCycleErase, + FlashCycleReadSfdp, + FlashCycleReadJedecId, + FlashCycleWriteStatus, + FlashCycleReadStatus, + FlashCycleMax +} FLASH_CYCLE_TYPE; + +/// +/// Flash Component Number +/// +typedef enum { + FlashComponent0, + FlashComponent1, + FlashComponentMax +} FLASH_COMPONENT_NUM; + +/// +/// Private data structure definitions for the driver +/// +#define PCH_SPI_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('P', 'S', 'P', 'I') + +typedef struct { + UINT32 Signature; + EFI_HANDLE Handle; + PCH_SPI_PROTOCOL SpiProtocol; + UINT16 PchAcpiBase; + UINTN PchSpiBase; + UINT16 ReadPermission; + UINT16 WritePermission; + UINT32 SfdpVscc0Value; + UINT32 SfdpVscc1Value; + UINT16 PchStrapBaseAddr; + UINT16 PchStrapSize; + UINT16 CpuStrapBaseAddr; + UINT16 CpuStrapSize; + UINT8 NumberOfComponents; + UINT32 Component1StartAddr; + UINT32 TotalFlashSize; +} SPI_INSTANCE; + +#define SPI_INSTANCE_FROM_SPIPROTOCOL(a) CR (a, SPI_INSTANCE, SpiProtocol, PCH_SPI_PRIVATE_DATA_SIGNATURE) + +// +// Function prototypes used by the SPI protocol. +// + +/** + Initialize an SPI protocol instance. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - Non-Legacy PCH) + @param[in] SpiInstance Pointer to SpiInstance to initialize + + @retval EFI_SUCCESS The protocol instance was properly initialized + @exception EFI_UNSUPPORTED The PCH is not supported by this module +**/ +EFI_STATUS +SpiProtocolConstructor ( + IN UINT8 PchId, + IN SPI_INSTANCE *SpiInstance + ); + +/** + This function is a hook for Spi to disable BIOS Write Protect + + @param[in] SpiBaseAddress SPI base address + + @retval EFI_SUCCESS The protocol instance was properly initialized + @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase + +**/ +EFI_STATUS +EFIAPI +DisableBiosWriteProtect ( + UINTN SpiBaseAddress + ); + +/** + This function is a hook for Spi to enable BIOS Write Protect + + @param[in] SpiBaseAddress SPI base address + +**/ +VOID +EFIAPI +EnableBiosWriteProtect ( + UINTN SpiBaseAddress + ); + +/** + Acquire pch spi mmio address. + + @param[in] SpiInstance Pointer to SpiInstance to initialize + + @retval PchSpiBar0 return SPI MMIO address +**/ +UINTN +AcquireSpiBar0 ( + IN SPI_INSTANCE *SpiInstance + ); + +/** + Release pch spi mmio address. + + @param[in] SpiInstance Pointer to SpiInstance to initialize + + @retval None +**/ +VOID +ReleaseSpiBar0 ( + IN SPI_INSTANCE *SpiInstance + ); + +/** + Check if a save and restore of the SPI controller state is necessary + + @retval TRUE It's necessary to save and restore SPI controller state + @retval FALSE It's not necessary to save and restore SPI controller state +**/ +BOOLEAN +IsSpiControllerSaveRestoreEnabled ( + VOID + ); + +/** + Read data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of the SPI cycle. + @param[out] Buffer The Pointer to caller-allocated buffer containing the dada received. + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashRead ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *Buffer + ); + +/** + Write data to the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of the SPI cycle. + @param[in] Buffer Pointer to caller-allocated buffer containing the data sent during the SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashWrite ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + IN UINT8 *Buffer + ); + +/** + Erase some area on the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of the SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashErase ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount + ); + +/** + Read SFDP data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] Address The starting byte address for SFDP data read. + @param[in] ByteCount Number of bytes in SFDP data portion of the SPI cycle + @param[out] SfdpData The Pointer to caller-allocated buffer containing the SFDP data received + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashReadSfdp ( + IN PCH_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *SfdpData + ); + +/** + Read Jedec Id from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] ByteCount Number of bytes in JedecId data portion of the SPI cycle, the data size is 3 typically + @param[out] JedecId The Pointer to caller-allocated buffer containing JEDEC ID received + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashReadJedecId ( + IN PCH_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 ByteCount, + OUT UINT8 *JedecId + ); + +/** + Write the status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically + @param[in] StatusValue The Pointer to caller-allocated buffer containing the value of Status register writing + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashWriteStatus ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + IN UINT8 *StatusValue + ); + +/** + Read status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically + @param[out] StatusValue The Pointer to caller-allocated buffer containing the value of Status register received. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashReadStatus ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + OUT UINT8 *StatusValue + ); + +/** + Get the SPI region base and size, based on the enum type + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for for the base address which is listed in the Descriptor. + @param[out] BaseAddress The Flash Linear Address for the Region 'n' Base + @param[out] RegionSize The size for the Region 'n' + + @retval EFI_SUCCESS Read success + @retval EFI_INVALID_PARAMETER Invalid region type given + @retval EFI_DEVICE_ERROR The region is not used +**/ +EFI_STATUS +EFIAPI +SpiProtocolGetRegionAddress ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + OUT UINT32 *BaseAddress, + OUT UINT32 *RegionSize + ); + +/** + Read PCH Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA. + @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle + @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing PCH Soft Strap Value. + If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolReadPchSoftStrap ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + Read CPU Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA. + @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle. + @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing CPU Soft Strap Value. + If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolReadCpuSoftStrap ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + Read CPU Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA. + @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle. + @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing CPU Soft Strap Value. + If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolReadCpuSoftStrap ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + Function updates entire softstrap region. + + @param[in] This Pointer to the EFI_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle + @param[out] Buffer Pointer to the PCH Soft Strap Values to be writen. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @exception EFI_UNSUPPORTED Command not supported. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolUpdatePchSoftStraps ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + OUT UINT8 *Buffer + ); + +/** + This function sends the programmed SPI command to the slave device. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SpiRegionType The SPI Region type for flash cycle which is listed in the Descriptor + @param[in] FlashCycleType The Flash SPI cycle type list in HSFC (Hardware Sequencing Flash Control Register) register + @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of the SPI cycle. + @param[in,out] Buffer Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle. + + @retval EFI_SUCCESS SPI command completes successfully. + @retval EFI_DEVICE_ERROR Device error, the command aborts abnormally. + @retval EFI_ACCESS_DENIED Some unrecognized command encountered in hardware sequencing mode + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. +**/ +EFI_STATUS +SendSpiCmd ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN FLASH_CYCLE_TYPE FlashCycleType, + IN UINT32 Address, + IN UINT32 ByteCount, + IN OUT UINT8 *Buffer + ); + +/** + Wait execution cycle to complete on the SPI interface. + + @param[in] This The SPI protocol instance + @param[in] PchSpiBar0 Spi MMIO base address + @param[in] ErrorCheck TRUE if the SpiCycle needs to do the error check + + @retval TRUE SPI cycle completed on the interface. + @retval FALSE Time out while waiting the SPI cycle to complete. + It's not safe to program the next command on the SPI interface. +**/ +BOOLEAN +WaitForSpiCycleComplete ( + IN PCH_SPI_PROTOCOL *This, + IN UINTN PchSpiBar0, + IN BOOLEAN ErrorCheck + ); + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Protocol/PchReset.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Protocol/PchReset.h new file mode 100644 index 0000000000..f951b381a6 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Protocol/PchReset.h @@ -0,0 +1,114 @@ +/** @file + PCH Reset Protocol + + @copyright + Copyright 2011 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_RESET_H_ +#define _PCH_RESET_H_ + +#include + +#define EFI_CAPSULE_VARIABLE_NAME L"CapsuleUpdateData" +extern EFI_GUID gEfiCapsuleVendorGuid; + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchResetProtocolGuid; +extern EFI_GUID gPchResetCallbackProtocolGuid; +extern EFI_GUID gPchPowerCycleResetGuid; +extern EFI_GUID gPchGlobalResetGuid; +extern EFI_GUID gPchGlobalResetWithEcGuid; +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_RESET_PROTOCOL PCH_RESET_PROTOCOL; + +typedef PCH_RESET_CALLBACK_PPI PCH_RESET_CALLBACK_PROTOCOL; + +// +// Related Definitions +// +// +// PCH Platform Specific ResetData +// +#define PCH_POWER_CYCLE_RESET_GUID \ + { \ + 0x8d8ee25b, 0x66dd, 0x4ed8, { 0x8a, 0xbd, 0x14, 0x16, 0xe8, 0x8e, 0x1d, 0x24 } \ + } + +#define PCH_GLOBAL_RESET_GUID \ + { \ + 0x9db31b4c, 0xf5ef, 0x48bb, { 0x94, 0x2b, 0x18, 0x1f, 0x7e, 0x3a, 0x3e, 0x40 } \ + } + +#define PCH_GLOBAL_RESET_WITH_EC_GUID \ + { \ + 0xd22e6b72, 0x53cd, 0x4158, { 0x83, 0x3f, 0x6f, 0xd8, 0x7e, 0xbe, 0xa9, 0x93 } \ + } + +#define PCH_PLATFORM_SPECIFIC_RESET_STRING L"PCH_RESET" +#define PCH_RESET_DATA_STRING_MAX_LENGTH sizeof (PCH_PLATFORM_SPECIFIC_RESET_STRING) + +typedef struct _RESET_DATA { + CHAR16 Description[PCH_RESET_DATA_STRING_MAX_LENGTH]; + EFI_GUID Guid; +} PCH_RESET_DATA; + + +// +// Member functions +// +/** + Execute Pch Reset from the Host controller. + + @param[in] This Pointer to the PCH_RESET_PROTOCOL instance. + @param[in] ResetType UEFI defined reset type. + @param[in] DataSize The size of ResetData in bytes. + @param[in] ResetData Optional element used to introduce a platform specific reset. + The exact type of the reset is defined by the EFI_GUID that follows + the Null-terminated Unicode string. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER If ResetType is invalid. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_RESET) ( + IN PCH_RESET_PROTOCOL *This, + IN PCH_RESET_TYPE ResetType, + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ); + +/** + Retrieve PCH platform specific ResetData + + @param[in] Guid PCH platform specific reset GUID. + @param[out] DataSize The size of ResetData in bytes. + + @retval ResetData A platform specific reset that the exact type of + the reset is defined by the EFI_GUID that follows + the Null-terminated Unicode string. + @retval NULL If Guid is not defined in PCH platform specific reset. +**/ +typedef +VOID * +(EFIAPI *PCH_RESET_GET_RESET_DATA) ( + IN EFI_GUID *Guid, + OUT UINTN *DataSize + ); + +/** + Interface structure to execute Pch Reset from the Host controller. +**/ +struct _PCH_RESET_PROTOCOL { + PCH_RESET Reset; + PCH_RESET_GET_RESET_DATA GetResetData; +}; + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Protocol/Spi.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Protocol/Spi.h new file mode 100644 index 0000000000..45560d67f5 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Protocol/Spi.h @@ -0,0 +1,305 @@ +/** @file + This file defines the PCH SPI Protocol which implements the + Intel(R) PCH SPI Host Controller Compatibility Interface. + + @copyright + Copyright 2006 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SPI_PROTOCOL_H_ +#define _PCH_SPI_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchSpiProtocolGuid; +extern EFI_GUID gPchSmmSpiProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL; + +// +// SPI protocol data structures and definitions +// + +/** + Flash Region Type +**/ +typedef enum { + FlashRegionDescriptor, + FlashRegionBios, + FlashRegionMe, + FlashRegionGbE, + FlashRegionPlatformData, + FlashRegionDer, + FlashRegionSecondaryBios, + FlashRegionuCodePatch, + FlashRegionEC, + FlashRegionDeviceExpansion2, + FlashRegionIE, + FlashRegion10Gbe_A, + FlashRegion10Gbe_B, + FlashRegion13, + FlashRegion14, + FlashRegion15, + FlashRegionAll, + FlashRegionMax +} FLASH_REGION_TYPE; + +// +// Protocol member functions +// + +/** + Read data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of the SPI cycle. + @param[out] Buffer The Pointer to caller-allocated buffer containing the dada received. + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ) ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *Buffer + ); + +/** + Write data to the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of the SPI cycle. + @param[in] Buffer Pointer to caller-allocated buffer containing the data sent during the SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_WRITE) ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + IN UINT8 *Buffer + ); + +/** + Erase some area on the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of the SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_ERASE) ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount + ); + +/** + Read SFDP data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] Address The starting byte address for SFDP data read. + @param[in] ByteCount Number of bytes in SFDP data portion of the SPI cycle + @param[out] SfdpData The Pointer to caller-allocated buffer containing the SFDP data received + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_SFDP) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *SfdpData + ); + +/** + Read Jedec Id from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] ByteCount Number of bytes in JedecId data portion of the SPI cycle, the data size is 3 typically + @param[out] JedecId The Pointer to caller-allocated buffer containing JEDEC ID received + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_JEDEC_ID) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 ByteCount, + OUT UINT8 *JedecId + ); + +/** + Write the status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically + @param[in] StatusValue The Pointer to caller-allocated buffer containing the value of Status register writing + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_WRITE_STATUS) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + IN UINT8 *StatusValue + ); + +/** + Read status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically + @param[out] StatusValue The Pointer to caller-allocated buffer containing the value of Status register received. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_STATUS) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + OUT UINT8 *StatusValue + ); + +/** + Get the SPI region base and size, based on the enum type + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for for the base address which is listed in the Descriptor. + @param[out] BaseAddress The Flash Linear Address for the Region 'n' Base + @param[out] RegionSize The size for the Region 'n' + + @retval EFI_SUCCESS Read success + @retval EFI_INVALID_PARAMETER Invalid region type given + @retval EFI_DEVICE_ERROR The region is not used +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_GET_REGION_ADDRESS) ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + OUT UINT32 *BaseAddress, + OUT UINT32 *RegionSize + ); + +/** + Read PCH Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA. + @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle + @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing PCH Soft Strap Value. + If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_READ_PCH_SOFTSTRAP) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + Read CPU Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA. + @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle. + @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing CPU Soft Strap Value. + If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_READ_CPU_SOFTSTRAP) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + These protocols/PPI allows a platform module to perform SPI operations through the + Intel PCH SPI Host Controller Interface. +**/ +struct _PCH_SPI_PROTOCOL { + /** + This member specifies the revision of this structure. This field is used to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + PCH_SPI_FLASH_READ FlashRead; ///< Read data from the flash part. + PCH_SPI_FLASH_WRITE FlashWrite; ///< Write data to the flash part. + PCH_SPI_FLASH_ERASE FlashErase; ///< Erase some area on the flash part. + PCH_SPI_FLASH_READ_SFDP FlashReadSfdp; ///< Read SFDP data from the flash part. + PCH_SPI_FLASH_READ_JEDEC_ID FlashReadJedecId; ///< Read Jedec Id from the flash part. + PCH_SPI_FLASH_WRITE_STATUS FlashWriteStatus; ///< Write the status register in the flash part. + PCH_SPI_FLASH_READ_STATUS FlashReadStatus; ///< Read status register in the flash part. + PCH_SPI_GET_REGION_ADDRESS GetRegionAddress; ///< Get the SPI region base and size + PCH_SPI_READ_PCH_SOFTSTRAP ReadPchSoftStrap; ///< Read PCH Soft Strap Values + PCH_SPI_READ_CPU_SOFTSTRAP ReadCpuSoftStrap; ///< Read CPU Soft Strap Values +}; + +/** + PCH SPI PPI/PROTOCOL revision number + + Revision 1: Initial version +**/ +#define PCH_SPI_SERVICES_REVISION 1 + +#endif -- 2.27.0.windows.1