From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f175.google.com (mail-pf1-f175.google.com [209.85.210.175]) by mx.groups.io with SMTP id smtpd.web10.2455.1626171255668957553 for ; Tue, 13 Jul 2021 03:14:15 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=PRklQVzc; spf=pass (domain: ventanamicro.com, ip: 209.85.210.175, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pf1-f175.google.com with SMTP id d12so19147003pfj.2 for ; Tue, 13 Jul 2021 03:14:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=xCRRNNuv1phUATfDjMe2BgNgaHP612G2RDCwDpWPFA8=; b=PRklQVzcEnX+9vB2KZEUwkQkojG8rCzWgpfDaA16JbiUeD//Q/L39ZoJL0+g5OtzFY Gz/sm7umklouZAkRyjQDY8TFLbHdXmxaiUKtTk35Z0gDa69VsnkzyBFj4j0r+cvB9SKr TcZi9QghzIvfZFZcxdb7bctQ+skhUXSztoUJi1zge9Me4przVy35E2dlPAocDK1Lhivk /53KlbMM0rPtO1arg80YjJyHYWZqIkH6d0GyCdjoEpT+ZYE2olF+81Xrh4xvuFEeTq5o 5ynQdIDOQwuqMAW94ac35uH4S7XSs6zRXwzIKH8I9JmC5WY0ajJcxvwIoTfUDmqJd9n2 rWdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=xCRRNNuv1phUATfDjMe2BgNgaHP612G2RDCwDpWPFA8=; b=HaCw9wiyUXUHwTSljFUdYGh/8gJXeNaKb5L+lxsvv7wLC/6rcC67ciePV1hh2jAHNc 404zt41oN4XOX1xHX1ff290YEv5CHzhVlkJmouEx7qqjbYd6Wok5a77ecP3NfoCjRTKd SE30DSlUHvkt4disIl+bqqoP8O9Sz563ukQS2Z/q9dtQGvSN2KAIQ/Q6Eqi8HZnQvQ1B 8MQR5IDFkKvo1eauQZ0PNFTJ8hsU3sjxnG50ThYiIZBLdXxiqL2zsZKBBYGEfiiRfvmJ H7ankJUFOUIgrITEm6QZDtQ1q8MkgNZ/yiCf6F9Xz0A/wpFsxUu7lTNdgNa3nXhGpHNb UeGg== X-Gm-Message-State: AOAM530FWdcbzIyxroyFLXebRd5UPebRhFHnqzl9VVnayZTDgpARwZNo tm7IG+WE9HTltn04pNKuYNFunA== X-Google-Smtp-Source: ABdhPJwo02VNsPNMQIGTCSOmRkezSe5KvoKM6+RYUiK7fUYbT702xBIm5m8J6NSwXt74z+8Lm1w46Q== X-Received: by 2002:a63:5703:: with SMTP id l3mr3589973pgb.338.1626171255291; Tue, 13 Jul 2021 03:14:15 -0700 (PDT) Return-Path: Received: from sunil-ThinkPad-T490 ([49.206.3.187]) by smtp.gmail.com with ESMTPSA id d20sm18652538pfn.219.2021.07.13.03.14.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jul 2021 03:14:14 -0700 (PDT) Date: Tue, 13 Jul 2021 15:44:08 +0530 From: Sunil V L To: Daniel Schaefer Cc: devel@edk2.groups.io, sunil.vl@gmail.com, Liming Gao , Bob Feng , Yuwei Chen , Pete Batard , Abner Chang Subject: Re: [PATCH] BaseTools GenFw: Add support for R_RISCV_PCREL_LO12_S relocation Message-ID: <20210713101408.GA72964@sunil-ThinkPad-T490> References: <20210710063114.4278-1-sunilvl@ventanamicro.com> <3a9012d4-512b-e545-5541-39986d5a7b50@hpe.com> MIME-Version: 1.0 In-Reply-To: <3a9012d4-512b-e545-5541-39986d5a7b50@hpe.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Jul 13, 2021 at 05:27:30PM +0800, Daniel Schaefer wrote: > Looks good. I compared it with existing R_RISCV_PCREL_LO12_I and looked at > the differences. > Thanks Daniel. > This one doesn't do use mRiscVPass1GotFixup. > I assume this is an optimization that's not possible here? GOT fixup is required only for load to avoid the indirection for symbol resolution. Thanks Sunil > > Haven't tested that it works but since it works for Pete: > > Reviewed-by: Daniel Schaefer > > Thanks! > > On 7/10/21 2:31 PM, Sunil V L wrote: > > Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3459 > > > > This patch adds support for R_RISCV_PCREL_LO12_S relocation type. > > The logic is same as existing R_RISCV_PCREL_LO12_I relocation > > except the difference between load vs store instruction formats. > > > > Signed-off-by: Sunil V L > > > > Cc: Liming Gao > > Cc: Bob Feng > > Cc: Yuwei Chen > > Cc: Pete Batard > > Cc: Abner Chang > > Cc: Daniel Schaefer > > --- > > BaseTools/Source/C/GenFw/Elf64Convert.c | 55 +++++++++++++++++++++++++ > > 1 file changed, 55 insertions(+) > > > > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c > > index 3d7e20aaff..0bb3ead228 100644 > > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c > > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c > > @@ -557,6 +557,60 @@ WriteSectionRiscV64 ( > > Value = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20)); > > break; > > + case R_RISCV_PCREL_LO12_S: > > + if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) { > > + int i; > > + Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20)); > > + > > + Value = ((UINT32)(RV_X(*(UINT32 *)Targ, 25, 7)) << 5); > > + Value = (Value | (UINT32)(RV_X(*(UINT32 *)Targ, 7, 5))); > > + > > + if(Value & (RISCV_IMM_REACH/2)) { > > + Value |= ~(RISCV_IMM_REACH-1); > > + } > > + Value = Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOffset[mRiscVPass1SymSecIndex]; > > + > > + if(-2048 > (INT32)Value) { > > + i = (((INT32)Value * -1) / 4096); > > + Value2 -= i; > > + Value += 4096 * i; > > + if(-2048 > (INT32)Value) { > > + Value2 -= 1; > > + Value += 4096; > > + } > > + } > > + else if( 2047 < (INT32)Value) { > > + i = (Value / 4096); > > + Value2 += i; > > + Value -= 4096 * i; > > + if(2047 < (INT32)Value) { > > + Value2 += 1; > > + Value -= 4096; > > + } > > + } > > + > > + // Update the IMM of SD instruction > > + // > > + // |31 25|24 20|19 15|14 12 |11 7|6 0| > > + // |-------------------------------------------|-------| > > + // |imm[11:5] | rs2 | rs1 | funct3 |imm[4:0] | opcode| > > + // --------------------------------------------------- > > + > > + // First Zero out current IMM > > + *(UINT32 *)Targ &= ~0xfe000f80; > > + > > + // Update with new IMM > > + *(UINT32 *)Targ |= (RV_X(Value, 5, 7) << 25); > > + *(UINT32 *)Targ |= (RV_X(Value, 0, 5) << 7); > > + > > + // Update previous instruction > > + *(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12)); > > + } > > + mRiscVPass1Sym = NULL; > > + mRiscVPass1Targ = NULL; > > + mRiscVPass1SymSecIndex = 0; > > + break; > > + > > case R_RISCV_PCREL_LO12_I: > > if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) { > > int i; > > @@ -1587,6 +1641,7 @@ WriteRelocations64 ( > > case R_RISCV_PCREL_HI20: > > case R_RISCV_GOT_HI20: > > case R_RISCV_PCREL_LO12_I: > > + case R_RISCV_PCREL_LO12_S: > > break; > > default: > >