From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lf1-f50.google.com (mail-lf1-f50.google.com [209.85.167.50]) by mx.groups.io with SMTP id smtpd.web08.25751.1626687061896248585 for ; Mon, 19 Jul 2021 02:31:02 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=NCTl7Unz; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.167.50, mailfrom: mw@semihalf.com) Received: by mail-lf1-f50.google.com with SMTP id f30so22548151lfv.10 for ; Mon, 19 Jul 2021 02:31:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8Zz42eiU6F5O0JfpBuoceW0dzu8yknb9voBWa6hgZCQ=; b=NCTl7UnzrmbfG8LAdfvFpJVNI6x6zPNUbE1AHstoqqmOAwMrBqgKN7AlxBzh0lWpld 2U+q/7YnIpxNGUs6Zu8fyPuZ49E3DJJI3OsFy/Thup3H8sRkOnPAkR+oLr/JVqBf+I/o baVCgh8MK6HwWidf8MnYWq7QAkTKhaG3u2SyJi2iuvxhKiWXg55v3/81b5wmTqYqsAkd fWoIV1zQZTwlQE9qyUhge8b9Q4mgHgwnj69K2bOSHFryN8T1+Eq06VmGd6E2eshL1kJM 0Uo/wdfqlTIU5rgcxeJ/HENQbKD18f1OYIR5UEs9qhjLtOSHJL8YN/mHe1SEo7E9OqTX 0wPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8Zz42eiU6F5O0JfpBuoceW0dzu8yknb9voBWa6hgZCQ=; b=ro67WNRFdIq1VBdEL9zuf38acKx8I+BuKg6K6tXpr1inz2YieEV7P0cn09nZuWrk5d SBC/lF1w/pa64g8gZJ0BNZfVv3P2mE/KCjev1GQCmKjlJ/xeE9CqcnS4r+soIk6WuNwC cZPxOnuGzY+vGAsD6wSJdafieczrIap62S9PbnryJhEo5x/wDDsqzaPuDxxfGDmwmYQq z4SMSTrEkoirkWZTCK1NiGhOAo4o9UPJf4W5/gWRE46M+/UXnvctR+JGrxpAWFt3W2ho 8w5sw9mDykGCFQPidYOVHMTZehh16o3/u7RIbQN6CzkI4T9gDS89+4G+qGd16tCfxU5J HqLA== X-Gm-Message-State: AOAM533dge7qEp37YUBtCObJ1hdSfM1DYQ+LzssaF9R+fK/6StzSZbnI DfNDivsIIc0U9RVbSaqV2AwdFmotIyQOl0u1 X-Google-Smtp-Source: ABdhPJw9ZkA4njQAOUwRtl4zfmZ5fdAWMO4nCsqsmq/CruVzH/JpHz3B0kNrA47JczTQBxB+Sx7JkA== X-Received: by 2002:ac2:562e:: with SMTP id b14mr17542937lff.620.1626687060083; Mon, 19 Jul 2021 02:31:00 -0700 (PDT) Return-Path: Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id u14sm1252560lfr.86.2021.07.19.02.30.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 02:30:59 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Marcin Wojtas Subject: [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables Date: Mon, 19 Jul 2021 11:30:10 +0200 Message-Id: <20210719093015.1490932-3-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210719093015.1490932-1-mw@semihalf.com> References: <20210719093015.1490932-1-mw@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable BBR 1.0 spec says that _STA is required for each device in DSDT or SSDT. Fix that for all platforms with the Marvell SoC's. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 ++++++= +++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++= ++++++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 72 ++++++= +++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 ++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 56 ++++++= +++++++++ 5 files changed, 272 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/= Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl index 345c1e4dd6..88e38efeeb 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA7K", 3) {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x000) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU1)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x001) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU2)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x100) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU3)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x101) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D =0D Device (AHC0)=0D @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A7K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CLS, Package (0x03) // _CLS: Class Code=0D {=0D 0x01,=0D @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A7K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -96,6 +120,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA7K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -123,6 +151,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -142,6 +174,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -160,6 +196,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) {=0D Name (_HID, "MRVL0001") // _HID: H= ardware ID=0D Name (_CID, "HISI0031") // _CID: C= ompatible ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress=0D Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings=0D {=0D @@ -186,6 +226,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) {=0D Name (_HID, "MRVL0100") // _HID: H= ardware ID=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite,=0D @@ -208,6 +252,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)=0D @@ -286,6 +334,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) {=0D Name (_HID, "PRP0001") // _HID= : Hardware ID=0D Name (_UID, 0x00) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)=0D @@ -312,6 +364,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment=0D Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_PRT, Package () // _PRT: PCI Routing Table=0D {=0D Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/= Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl index 91401c74c8..77d3aebaf1 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x000) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU1)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x001) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU2)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x100) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU3)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x101) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D =0D Device (AHC0)=0D @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CLS, Package (0x03) // _CLS: Class Code=0D {=0D 0x01,=0D @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CLS, Package (0x03) // _CLS: Class Code=0D {=0D 0x01,=0D @@ -92,6 +116,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -122,6 +150,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -151,6 +183,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -170,6 +206,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x02) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -207,6 +251,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "MRVL0001") // _HID: H= ardware ID=0D Name (_CID, "HISI0031") // _CID: C= ompatible ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress=0D Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings=0D {=0D @@ -233,6 +281,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "MRVL0100") // _HID: H= ardware ID=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite,=0D @@ -251,6 +303,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)=0D @@ -309,6 +365,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "MRVL0100") // _HID: H= ardware ID=0D Name (_UID, 0x01) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite,=0D @@ -327,6 +387,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x01) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)=0D @@ -385,6 +449,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "PRP0001") // _HID= : Hardware ID=0D Name (_UID, 0x00) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)=0D @@ -405,6 +473,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "PRP0001") // _HID= : Hardware ID=0D Name (_UID, 0x01) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xF4760000, 0x7D)=0D @@ -431,6 +503,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment=0D Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_PRT, Package () // _PRT: PCI Routing Table=0D {=0D Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl= b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl index d26945d933..1ecbd0309c 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl @@ -19,21 +19,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x000) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU1)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x001) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU2)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x100) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU3)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x101) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D =0D Device (AHC0)=0D @@ -41,6 +57,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CLS, Package (0x03) // _CLS: Class Code=0D {=0D 0x01,=0D @@ -91,6 +111,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -122,6 +146,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -150,6 +178,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -169,6 +201,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -188,6 +224,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x02) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -206,6 +246,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "MRVL0001") // _HID: H= ardware ID=0D Name (_CID, "HISI0031") // _CID: C= ompatible ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress=0D Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings=0D {=0D @@ -232,6 +276,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "MRVL0100") // _HID: H= ardware ID=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite,=0D @@ -249,6 +297,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "MRVL0101") // _HID: H= ardware ID=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite,=0D @@ -283,6 +335,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)=0D @@ -322,6 +378,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x01) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)=0D @@ -400,6 +460,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "PRP0001") // _HID= : Hardware ID=0D Name (_UID, 0x00) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)=0D @@ -420,6 +484,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "PRP0001") // _HID= : Hardware ID=0D Name (_UID, 0x01) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xF4760000, 0x7D)=0D @@ -446,6 +514,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment=0D Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_PRT, Package () // _PRT: PCI Routing Table=0D {=0D Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl index 8377b13763..d6619e367b 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl @@ -20,6 +20,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU = ", "CN9131", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CLS, Package (0x03) // _CLS: Class Code=0D {=0D 0x01,=0D @@ -45,6 +49,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU = ", "CN9131", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x02) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -63,6 +71,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU = ", "CN9131", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x01) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl index d76a2a902b..536df8ab4b 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN91= 30", 3) {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x000) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU1)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x001) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU2)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x100) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU3)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x101) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D =0D Device (AHC0)=0D @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN913= 0", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CLS, Package (0x03) // _CLS: Class Code=0D {=0D 0x01,=0D @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN913= 0", 3) Name (_HID, "MRVL0003") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -98,6 +122,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN91= 30", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -126,6 +154,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -145,6 +177,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -163,6 +199,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) {=0D Name (_HID, "MRVL0001") // _HID: H= ardware ID=0D Name (_CID, "HISI0031") // _CID: C= ompatible ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress=0D Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings=0D {=0D @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) {=0D Name (_HID, "MRVL0100") // _HID: H= ardware ID=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite,=0D @@ -211,6 +255,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)=0D @@ -289,6 +337,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) {=0D Name (_HID, "PRP0001") // _HID= : Hardware ID=0D Name (_UID, 0x00) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)=0D @@ -315,6 +367,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_SEG, 0x00) // _SEG: PCI Segment=0D Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_PRT, Package () // _PRT: PCI Routing Table=0D {=0D Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D --=20 2.29.0