From: "Marcin Wojtas" <mw@semihalf.com>
To: devel@edk2.groups.io
Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com,
gjb@semihalf.com, upstream@semihalf.com,
Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com,
Marcin Wojtas <mw@semihalf.com>
Subject: [edk2-platforms PATCH 3/7] Marvell/Cn913xDbA: AcpiTables: Introduce DBG2 table
Date: Mon, 19 Jul 2021 11:30:11 +0200 [thread overview]
Message-ID: <20210719093015.1490932-4-mw@semihalf.com> (raw)
In-Reply-To: <20210719093015.1490932-1-mw@semihalf.com>
The DBG2 table is mandatory as per SBBR v1.2 specification.
Introduce it via CP0_UART0 interface.
Note: in order to use it, DPR58 and DPR59 must be switched to
positions 2-3.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 4 +-
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 1 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf | 1 +
| 2 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h | 9 +++
Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h | 2 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc | 74 ++++++++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 33 +++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc | 2 -
9 files changed, 124 insertions(+), 4 deletions(-)
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc
diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
index 33fb7ccc08..756d875f6c 100644
--- a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
+++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
@@ -32,8 +32,8 @@
gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 }
gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 0x3, 0x1, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x3, 0x9 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x9, 0x3, 0x7, 0x6, 0x7, 0x2, 0x2, 0x2, 0x2, 0x1 }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x3, 0xA }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x3, 0x7, 0x6, 0x7, 0x2, 0x2, 0x2, 0x2, 0x1 }
gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE }
gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf
index 191a747585..2cd13aa2b6 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf
@@ -18,6 +18,7 @@
VERSION_STRING = 1.0
[Sources]
+ Cn913xDbA/Dbg2.aslc
Cn913xDbA/Dsdt.asl
Cn913xDbA/Mcfg.aslc
Fadt.aslc
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
index bbf1b5133a..0c9fb82682 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
@@ -19,6 +19,7 @@
[Sources]
Cn9131DbA/Ssdt.asl
+ Cn913xDbA/Dbg2.aslc
Cn913xDbA/Dsdt.asl
Cn913xDbA/Mcfg.aslc
Fadt.aslc
--git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
index 283867692e..b93799dd03 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
@@ -11,6 +11,8 @@
#include <IndustryStandard/Acpi.h>
+#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACPI_5_0_BYTE, Address }
+
#define ACPI_OEM_ID_ARRAY {'M','V','E','B','U',' '}
#define ACPI_OEM_REVISION 0
#define ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O')
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h
new file mode 100644
index 0000000000..4584967016
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h
@@ -0,0 +1,9 @@
+/**
+
+ Copyright (C) 2021, Semihalf.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#define CN913X_DBG2_UART_REG_BASE 0xF2702000
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h b/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
index 6befe2ae54..83006ebd8a 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
@@ -22,6 +22,8 @@
#define CP_GIC_SPI_CP0_USB_H1 112
#define CP_GIC_SPI_CP0_USB_H0 113
#define CP_GIC_SPI_CP0_SATA_H0 114
+#define CP_GIC_SPI_CP0_UART0 121
+#define CP_GIC_SPI_CP0_UART1 122
#define CP_GIC_SPI_CP1_PCI0 288
#define CP_GIC_SPI_CP1_PCI1 289
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc
new file mode 100644
index 0000000000..bea55d0114
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc
@@ -0,0 +1,74 @@
+/** @file
+* Debug Port Table (DBG2)
+*
+* Copyright (c) 2020 Linaro Ltd. All rights reserved.
+* Copyright (c) 2021 ARM Ltd. All rights reserved.
+* Copyright (c) 2021 Semihalf. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/DebugPort2Table.h>
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+
+#include "AcpiHeader.h"
+#include "Cn913xDbA/Dbg2.h"
+
+#pragma pack(1)
+
+#define CN913X_UART_STR { '\\', '_', 'S', 'B', '.', 'C', 'O', 'M', '2', 0x00 }
+
+typedef struct {
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister;
+ UINT32 AddressSize;
+ UINT8 NameSpaceString[10];
+} DBG2_DEBUG_DEVICE_INFORMATION;
+
+typedef struct {
+ EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description;
+ DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo;
+} DBG2_TABLE;
+
+
+STATIC DBG2_TABLE Dbg2 = {
+ {
+ __ACPI_HEADER (
+ EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE,
+ DBG2_TABLE,
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION
+ ),
+ OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo),
+ 1 /* NumberOfDebugPorts */
+ },
+ {
+ {
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
+ sizeof (DBG2_DEBUG_DEVICE_INFORMATION),
+ 1, /* NumberofGenericAddressRegisters */
+ 10, /* NameSpaceStringLength */
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString),
+ 0, /* OemDataLength */
+ 0, /* OemDataOffset */
+ EFI_ACPI_DBG2_PORT_TYPE_SERIAL,
+ EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_SUBSET_COMPATIBLE_WITH_MS_DBGP_SPEC,
+ {
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE
+ },
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister),
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize)
+ },
+ MV_UART_AS32 (CN913X_DBG2_UART_REG_BASE), /* BaseAddress */
+ SIZE_4KB, /* AddressSize */
+ CN913X_UART_STR, /* NameSpaceString */
+ }
+};
+
+#pragma pack()
+
+// Reference the table being generated to prevent the optimizer from removing
+// the data structure from the executable
+VOID* CONST ReferenceAcpiTable = &Dbg2;
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
index 536df8ab4b..7335e443c6 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
@@ -9,6 +9,7 @@
**/
+#include "Cn913xDbA/Dbg2.h"
#include "Cn913xDbA/Pcie.h"
#include "IcuInterrupts.h"
@@ -199,6 +200,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
{
Name (_HID, "MRVL0001") // _HID: Hardware ID
Name (_CID, "HISI0031") // _CID: Compatible ID
+ Name (_UID, 0x00) // _UID: Unique ID
Method (_STA) // _STA: Device status
{
Return (0xF)
@@ -225,6 +227,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
})
}
+ Device (COM2)
+ {
+ Name (_HID, "MRVL0001") // _HID: Hardware ID
+ Name (_CID, "HISI0031") // _CID: Compatible ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_ADR, CN913X_DBG2_UART_REG_BASE) // _ADR: Address
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ CN913X_DBG2_UART_REG_BASE, // Address Base
+ 0x00000100, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP0_UART0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", FixedPcdGet32 (PcdSerialClockRate) },
+ Package () { "reg-io-width", 1 },
+ Package () { "reg-shift", 2 },
+ }
+ })
+ }
+
Device (SMI0)
{
Name (_HID, "MRVL0100") // _HID: Hardware ID
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc
index 2a3415f0a6..2dda2def81 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc
@@ -15,8 +15,6 @@
#include "AcpiHeader.h"
-#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACPI_5_0_BYTE, Address }
-
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
__ACPI_HEADER(EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
--
2.29.0
next prev parent reply other threads:[~2021-07-19 9:31 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-19 9:30 [edk2-platforms PATCH 0/7] Marvell ACS improvements Marcin Wojtas
2021-07-19 9:30 ` [edk2-platforms PATCH 1/7] Marvell: Armada7k8k: Add missing VariablePolicyHelperLib resolution Marcin Wojtas
2021-07-19 9:30 ` [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables Marcin Wojtas
2021-07-19 9:54 ` Ard Biesheuvel
2021-07-19 15:06 ` Marcin Wojtas
2021-07-29 9:46 ` Marcin Wojtas
2021-07-29 9:57 ` Ard Biesheuvel
2021-07-30 9:57 ` Marcin Wojtas
2021-08-01 16:58 ` Ard Biesheuvel
2021-08-10 14:36 ` Samer El-Haj-Mahmoud
2021-08-10 14:41 ` [edk2-devel] " Ard Biesheuvel
2021-08-10 15:01 ` Samer El-Haj-Mahmoud
2021-08-10 22:12 ` Marcin Wojtas
2021-07-19 9:30 ` Marcin Wojtas [this message]
2021-07-19 9:30 ` [edk2-platforms PATCH 4/7] SolidRun/Armada80x0McBin: AcpiTables: Introduce DBG2 table Marcin Wojtas
2021-07-19 9:30 ` [edk2-platforms PATCH 5/7] Marvell: Armada7k8k/OcteonTx: Switch to MonotonicCounterRuntimeDxe Marcin Wojtas
2021-07-19 9:30 ` [edk2-platforms PATCH 6/7] Marvell/Drivers: SmbiosPlatformDxe: Update Type0 information Marcin Wojtas
2021-07-19 9:30 ` [edk2-platforms PATCH 7/7] Marvell: Armada7k8k/OcteonTx: Bump firmware to "EDK2 SH 1.0" revision Marcin Wojtas
2021-08-01 17:14 ` [edk2-platforms PATCH 0/7] Marvell ACS improvements Ard Biesheuvel
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