From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) by mx.groups.io with SMTP id smtpd.web08.25752.1626687063028851700 for ; Mon, 19 Jul 2021 02:31:03 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=piSl5rJz; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.167.51, mailfrom: mw@semihalf.com) Received: by mail-lf1-f51.google.com with SMTP id i5so29131165lfe.2 for ; Mon, 19 Jul 2021 02:31:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3EJsrJgNpMOWc3WP4rvrgvbJ1FU5UAURQGmBE+iYsdc=; b=piSl5rJzUzYBpvaa2E72UjdWZ+V0t3gzQsUBs/+syh6cL4DogtgtR7mpTC574heDzK C+nwFbuv1ZQrbNtR71QmMM4dcaADC+19eq1geJXyGjRWjlJgic9D74Fpt2rX/+WJu/WX 2IcZw/7loMNoRLNzGg5u0UKvgzyONNQhBxibbB2frZ5gV20W4InPFXLEs9Y/9nmO6geF ZBV5zRyak2WIpK2GEtTuRaJLW44sk30t7uFm3N7VeseQrNfkfpf+oUoZPycc/DcCtD4f QewB7+pbRtv5M3o+ud99b87dNeZw43niakFjSTPlr/R65cvggyzJIK6GQHhClvXT0+A3 aoAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3EJsrJgNpMOWc3WP4rvrgvbJ1FU5UAURQGmBE+iYsdc=; b=ks/It3pZCsHpCoCbs6/PTp9Q8gZKa7EbrMd5kfmM/DzUDHTAMxGNCxwpoORjBTXAmM IbncxKyqI9f9ml7c3Else9ei64Ibpd4dXNLxbGSoCC0mBr5Nr3VdzBiE9t37xbTFuHHG EDFXyThNoATp38Zma6HD38Q627xnfkB/aXgMRZD60YkBvdBecizC3VhPRxbm/b5RJFps YpTAoOONZOFTVOS0ti9anFFSfn803awH5/g8PuXjY9kvNXLKqwBF8Vk3H/DbBx7xJU1z Va1jLdXOpcT+X0/CMTygNz7A1hSHdwnnqEMRIHRGljmqA9uDFDOh9w0bFLYw66Vx8kw7 +enQ== X-Gm-Message-State: AOAM531nMiu4G+IAkXipkwfO3fj+UOX0Bkv3RvrvCB+6xyjLXD2mdlOb P2sPnHidh7WHiQBtbebpF+Z9By98fwcgvkzS X-Google-Smtp-Source: ABdhPJwe4BhymFX+FzlQlOptBxgcDAnZYQUPcWhYu37TkaJuptWdRgiBz5ZvpxCvdBmM21BIJywx/Q== X-Received: by 2002:ac2:558f:: with SMTP id v15mr10130940lfg.326.1626687061216; Mon, 19 Jul 2021 02:31:01 -0700 (PDT) Return-Path: Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id u14sm1252560lfr.86.2021.07.19.02.31.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 02:31:00 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Marcin Wojtas Subject: [edk2-platforms PATCH 3/7] Marvell/Cn913xDbA: AcpiTables: Introduce DBG2 table Date: Mon, 19 Jul 2021 11:30:11 +0200 Message-Id: <20210719093015.1490932-4-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210719093015.1490932-1-mw@semihalf.com> References: <20210719093015.1490932-1-mw@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable The DBG2 table is mandatory as per SBBR v1.2 specification. Introduce it via CP0_UART0 interface. Note: in order to use it, DPR58 and DPR59 must be switched to positions 2-3. Signed-off-by: Marcin Wojtas --- Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 4 +- Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 1 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf | 1 + Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h | 2 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h | 9 +++ Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h | 2 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc | 74 +++++++++= +++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 33 +++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc | 2 - 9 files changed, 124 insertions(+), 4 deletions(-) create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.= aslc diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell= /Cn913xDb/Cn9130DbA.dsc.inc index 33fb7ccc08..756d875f6c 100644 --- a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc +++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc @@ -32,8 +32,8 @@ gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64=0D gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0= x3, 0x3, 0x3, 0x3 }=0D gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 0= x3, 0x1, 0x1, 0x1 }=0D - gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x3, 0x9 }=0D - gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x9, 0x3, 0x7, 0x6, 0x7, 0x2, 0= x2, 0x2, 0x2, 0x1 }=0D + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x3, 0xA }=0D + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x3, 0x7, 0x6, 0x7, 0x2, 0= x2, 0x2, 0x2, 0x1 }=0D gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 }=0D gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= xE, 0xE, 0xE, 0xE }=0D gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 }=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf b/Silico= n/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf index 191a747585..2cd13aa2b6 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf @@ -18,6 +18,7 @@ VERSION_STRING =3D 1.0=0D =0D [Sources]=0D + Cn913xDbA/Dbg2.aslc=0D Cn913xDbA/Dsdt.asl=0D Cn913xDbA/Mcfg.aslc=0D Fadt.aslc=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf b/Silico= n/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf index bbf1b5133a..0c9fb82682 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf @@ -19,6 +19,7 @@ =0D [Sources]=0D Cn9131DbA/Ssdt.asl=0D + Cn913xDbA/Dbg2.aslc=0D Cn913xDbA/Dsdt.asl=0D Cn913xDbA/Mcfg.aslc=0D Fadt.aslc=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h b/Silicon= /Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h index 283867692e..b93799dd03 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h @@ -11,6 +11,8 @@ =0D #include =0D =0D +#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACP= I_5_0_BYTE, Address }=0D +=0D #define ACPI_OEM_ID_ARRAY {'M','V','E','B','U',' '}=0D #define ACPI_OEM_REVISION 0=0D #define ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O')=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h b/Sil= icon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h new file mode 100644 index 0000000000..4584967016 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h @@ -0,0 +1,9 @@ +/**=0D +=0D + Copyright (C) 2021, Semihalf.=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#define CN913X_DBG2_UART_REG_BASE 0xF2702000=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h b/Sili= con/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h index 6befe2ae54..83006ebd8a 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h @@ -22,6 +22,8 @@ #define CP_GIC_SPI_CP0_USB_H1 112=0D #define CP_GIC_SPI_CP0_USB_H0 113=0D #define CP_GIC_SPI_CP0_SATA_H0 114=0D +#define CP_GIC_SPI_CP0_UART0 121=0D +#define CP_GIC_SPI_CP0_UART1 122=0D =0D #define CP_GIC_SPI_CP1_PCI0 288=0D #define CP_GIC_SPI_CP1_PCI1 289=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc b/= Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc new file mode 100644 index 0000000000..bea55d0114 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc @@ -0,0 +1,74 @@ +/** @file=0D +* Debug Port Table (DBG2)=0D +*=0D +* Copyright (c) 2020 Linaro Ltd. All rights reserved.=0D +* Copyright (c) 2021 ARM Ltd. All rights reserved.=0D +* Copyright (c) 2021 Semihalf. All rights reserved.=0D +*=0D +* SPDX-License-Identifier: BSD-2-Clause-Patent=0D +*=0D +**/=0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include "AcpiHeader.h"=0D +#include "Cn913xDbA/Dbg2.h"=0D +=0D +#pragma pack(1)=0D +=0D +#define CN913X_UART_STR { '\\', '_', 'S', 'B', '.', 'C', 'O', 'M', '2', 0x= 00 }=0D +=0D +typedef struct {=0D + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device;=0D + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister;=0D + UINT32 AddressSize;=0D + UINT8 NameSpaceString[10];=0D +} DBG2_DEBUG_DEVICE_INFORMATION;=0D +=0D +typedef struct {=0D + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description;=0D + DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo;=0D +} DBG2_TABLE;=0D +=0D +=0D +STATIC DBG2_TABLE Dbg2 =3D {=0D + {=0D + __ACPI_HEADER (=0D + EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE,=0D + DBG2_TABLE,=0D + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION=0D + ),=0D + OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo),=0D + 1 /* NumberOfDebugPorts */=0D + },=0D + {=0D + {=0D + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,=0D + sizeof (DBG2_DEBUG_DEVICE_INFORMATION),=0D + 1, /* NumberofGenericAddressRegist= ers */=0D + 10, /* NameSpaceStringLength */=0D + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString),=0D + 0, /* OemDataLength */=0D + 0, /* OemDataOffset */=0D + EFI_ACPI_DBG2_PORT_TYPE_SERIAL,=0D + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_SUBSET_COMPATIBLE_WITH_MS_DB= GP_SPEC,=0D + {=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE=0D + },=0D + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister),=0D + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize)=0D + },=0D + MV_UART_AS32 (CN913X_DBG2_UART_REG_BASE), /* BaseAddress */= =0D + SIZE_4KB, /* AddressSize */= =0D + CN913X_UART_STR, /* NameSpaceStrin= g */=0D + }=0D +};=0D +=0D +#pragma pack()=0D +=0D +// Reference the table being generated to prevent the optimizer from remov= ing=0D +// the data structure from the executable=0D +VOID* CONST ReferenceAcpiTable =3D &Dbg2;=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl index 536df8ab4b..7335e443c6 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl @@ -9,6 +9,7 @@ =0D **/=0D =0D +#include "Cn913xDbA/Dbg2.h"=0D #include "Cn913xDbA/Pcie.h"=0D #include "IcuInterrupts.h"=0D =0D @@ -199,6 +200,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN91= 30", 3) {=0D Name (_HID, "MRVL0001") // _HID: H= ardware ID=0D Name (_CID, "HISI0031") // _CID: C= ompatible ID=0D + Name (_UID, 0x00) // _UID: U= nique ID=0D Method (_STA) // _STA: D= evice status=0D {=0D Return (0xF)=0D @@ -225,6 +227,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) })=0D }=0D =0D + Device (COM2)=0D + {=0D + Name (_HID, "MRVL0001") // _HID: H= ardware ID=0D + Name (_CID, "HISI0031") // _CID: C= ompatible ID=0D + Name (_UID, 0x01) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_ADR, CN913X_DBG2_UART_REG_BASE) // _ADR: A= ddress=0D + Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings=0D + {=0D + Memory32Fixed (ReadWrite,=0D + CN913X_DBG2_UART_REG_BASE, // Address= Base=0D + 0x00000100, // Address= Length=0D + )=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, )=0D + {=0D + CP_GIC_SPI_CP0_UART0=0D + }=0D + })=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "clock-frequency", FixedPcdGet32 (PcdSe= rialClockRate) },=0D + Package () { "reg-io-width", 1 },=0D + Package () { "reg-shift", 2 },=0D + }=0D + })=0D + }=0D +=0D Device (SMI0)=0D {=0D Name (_HID, "MRVL0100") // _HID: H= ardware ID=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc b/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Spcr.aslc index 2a3415f0a6..2dda2def81 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc @@ -15,8 +15,6 @@ =0D #include "AcpiHeader.h"=0D =0D -#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACP= I_5_0_BYTE, Address }=0D -=0D EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr =3D {=0D __ACPI_HEADER(EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATU= RE,=0D EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,=0D --=20 2.29.0