* [edk2-platforms PATCH 0/7] Marvell ACS improvements
@ 2021-07-19 9:30 Marcin Wojtas
2021-07-19 9:30 ` [edk2-platforms PATCH 1/7] Marvell: Armada7k8k: Add missing VariablePolicyHelperLib resolution Marcin Wojtas
` (7 more replies)
0 siblings, 8 replies; 19+ messages in thread
From: Marcin Wojtas @ 2021-07-19 9:30 UTC (permalink / raw)
To: devel
Cc: leif, ardb+tianocore, jaz, gjb, upstream, Samer.El-Haj-Mahmoud,
jon, Marcin Wojtas
Hi,
This new series comes with the remaining improvements that allow
the ACS3.0 test suite to pass the SBSA/FWTS/SCT to the
maximum non-HW related extent. Missing _STA methods
and DBG2 description are added to the ACPI tables.
Moreover all platforms start using the maintained
MonotonicCounterRuntimeDxe. Also a build fix is added
for the VariablePolicyHelperLib resolution, that is
required after the recent changes in edk2.
Last but not least the SMBIOS Type0 description
is updated with the actual EDK2 firmare vendor and version
strings.
More details can be found in the commit logs.
The patchest is publicly available in the github:
https://github.com/semihalf-wojtas-marcin/edk2-platforms/commits/marvell-acs-r20210719
Best regards,
Marcin
Grzegorz Bernacki (2):
Marvell: Armada7k8k: Add missing VariablePolicyHelperLib resolution
Marvell: Armada7k8k/OcteonTx: Switch to MonotonicCounterRuntimeDxe
Marcin Wojtas (5):
Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables
Marvell/Cn913xDbA: AcpiTables: Introduce DBG2 table
SolidRun/Armada80x0McBin: AcpiTables: Introduce DBG2 table
Marvell/Drivers: SmbiosPlatformDxe: Update Type0 information
Marvell: Armada7k8k/OcteonTx: Bump firmware to "EDK2 SH 1.0" revision
Silicon/Marvell/Marvell.dec | 2 +
Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 4 +-
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 8 +-
Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 2 +-
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf | 1 +
Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 2 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 1 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf | 1 +
Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h | 2 +
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h | 9 ++
Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h | 2 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h | 2 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h | 9 ++
Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h | 2 +
Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 6 +-
Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 +++++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc | 74 ++++++++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 105 ++++++++++++++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc | 2 -
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 +++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc | 74 ++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 89 +++++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc | 2 -
24 files changed, 530 insertions(+), 13 deletions(-)
create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h
create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc
--
2.29.0
^ permalink raw reply [flat|nested] 19+ messages in thread* [edk2-platforms PATCH 1/7] Marvell: Armada7k8k: Add missing VariablePolicyHelperLib resolution 2021-07-19 9:30 [edk2-platforms PATCH 0/7] Marvell ACS improvements Marcin Wojtas @ 2021-07-19 9:30 ` Marcin Wojtas 2021-07-19 9:30 ` [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables Marcin Wojtas ` (6 subsequent siblings) 7 siblings, 0 replies; 19+ messages in thread From: Marcin Wojtas @ 2021-07-19 9:30 UTC (permalink / raw) To: devel Cc: leif, ardb+tianocore, jaz, gjb, upstream, Samer.El-Haj-Mahmoud, jon, Marcin Wojtas From: Grzegorz Bernacki <gjb@semihalf.com> The latest changes in MdeModulePkg/Universal/BdsDxe require VariablePolicyHelperLib resolution. Fix that for all platforms based on the Marvell SoCs. Signed-off-by: Marcin Wojtas <mw@semihalf.com> --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc index 939fbf14d9..c919d4bfab 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -175,6 +175,7 @@ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf [LibraryClasses.common.UEFI_APPLICATION] PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf @@ -197,6 +198,7 @@ !endif DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLibRuntimeDxe.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf [LibraryClasses.ARM, LibraryClasses.AARCH64] # @@ -563,7 +565,6 @@ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf - VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf } # UEFI application (Shell Embedded Boot Loader) -- 2.29.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables 2021-07-19 9:30 [edk2-platforms PATCH 0/7] Marvell ACS improvements Marcin Wojtas 2021-07-19 9:30 ` [edk2-platforms PATCH 1/7] Marvell: Armada7k8k: Add missing VariablePolicyHelperLib resolution Marcin Wojtas @ 2021-07-19 9:30 ` Marcin Wojtas 2021-07-19 9:54 ` Ard Biesheuvel 2021-07-19 9:30 ` [edk2-platforms PATCH 3/7] Marvell/Cn913xDbA: AcpiTables: Introduce DBG2 table Marcin Wojtas ` (5 subsequent siblings) 7 siblings, 1 reply; 19+ messages in thread From: Marcin Wojtas @ 2021-07-19 9:30 UTC (permalink / raw) To: devel Cc: leif, ardb+tianocore, jaz, gjb, upstream, Samer.El-Haj-Mahmoud, jon, Marcin Wojtas BBR 1.0 spec says that _STA is required for each device in DSDT or SSDT. Fix that for all platforms with the Marvell SoC's. Signed-off-by: Marcin Wojtas <mw@semihalf.com> --- Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 +++++++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++++++++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 72 +++++++++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 ++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 56 +++++++++++++++ 5 files changed, 272 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl index 345c1e4dd6..88e38efeeb 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID Name (_UID, 0x000) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU1) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID Name (_UID, 0x001) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU2) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID Name (_UID, 0x100) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID Name (_UID, 0x101) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (AHC0) @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -96,6 +120,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -123,6 +151,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -142,6 +174,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -160,6 +196,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) { Name (_HID, "MRVL0001") // _HID: Hardware ID Name (_CID, "HISI0031") // _CID: Compatible ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -186,6 +226,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) { Name (_HID, "MRVL0100") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -208,6 +252,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) Name (_HID, "MRVL0110") // _HID: Hardware ID Name (_CCA, 0x01) // Cache-coherent controller Name (_UID, 0x00) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) @@ -286,6 +334,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) { Name (_HID, "PRP0001") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) @@ -312,6 +364,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment Name (_BBN, 0x00) // _BBN: BIOS Bus Number Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_PRT, Package () // _PRT: PCI Routing Table { Package () { 0xFFFF, 0x0, 0x0, 0x40 }, diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl index 91401c74c8..77d3aebaf1 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID Name (_UID, 0x000) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU1) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID Name (_UID, 0x001) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU2) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID Name (_UID, 0x100) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID Name (_UID, 0x101) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (AHC0) @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -92,6 +116,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -122,6 +150,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -151,6 +183,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -170,6 +206,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x02) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -207,6 +251,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) { Name (_HID, "MRVL0001") // _HID: Hardware ID Name (_CID, "HISI0031") // _CID: Compatible ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -233,6 +281,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) { Name (_HID, "MRVL0100") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -251,6 +303,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) Name (_HID, "MRVL0110") // _HID: Hardware ID Name (_CCA, 0x01) // Cache-coherent controller Name (_UID, 0x00) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) @@ -309,6 +365,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) { Name (_HID, "MRVL0100") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -327,6 +387,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) Name (_HID, "MRVL0110") // _HID: Hardware ID Name (_CCA, 0x01) // Cache-coherent controller Name (_UID, 0x01) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) @@ -385,6 +449,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) { Name (_HID, "PRP0001") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) @@ -405,6 +473,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) { Name (_HID, "PRP0001") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) @@ -431,6 +503,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment Name (_BBN, 0x00) // _BBN: BIOS Bus Number Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_PRT, Package () // _PRT: PCI Routing Table { Package () { 0xFFFF, 0x0, 0x0, 0x40 }, diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl index d26945d933..1ecbd0309c 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl @@ -19,21 +19,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID Name (_UID, 0x000) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU1) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID Name (_UID, 0x001) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU2) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID Name (_UID, 0x100) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID Name (_UID, 0x101) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (AHC0) @@ -41,6 +57,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -91,6 +111,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -122,6 +146,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -150,6 +178,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -169,6 +201,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -188,6 +224,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x02) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -206,6 +246,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) { Name (_HID, "MRVL0001") // _HID: Hardware ID Name (_CID, "HISI0031") // _CID: Compatible ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -232,6 +276,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) { Name (_HID, "MRVL0100") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -249,6 +297,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) { Name (_HID, "MRVL0101") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -283,6 +335,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) Name (_HID, "MRVL0110") // _HID: Hardware ID Name (_CCA, 0x01) // Cache-coherent controller Name (_UID, 0x00) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) @@ -322,6 +378,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) Name (_HID, "MRVL0110") // _HID: Hardware ID Name (_CCA, 0x01) // Cache-coherent controller Name (_UID, 0x01) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) @@ -400,6 +460,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) { Name (_HID, "PRP0001") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) @@ -420,6 +484,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) { Name (_HID, "PRP0001") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) @@ -446,6 +514,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment Name (_BBN, 0x00) // _BBN: BIOS Bus Number Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_PRT, Package () // _PRT: PCI Routing Table { Package () { 0xFFFF, 0x0, 0x0, 0x40 }, diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl index 8377b13763..d6619e367b 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl @@ -20,6 +20,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -45,6 +49,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x02) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -63,6 +71,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) Name (_HID, "MRVL0110") // _HID: Hardware ID Name (_CCA, 0x01) // Cache-coherent controller Name (_UID, 0x01) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl index d76a2a902b..536df8ab4b 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID Name (_UID, 0x000) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU1) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID Name (_UID, 0x001) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU2) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID Name (_UID, 0x100) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID Name (_UID, 0x101) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (AHC0) @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) Name (_HID, "MRVL0003") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -98,6 +122,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -126,6 +154,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -145,6 +177,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -163,6 +199,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) { Name (_HID, "MRVL0001") // _HID: Hardware ID Name (_CID, "HISI0031") // _CID: Compatible ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) { Name (_HID, "MRVL0100") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -211,6 +255,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) Name (_HID, "MRVL0110") // _HID: Hardware ID Name (_CCA, 0x01) // Cache-coherent controller Name (_UID, 0x00) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) @@ -289,6 +337,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) { Name (_HID, "PRP0001") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) @@ -315,6 +367,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) Name (_SEG, 0x00) // _SEG: PCI Segment Name (_BBN, 0x00) // _BBN: BIOS Bus Number Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_PRT, Package () // _PRT: PCI Routing Table { Package () { 0xFFFF, 0x0, 0x0, 0x40 }, -- 2.29.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables 2021-07-19 9:30 ` [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables Marcin Wojtas @ 2021-07-19 9:54 ` Ard Biesheuvel 2021-07-19 15:06 ` Marcin Wojtas 0 siblings, 1 reply; 19+ messages in thread From: Ard Biesheuvel @ 2021-07-19 9:54 UTC (permalink / raw) To: Marcin Wojtas, Samer El-Haj-Mahmoud Cc: edk2-devel-groups-io, Leif Lindholm, Ard Biesheuvel, Grzegorz Jaszczyk, Grzegorz Bernacki, upstream, Jon Nettleton On Mon, 19 Jul 2021 at 11:31, Marcin Wojtas <mw@semihalf.com> wrote: > > BBR 1.0 spec says that _STA is required for each device in DSDT or SSDT. > Fix that for all platforms with the Marvell SoC's. > Can we fix the BBR instead? If ACPI itself does not require _STA, BBR should not require it either. > Signed-off-by: Marcin Wojtas <mw@semihalf.com> > --- > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 +++++++++++++++ > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++++++++++++++++ > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 72 +++++++++++++++++++ > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 ++++ > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 56 +++++++++++++++ > 5 files changed, 272 insertions(+) > > diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > index 345c1e4dd6..88e38efeeb 100644 > --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > { > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > Name (_UID, 0x000) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > } > Device (CPU1) > { > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > Name (_UID, 0x001) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > } > Device (CPU2) > { > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > Name (_UID, 0x100) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > } > Device (CPU3) > { > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > Name (_UID, 0x101) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > } > > Device (AHC0) > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > Name (_HID, "LNRO001E") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CLS, Package (0x03) // _CLS: Class Code > { > 0x01, > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > Name (_HID, "MRVL0002") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -96,6 +120,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > Name (_HID, "MRVL0004") // _HID: Hardware ID > Name (_UID, 0x01) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -123,6 +151,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > Name (_HID, "PNP0D10") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -142,6 +174,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > Name (_HID, "PNP0D10") // _HID: Hardware ID > Name (_UID, 0x01) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -160,6 +196,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > { > Name (_HID, "MRVL0001") // _HID: Hardware ID > Name (_CID, "HISI0031") // _CID: Compatible ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -186,6 +226,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > { > Name (_HID, "MRVL0100") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CRS, ResourceTemplate () > { > Memory32Fixed (ReadWrite, > @@ -208,6 +252,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > Name (_HID, "MRVL0110") // _HID: Hardware ID > Name (_CCA, 0x01) // Cache-coherent controller > Name (_UID, 0x00) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CRS, ResourceTemplate () > { > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > @@ -286,6 +334,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > { > Name (_HID, "PRP0001") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CRS, ResourceTemplate () > { > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > @@ -312,6 +364,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > Name (_SEG, 0x00) // _SEG: PCI Segment > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_PRT, Package () // _PRT: PCI Routing Table > { > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > index 91401c74c8..77d3aebaf1 100644 > --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > { > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > Name (_UID, 0x000) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > } > Device (CPU1) > { > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > Name (_UID, 0x001) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > } > Device (CPU2) > { > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > Name (_UID, 0x100) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > } > Device (CPU3) > { > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > Name (_UID, 0x101) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > } > > Device (AHC0) > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > Name (_HID, "LNRO001E") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CLS, Package (0x03) // _CLS: Class Code > { > 0x01, > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > Name (_HID, "LNRO001E") // _HID: Hardware ID > Name (_UID, 0x01) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CLS, Package (0x03) // _CLS: Class Code > { > 0x01, > @@ -92,6 +116,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > Name (_HID, "MRVL0002") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -122,6 +150,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > Name (_HID, "MRVL0004") // _HID: Hardware ID > Name (_UID, 0x01) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -151,6 +183,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > Name (_HID, "PNP0D10") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -170,6 +206,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > Name (_HID, "PNP0D10") // _HID: Hardware ID > Name (_UID, 0x01) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > Name (_HID, "PNP0D10") // _HID: Hardware ID > Name (_UID, 0x02) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -207,6 +251,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > { > Name (_HID, "MRVL0001") // _HID: Hardware ID > Name (_CID, "HISI0031") // _CID: Compatible ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -233,6 +281,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > { > Name (_HID, "MRVL0100") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CRS, ResourceTemplate () > { > Memory32Fixed (ReadWrite, > @@ -251,6 +303,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > Name (_HID, "MRVL0110") // _HID: Hardware ID > Name (_CCA, 0x01) // Cache-coherent controller > Name (_UID, 0x00) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CRS, ResourceTemplate () > { > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > @@ -309,6 +365,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > { > Name (_HID, "MRVL0100") // _HID: Hardware ID > Name (_UID, 0x01) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CRS, ResourceTemplate () > { > Memory32Fixed (ReadWrite, > @@ -327,6 +387,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > Name (_HID, "MRVL0110") // _HID: Hardware ID > Name (_CCA, 0x01) // Cache-coherent controller > Name (_UID, 0x01) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CRS, ResourceTemplate () > { > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > @@ -385,6 +449,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > { > Name (_HID, "PRP0001") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CRS, ResourceTemplate () > { > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > @@ -405,6 +473,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > { > Name (_HID, "PRP0001") // _HID: Hardware ID > Name (_UID, 0x01) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CRS, ResourceTemplate () > { > Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) > @@ -431,6 +503,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > Name (_SEG, 0x00) // _SEG: PCI Segment > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_PRT, Package () // _PRT: PCI Routing Table > { > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > index d26945d933..1ecbd0309c 100644 > --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > @@ -19,21 +19,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > { > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > Name (_UID, 0x000) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > } > Device (CPU1) > { > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > Name (_UID, 0x001) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > } > Device (CPU2) > { > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > Name (_UID, 0x100) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > } > Device (CPU3) > { > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > Name (_UID, 0x101) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > } > > Device (AHC0) > @@ -41,6 +57,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > Name (_HID, "LNRO001E") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CLS, Package (0x03) // _CLS: Class Code > { > 0x01, > @@ -91,6 +111,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > Name (_HID, "MRVL0002") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -122,6 +146,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > Name (_HID, "MRVL0004") // _HID: Hardware ID > Name (_UID, 0x01) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -150,6 +178,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > Name (_HID, "PNP0D10") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -169,6 +201,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > Name (_HID, "PNP0D10") // _HID: Hardware ID > Name (_UID, 0x01) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -188,6 +224,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > Name (_HID, "PNP0D10") // _HID: Hardware ID > Name (_UID, 0x02) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -206,6 +246,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > { > Name (_HID, "MRVL0001") // _HID: Hardware ID > Name (_CID, "HISI0031") // _CID: Compatible ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -232,6 +276,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > { > Name (_HID, "MRVL0100") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CRS, ResourceTemplate () > { > Memory32Fixed (ReadWrite, > @@ -249,6 +297,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > { > Name (_HID, "MRVL0101") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CRS, ResourceTemplate () > { > Memory32Fixed (ReadWrite, > @@ -283,6 +335,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > Name (_HID, "MRVL0110") // _HID: Hardware ID > Name (_CCA, 0x01) // Cache-coherent controller > Name (_UID, 0x00) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CRS, ResourceTemplate () > { > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > @@ -322,6 +378,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > Name (_HID, "MRVL0110") // _HID: Hardware ID > Name (_CCA, 0x01) // Cache-coherent controller > Name (_UID, 0x01) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CRS, ResourceTemplate () > { > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > @@ -400,6 +460,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > { > Name (_HID, "PRP0001") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CRS, ResourceTemplate () > { > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > @@ -420,6 +484,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > { > Name (_HID, "PRP0001") // _HID: Hardware ID > Name (_UID, 0x01) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CRS, ResourceTemplate () > { > Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) > @@ -446,6 +514,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > Name (_SEG, 0x00) // _SEG: PCI Segment > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_PRT, Package () // _PRT: PCI Routing Table > { > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > index 8377b13763..d6619e367b 100644 > --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > @@ -20,6 +20,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) > Name (_HID, "LNRO001E") // _HID: Hardware ID > Name (_UID, 0x01) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CLS, Package (0x03) // _CLS: Class Code > { > 0x01, > @@ -45,6 +49,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) > Name (_HID, "PNP0D10") // _HID: Hardware ID > Name (_UID, 0x02) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -63,6 +71,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) > Name (_HID, "MRVL0110") // _HID: Hardware ID > Name (_CCA, 0x01) // Cache-coherent controller > Name (_UID, 0x01) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CRS, ResourceTemplate () > { > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > index d76a2a902b..536df8ab4b 100644 > --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > { > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > Name (_UID, 0x000) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > } > Device (CPU1) > { > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > Name (_UID, 0x001) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > } > Device (CPU2) > { > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > Name (_UID, 0x100) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > } > Device (CPU3) > { > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > Name (_UID, 0x101) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > } > > Device (AHC0) > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > Name (_HID, "LNRO001E") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CLS, Package (0x03) // _CLS: Class Code > { > 0x01, > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > Name (_HID, "MRVL0003") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -98,6 +122,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > Name (_HID, "MRVL0004") // _HID: Hardware ID > Name (_UID, 0x01) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -126,6 +154,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > Name (_HID, "PNP0D10") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -145,6 +177,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > Name (_HID, "PNP0D10") // _HID: Hardware ID > Name (_UID, 0x01) // _UID: Unique ID > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -163,6 +199,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > { > Name (_HID, "MRVL0001") // _HID: Hardware ID > Name (_CID, "HISI0031") // _CID: Compatible ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > { > @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > { > Name (_HID, "MRVL0100") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CRS, ResourceTemplate () > { > Memory32Fixed (ReadWrite, > @@ -211,6 +255,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > Name (_HID, "MRVL0110") // _HID: Hardware ID > Name (_CCA, 0x01) // Cache-coherent controller > Name (_UID, 0x00) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CRS, ResourceTemplate () > { > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > @@ -289,6 +337,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > { > Name (_HID, "PRP0001") // _HID: Hardware ID > Name (_UID, 0x00) // _UID: Unique ID > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_CRS, ResourceTemplate () > { > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > @@ -315,6 +367,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > Name (_SEG, 0x00) // _SEG: PCI Segment > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > + Method (_STA) // _STA: Device status > + { > + Return (0xF) > + } > Name (_PRT, Package () // _PRT: PCI Routing Table > { > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > -- > 2.29.0 > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables 2021-07-19 9:54 ` Ard Biesheuvel @ 2021-07-19 15:06 ` Marcin Wojtas 2021-07-29 9:46 ` Marcin Wojtas 0 siblings, 1 reply; 19+ messages in thread From: Marcin Wojtas @ 2021-07-19 15:06 UTC (permalink / raw) To: Ard Biesheuvel Cc: Samer El-Haj-Mahmoud, edk2-devel-groups-io, Leif Lindholm, Ard Biesheuvel, Grzegorz Jaszczyk, Grzegorz Bernacki, upstream, Jon Nettleton Hi Ard, pon., 19 lip 2021 o 11:54 Ard Biesheuvel <ardb@kernel.org> napisał(a): > > On Mon, 19 Jul 2021 at 11:31, Marcin Wojtas <mw@semihalf.com> wrote: > > > > BBR 1.0 spec says that _STA is required for each device in DSDT or SSDT. > > Fix that for all platforms with the Marvell SoC's. > > > > Can we fix the BBR instead? If ACPI itself does not require _STA, BBR > should not require it either. > > I consulted with ARM on the matter. SBBR has requirements of things that are otherwise optional in UEFI/ACPI/SMBIOS. Also some OS's may require that and I can see those methods in most of the other ACPI source files in the edk2-platfoms tree. I think the BBR requirements discussions can follow, but it would be great if this change can be applied, so that no to block other development. Best regards, Marcin > > > Signed-off-by: Marcin Wojtas <mw@semihalf.com> > > --- > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 +++++++++++++++ > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++++++++++++++++ > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 72 +++++++++++++++++++ > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 ++++ > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 56 +++++++++++++++ > > 5 files changed, 272 insertions(+) > > > > diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > > index 345c1e4dd6..88e38efeeb 100644 > > --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > > +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > { > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > Name (_UID, 0x000) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > } > > Device (CPU1) > > { > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > Name (_UID, 0x001) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > } > > Device (CPU2) > > { > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > Name (_UID, 0x100) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > } > > Device (CPU3) > > { > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > Name (_UID, 0x101) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > } > > > > Device (AHC0) > > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CLS, Package (0x03) // _CLS: Class Code > > { > > 0x01, > > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > Name (_HID, "MRVL0002") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -96,6 +120,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > Name (_UID, 0x01) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -123,6 +151,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -142,6 +174,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > Name (_UID, 0x01) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -160,6 +196,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > { > > Name (_HID, "MRVL0001") // _HID: Hardware ID > > Name (_CID, "HISI0031") // _CID: Compatible ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -186,6 +226,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > { > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CRS, ResourceTemplate () > > { > > Memory32Fixed (ReadWrite, > > @@ -208,6 +252,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > Name (_CCA, 0x01) // Cache-coherent controller > > Name (_UID, 0x00) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CRS, ResourceTemplate () > > { > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > @@ -286,6 +334,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > { > > Name (_HID, "PRP0001") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CRS, ResourceTemplate () > > { > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > @@ -312,6 +364,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > Name (_SEG, 0x00) // _SEG: PCI Segment > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_PRT, Package () // _PRT: PCI Routing Table > > { > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > > index 91401c74c8..77d3aebaf1 100644 > > --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > > +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > { > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > Name (_UID, 0x000) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > } > > Device (CPU1) > > { > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > Name (_UID, 0x001) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > } > > Device (CPU2) > > { > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > Name (_UID, 0x100) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > } > > Device (CPU3) > > { > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > Name (_UID, 0x101) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > } > > > > Device (AHC0) > > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CLS, Package (0x03) // _CLS: Class Code > > { > > 0x01, > > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > Name (_UID, 0x01) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CLS, Package (0x03) // _CLS: Class Code > > { > > 0x01, > > @@ -92,6 +116,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > Name (_HID, "MRVL0002") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -122,6 +150,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > Name (_UID, 0x01) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -151,6 +183,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -170,6 +206,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > Name (_UID, 0x01) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > Name (_UID, 0x02) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -207,6 +251,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > { > > Name (_HID, "MRVL0001") // _HID: Hardware ID > > Name (_CID, "HISI0031") // _CID: Compatible ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -233,6 +281,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > { > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CRS, ResourceTemplate () > > { > > Memory32Fixed (ReadWrite, > > @@ -251,6 +303,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > Name (_CCA, 0x01) // Cache-coherent controller > > Name (_UID, 0x00) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CRS, ResourceTemplate () > > { > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > @@ -309,6 +365,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > { > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > Name (_UID, 0x01) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CRS, ResourceTemplate () > > { > > Memory32Fixed (ReadWrite, > > @@ -327,6 +387,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > Name (_CCA, 0x01) // Cache-coherent controller > > Name (_UID, 0x01) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CRS, ResourceTemplate () > > { > > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > > @@ -385,6 +449,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > { > > Name (_HID, "PRP0001") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CRS, ResourceTemplate () > > { > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > @@ -405,6 +473,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > { > > Name (_HID, "PRP0001") // _HID: Hardware ID > > Name (_UID, 0x01) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CRS, ResourceTemplate () > > { > > Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) > > @@ -431,6 +503,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > Name (_SEG, 0x00) // _SEG: PCI Segment > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_PRT, Package () // _PRT: PCI Routing Table > > { > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > > index d26945d933..1ecbd0309c 100644 > > --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > > +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > > @@ -19,21 +19,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > { > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > Name (_UID, 0x000) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > } > > Device (CPU1) > > { > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > Name (_UID, 0x001) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > } > > Device (CPU2) > > { > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > Name (_UID, 0x100) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > } > > Device (CPU3) > > { > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > Name (_UID, 0x101) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > } > > > > Device (AHC0) > > @@ -41,6 +57,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CLS, Package (0x03) // _CLS: Class Code > > { > > 0x01, > > @@ -91,6 +111,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > Name (_HID, "MRVL0002") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -122,6 +146,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > Name (_UID, 0x01) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -150,6 +178,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -169,6 +201,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > Name (_UID, 0x01) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -188,6 +224,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > Name (_UID, 0x02) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -206,6 +246,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > { > > Name (_HID, "MRVL0001") // _HID: Hardware ID > > Name (_CID, "HISI0031") // _CID: Compatible ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -232,6 +276,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > { > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CRS, ResourceTemplate () > > { > > Memory32Fixed (ReadWrite, > > @@ -249,6 +297,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > { > > Name (_HID, "MRVL0101") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CRS, ResourceTemplate () > > { > > Memory32Fixed (ReadWrite, > > @@ -283,6 +335,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > Name (_CCA, 0x01) // Cache-coherent controller > > Name (_UID, 0x00) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CRS, ResourceTemplate () > > { > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > @@ -322,6 +378,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > Name (_CCA, 0x01) // Cache-coherent controller > > Name (_UID, 0x01) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CRS, ResourceTemplate () > > { > > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > > @@ -400,6 +460,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > { > > Name (_HID, "PRP0001") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CRS, ResourceTemplate () > > { > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > @@ -420,6 +484,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > { > > Name (_HID, "PRP0001") // _HID: Hardware ID > > Name (_UID, 0x01) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CRS, ResourceTemplate () > > { > > Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) > > @@ -446,6 +514,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > Name (_SEG, 0x00) // _SEG: PCI Segment > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_PRT, Package () // _PRT: PCI Routing Table > > { > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > > index 8377b13763..d6619e367b 100644 > > --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > > +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > > @@ -20,6 +20,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > Name (_UID, 0x01) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CLS, Package (0x03) // _CLS: Class Code > > { > > 0x01, > > @@ -45,6 +49,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > Name (_UID, 0x02) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -63,6 +71,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > Name (_CCA, 0x01) // Cache-coherent controller > > Name (_UID, 0x01) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CRS, ResourceTemplate () > > { > > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > > diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > > index d76a2a902b..536df8ab4b 100644 > > --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > > +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > { > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > Name (_UID, 0x000) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > } > > Device (CPU1) > > { > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > Name (_UID, 0x001) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > } > > Device (CPU2) > > { > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > Name (_UID, 0x100) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > } > > Device (CPU3) > > { > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > Name (_UID, 0x101) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > } > > > > Device (AHC0) > > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CLS, Package (0x03) // _CLS: Class Code > > { > > 0x01, > > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > Name (_HID, "MRVL0003") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -98,6 +122,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > Name (_UID, 0x01) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -126,6 +154,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -145,6 +177,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > Name (_UID, 0x01) // _UID: Unique ID > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -163,6 +199,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > { > > Name (_HID, "MRVL0001") // _HID: Hardware ID > > Name (_CID, "HISI0031") // _CID: Compatible ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > { > > @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > { > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CRS, ResourceTemplate () > > { > > Memory32Fixed (ReadWrite, > > @@ -211,6 +255,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > Name (_CCA, 0x01) // Cache-coherent controller > > Name (_UID, 0x00) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CRS, ResourceTemplate () > > { > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > @@ -289,6 +337,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > { > > Name (_HID, "PRP0001") // _HID: Hardware ID > > Name (_UID, 0x00) // _UID: Unique ID > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_CRS, ResourceTemplate () > > { > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > @@ -315,6 +367,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > Name (_SEG, 0x00) // _SEG: PCI Segment > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > + Method (_STA) // _STA: Device status > > + { > > + Return (0xF) > > + } > > Name (_PRT, Package () // _PRT: PCI Routing Table > > { > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > -- > > 2.29.0 > > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables 2021-07-19 15:06 ` Marcin Wojtas @ 2021-07-29 9:46 ` Marcin Wojtas 2021-07-29 9:57 ` Ard Biesheuvel 0 siblings, 1 reply; 19+ messages in thread From: Marcin Wojtas @ 2021-07-29 9:46 UTC (permalink / raw) To: Ard Biesheuvel Cc: Samer El-Haj-Mahmoud, edk2-devel-groups-io, Leif Lindholm, Ard Biesheuvel, Grzegorz Jaszczyk, Grzegorz Bernacki, upstream, Jon Nettleton Hi Ard, pon., 19 lip 2021 o 17:06 Marcin Wojtas <mw@semihalf.com> napisał(a): > > Hi Ard, > > pon., 19 lip 2021 o 11:54 Ard Biesheuvel <ardb@kernel.org> napisał(a): > > > > On Mon, 19 Jul 2021 at 11:31, Marcin Wojtas <mw@semihalf.com> wrote: > > > > > > BBR 1.0 spec says that _STA is required for each device in DSDT or SSDT. > > > Fix that for all platforms with the Marvell SoC's. > > > > > > > Can we fix the BBR instead? If ACPI itself does not require _STA, BBR > > should not require it either. > > > > > > I consulted with ARM on the matter. SBBR has requirements of things > that are otherwise optional in UEFI/ACPI/SMBIOS. Also some OS's may > require that and I can see those methods in most of the other ACPI > source files in the edk2-platfoms tree. I think the BBR requirements > discussions can follow, but it would be great if this change can be > applied, so that no to block other development. > Do you have any feedback to the patchset and the _STA methods concerns? Best regards, Marcin > > > > > > Signed-off-by: Marcin Wojtas <mw@semihalf.com> > > > --- > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 +++++++++++++++ > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++++++++++++++++ > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 72 +++++++++++++++++++ > > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 ++++ > > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 56 +++++++++++++++ > > > 5 files changed, 272 insertions(+) > > > > > > diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > > > index 345c1e4dd6..88e38efeeb 100644 > > > --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > > > +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > > > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > { > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > Name (_UID, 0x000) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > } > > > Device (CPU1) > > > { > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > Name (_UID, 0x001) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > } > > > Device (CPU2) > > > { > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > Name (_UID, 0x100) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > } > > > Device (CPU3) > > > { > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > Name (_UID, 0x101) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > } > > > > > > Device (AHC0) > > > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > { > > > 0x01, > > > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > Name (_HID, "MRVL0002") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -96,6 +120,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > > Name (_UID, 0x01) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -123,6 +151,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -142,6 +174,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > Name (_UID, 0x01) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -160,6 +196,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > { > > > Name (_HID, "MRVL0001") // _HID: Hardware ID > > > Name (_CID, "HISI0031") // _CID: Compatible ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -186,6 +226,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > { > > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CRS, ResourceTemplate () > > > { > > > Memory32Fixed (ReadWrite, > > > @@ -208,6 +252,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > Name (_CCA, 0x01) // Cache-coherent controller > > > Name (_UID, 0x00) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CRS, ResourceTemplate () > > > { > > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > > @@ -286,6 +334,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > { > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CRS, ResourceTemplate () > > > { > > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > > @@ -312,6 +364,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > Name (_SEG, 0x00) // _SEG: PCI Segment > > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_PRT, Package () // _PRT: PCI Routing Table > > > { > > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > > diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > > > index 91401c74c8..77d3aebaf1 100644 > > > --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > > > +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > > > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > { > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > Name (_UID, 0x000) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > } > > > Device (CPU1) > > > { > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > Name (_UID, 0x001) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > } > > > Device (CPU2) > > > { > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > Name (_UID, 0x100) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > } > > > Device (CPU3) > > > { > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > Name (_UID, 0x101) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > } > > > > > > Device (AHC0) > > > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > { > > > 0x01, > > > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > Name (_UID, 0x01) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > { > > > 0x01, > > > @@ -92,6 +116,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > Name (_HID, "MRVL0002") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -122,6 +150,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > > Name (_UID, 0x01) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -151,6 +183,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -170,6 +206,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > Name (_UID, 0x01) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > Name (_UID, 0x02) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -207,6 +251,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > { > > > Name (_HID, "MRVL0001") // _HID: Hardware ID > > > Name (_CID, "HISI0031") // _CID: Compatible ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -233,6 +281,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > { > > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CRS, ResourceTemplate () > > > { > > > Memory32Fixed (ReadWrite, > > > @@ -251,6 +303,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > Name (_CCA, 0x01) // Cache-coherent controller > > > Name (_UID, 0x00) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CRS, ResourceTemplate () > > > { > > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > > @@ -309,6 +365,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > { > > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > > Name (_UID, 0x01) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CRS, ResourceTemplate () > > > { > > > Memory32Fixed (ReadWrite, > > > @@ -327,6 +387,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > Name (_CCA, 0x01) // Cache-coherent controller > > > Name (_UID, 0x01) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CRS, ResourceTemplate () > > > { > > > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > > > @@ -385,6 +449,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > { > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CRS, ResourceTemplate () > > > { > > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > > @@ -405,6 +473,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > { > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > Name (_UID, 0x01) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CRS, ResourceTemplate () > > > { > > > Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) > > > @@ -431,6 +503,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > Name (_SEG, 0x00) // _SEG: PCI Segment > > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_PRT, Package () // _PRT: PCI Routing Table > > > { > > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > > diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > > > index d26945d933..1ecbd0309c 100644 > > > --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > > > +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > > > @@ -19,21 +19,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > { > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > Name (_UID, 0x000) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > } > > > Device (CPU1) > > > { > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > Name (_UID, 0x001) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > } > > > Device (CPU2) > > > { > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > Name (_UID, 0x100) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > } > > > Device (CPU3) > > > { > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > Name (_UID, 0x101) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > } > > > > > > Device (AHC0) > > > @@ -41,6 +57,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > { > > > 0x01, > > > @@ -91,6 +111,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > Name (_HID, "MRVL0002") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -122,6 +146,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > > Name (_UID, 0x01) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -150,6 +178,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -169,6 +201,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > Name (_UID, 0x01) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -188,6 +224,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > Name (_UID, 0x02) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -206,6 +246,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > { > > > Name (_HID, "MRVL0001") // _HID: Hardware ID > > > Name (_CID, "HISI0031") // _CID: Compatible ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -232,6 +276,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > { > > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CRS, ResourceTemplate () > > > { > > > Memory32Fixed (ReadWrite, > > > @@ -249,6 +297,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > { > > > Name (_HID, "MRVL0101") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CRS, ResourceTemplate () > > > { > > > Memory32Fixed (ReadWrite, > > > @@ -283,6 +335,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > Name (_CCA, 0x01) // Cache-coherent controller > > > Name (_UID, 0x00) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CRS, ResourceTemplate () > > > { > > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > > @@ -322,6 +378,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > Name (_CCA, 0x01) // Cache-coherent controller > > > Name (_UID, 0x01) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CRS, ResourceTemplate () > > > { > > > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > > > @@ -400,6 +460,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > { > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CRS, ResourceTemplate () > > > { > > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > > @@ -420,6 +484,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > { > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > Name (_UID, 0x01) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CRS, ResourceTemplate () > > > { > > > Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) > > > @@ -446,6 +514,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > Name (_SEG, 0x00) // _SEG: PCI Segment > > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_PRT, Package () // _PRT: PCI Routing Table > > > { > > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > > diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > > > index 8377b13763..d6619e367b 100644 > > > --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > > > +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > > > @@ -20,6 +20,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > Name (_UID, 0x01) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > { > > > 0x01, > > > @@ -45,6 +49,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > Name (_UID, 0x02) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -63,6 +71,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > Name (_CCA, 0x01) // Cache-coherent controller > > > Name (_UID, 0x01) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CRS, ResourceTemplate () > > > { > > > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > > > diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > > > index d76a2a902b..536df8ab4b 100644 > > > --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > > > +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > > > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > { > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > Name (_UID, 0x000) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > } > > > Device (CPU1) > > > { > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > Name (_UID, 0x001) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > } > > > Device (CPU2) > > > { > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > Name (_UID, 0x100) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > } > > > Device (CPU3) > > > { > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > Name (_UID, 0x101) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > } > > > > > > Device (AHC0) > > > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > { > > > 0x01, > > > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > Name (_HID, "MRVL0003") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -98,6 +122,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > > Name (_UID, 0x01) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -126,6 +154,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -145,6 +177,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > Name (_UID, 0x01) // _UID: Unique ID > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -163,6 +199,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > { > > > Name (_HID, "MRVL0001") // _HID: Hardware ID > > > Name (_CID, "HISI0031") // _CID: Compatible ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > { > > > @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > { > > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CRS, ResourceTemplate () > > > { > > > Memory32Fixed (ReadWrite, > > > @@ -211,6 +255,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > Name (_CCA, 0x01) // Cache-coherent controller > > > Name (_UID, 0x00) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CRS, ResourceTemplate () > > > { > > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > > @@ -289,6 +337,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > { > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > Name (_UID, 0x00) // _UID: Unique ID > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_CRS, ResourceTemplate () > > > { > > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > > @@ -315,6 +367,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > Name (_SEG, 0x00) // _SEG: PCI Segment > > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > + Method (_STA) // _STA: Device status > > > + { > > > + Return (0xF) > > > + } > > > Name (_PRT, Package () // _PRT: PCI Routing Table > > > { > > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > > -- > > > 2.29.0 > > > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables 2021-07-29 9:46 ` Marcin Wojtas @ 2021-07-29 9:57 ` Ard Biesheuvel 2021-07-30 9:57 ` Marcin Wojtas 0 siblings, 1 reply; 19+ messages in thread From: Ard Biesheuvel @ 2021-07-29 9:57 UTC (permalink / raw) To: Marcin Wojtas Cc: Samer El-Haj-Mahmoud, edk2-devel-groups-io, Leif Lindholm, Ard Biesheuvel, Grzegorz Jaszczyk, Grzegorz Bernacki, upstream, Jon Nettleton On Thu, 29 Jul 2021 at 11:46, Marcin Wojtas <mw@semihalf.com> wrote: > > Hi Ard, > > pon., 19 lip 2021 o 17:06 Marcin Wojtas <mw@semihalf.com> napisał(a): > > > > Hi Ard, > > > > pon., 19 lip 2021 o 11:54 Ard Biesheuvel <ardb@kernel.org> napisał(a): > > > > > > On Mon, 19 Jul 2021 at 11:31, Marcin Wojtas <mw@semihalf.com> wrote: > > > > > > > > BBR 1.0 spec says that _STA is required for each device in DSDT or SSDT. > > > > Fix that for all platforms with the Marvell SoC's. > > > > > > > > > > Can we fix the BBR instead? If ACPI itself does not require _STA, BBR > > > should not require it either. > > > > > > > > > > I consulted with ARM on the matter. SBBR has requirements of things > > that are otherwise optional in UEFI/ACPI/SMBIOS. Also some OS's may > > require that and I can see those methods in most of the other ACPI > > source files in the edk2-platfoms tree. I think the BBR requirements > > discussions can follow, but it would be great if this change can be > > applied, so that no to block other development. > > > > Do you have any feedback to the patchset and the _STA methods concerns? > Yes. I would like to understand why _STA methods are now mandated by BBR. > > > > > > > > > Signed-off-by: Marcin Wojtas <mw@semihalf.com> > > > > --- > > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 +++++++++++++++ > > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++++++++++++++++ > > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 72 +++++++++++++++++++ > > > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 ++++ > > > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 56 +++++++++++++++ > > > > 5 files changed, 272 insertions(+) > > > > > > > > diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > > > > index 345c1e4dd6..88e38efeeb 100644 > > > > --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > > > > +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > > > > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > { > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > Name (_UID, 0x000) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > } > > > > Device (CPU1) > > > > { > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > Name (_UID, 0x001) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > } > > > > Device (CPU2) > > > > { > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > Name (_UID, 0x100) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > } > > > > Device (CPU3) > > > > { > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > Name (_UID, 0x101) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > } > > > > > > > > Device (AHC0) > > > > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > { > > > > 0x01, > > > > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > Name (_HID, "MRVL0002") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -96,6 +120,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -123,6 +151,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -142,6 +174,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -160,6 +196,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > { > > > > Name (_HID, "MRVL0001") // _HID: Hardware ID > > > > Name (_CID, "HISI0031") // _CID: Compatible ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -186,6 +226,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > { > > > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CRS, ResourceTemplate () > > > > { > > > > Memory32Fixed (ReadWrite, > > > > @@ -208,6 +252,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CRS, ResourceTemplate () > > > > { > > > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > > > @@ -286,6 +334,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > { > > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CRS, ResourceTemplate () > > > > { > > > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > > > @@ -312,6 +364,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > Name (_SEG, 0x00) // _SEG: PCI Segment > > > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_PRT, Package () // _PRT: PCI Routing Table > > > > { > > > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > > > diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > > > > index 91401c74c8..77d3aebaf1 100644 > > > > --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > > > > +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > > > > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > { > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > Name (_UID, 0x000) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > } > > > > Device (CPU1) > > > > { > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > Name (_UID, 0x001) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > } > > > > Device (CPU2) > > > > { > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > Name (_UID, 0x100) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > } > > > > Device (CPU3) > > > > { > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > Name (_UID, 0x101) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > } > > > > > > > > Device (AHC0) > > > > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > { > > > > 0x01, > > > > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > { > > > > 0x01, > > > > @@ -92,6 +116,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > Name (_HID, "MRVL0002") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -122,6 +150,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -151,6 +183,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -170,6 +206,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > Name (_UID, 0x02) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -207,6 +251,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > { > > > > Name (_HID, "MRVL0001") // _HID: Hardware ID > > > > Name (_CID, "HISI0031") // _CID: Compatible ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -233,6 +281,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > { > > > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CRS, ResourceTemplate () > > > > { > > > > Memory32Fixed (ReadWrite, > > > > @@ -251,6 +303,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CRS, ResourceTemplate () > > > > { > > > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > > > @@ -309,6 +365,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > { > > > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CRS, ResourceTemplate () > > > > { > > > > Memory32Fixed (ReadWrite, > > > > @@ -327,6 +387,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CRS, ResourceTemplate () > > > > { > > > > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > > > > @@ -385,6 +449,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > { > > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CRS, ResourceTemplate () > > > > { > > > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > > > @@ -405,6 +473,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > { > > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CRS, ResourceTemplate () > > > > { > > > > Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) > > > > @@ -431,6 +503,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > Name (_SEG, 0x00) // _SEG: PCI Segment > > > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_PRT, Package () // _PRT: PCI Routing Table > > > > { > > > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > > > diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > > > > index d26945d933..1ecbd0309c 100644 > > > > --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > > > > +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > > > > @@ -19,21 +19,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > { > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > Name (_UID, 0x000) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > } > > > > Device (CPU1) > > > > { > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > Name (_UID, 0x001) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > } > > > > Device (CPU2) > > > > { > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > Name (_UID, 0x100) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > } > > > > Device (CPU3) > > > > { > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > Name (_UID, 0x101) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > } > > > > > > > > Device (AHC0) > > > > @@ -41,6 +57,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > { > > > > 0x01, > > > > @@ -91,6 +111,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > Name (_HID, "MRVL0002") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -122,6 +146,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -150,6 +178,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -169,6 +201,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -188,6 +224,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > Name (_UID, 0x02) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -206,6 +246,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > { > > > > Name (_HID, "MRVL0001") // _HID: Hardware ID > > > > Name (_CID, "HISI0031") // _CID: Compatible ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -232,6 +276,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > { > > > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CRS, ResourceTemplate () > > > > { > > > > Memory32Fixed (ReadWrite, > > > > @@ -249,6 +297,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > { > > > > Name (_HID, "MRVL0101") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CRS, ResourceTemplate () > > > > { > > > > Memory32Fixed (ReadWrite, > > > > @@ -283,6 +335,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CRS, ResourceTemplate () > > > > { > > > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > > > @@ -322,6 +378,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CRS, ResourceTemplate () > > > > { > > > > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > > > > @@ -400,6 +460,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > { > > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CRS, ResourceTemplate () > > > > { > > > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > > > @@ -420,6 +484,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > { > > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CRS, ResourceTemplate () > > > > { > > > > Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) > > > > @@ -446,6 +514,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > Name (_SEG, 0x00) // _SEG: PCI Segment > > > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_PRT, Package () // _PRT: PCI Routing Table > > > > { > > > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > > > diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > > > > index 8377b13763..d6619e367b 100644 > > > > --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > > > > +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > > > > @@ -20,6 +20,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > { > > > > 0x01, > > > > @@ -45,6 +49,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > Name (_UID, 0x02) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -63,6 +71,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CRS, ResourceTemplate () > > > > { > > > > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > > > > diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > > > > index d76a2a902b..536df8ab4b 100644 > > > > --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > > > > +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > > > > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > { > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > Name (_UID, 0x000) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > } > > > > Device (CPU1) > > > > { > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > Name (_UID, 0x001) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > } > > > > Device (CPU2) > > > > { > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > Name (_UID, 0x100) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > } > > > > Device (CPU3) > > > > { > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > Name (_UID, 0x101) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > } > > > > > > > > Device (AHC0) > > > > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > { > > > > 0x01, > > > > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > Name (_HID, "MRVL0003") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -98,6 +122,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -126,6 +154,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -145,6 +177,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -163,6 +199,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > { > > > > Name (_HID, "MRVL0001") // _HID: Hardware ID > > > > Name (_CID, "HISI0031") // _CID: Compatible ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > { > > > > @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > { > > > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CRS, ResourceTemplate () > > > > { > > > > Memory32Fixed (ReadWrite, > > > > @@ -211,6 +255,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CRS, ResourceTemplate () > > > > { > > > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > > > @@ -289,6 +337,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > { > > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_CRS, ResourceTemplate () > > > > { > > > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > > > @@ -315,6 +367,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > Name (_SEG, 0x00) // _SEG: PCI Segment > > > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > + Method (_STA) // _STA: Device status > > > > + { > > > > + Return (0xF) > > > > + } > > > > Name (_PRT, Package () // _PRT: PCI Routing Table > > > > { > > > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > > > -- > > > > 2.29.0 > > > > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables 2021-07-29 9:57 ` Ard Biesheuvel @ 2021-07-30 9:57 ` Marcin Wojtas 2021-08-01 16:58 ` Ard Biesheuvel 2021-08-10 14:36 ` Samer El-Haj-Mahmoud 0 siblings, 2 replies; 19+ messages in thread From: Marcin Wojtas @ 2021-07-30 9:57 UTC (permalink / raw) To: Ard Biesheuvel Cc: Samer El-Haj-Mahmoud, edk2-devel-groups-io, Leif Lindholm, Ard Biesheuvel, Grzegorz Jaszczyk, Grzegorz Bernacki, upstream, Jon Nettleton Hi Ard, czw., 29 lip 2021 o 11:58 Ard Biesheuvel <ardb@kernel.org> napisał(a): > > On Thu, 29 Jul 2021 at 11:46, Marcin Wojtas <mw@semihalf.com> wrote: > > > > Hi Ard, > > > > pon., 19 lip 2021 o 17:06 Marcin Wojtas <mw@semihalf.com> napisał(a): > > > > > > Hi Ard, > > > > > > pon., 19 lip 2021 o 11:54 Ard Biesheuvel <ardb@kernel.org> napisał(a): > > > > > > > > On Mon, 19 Jul 2021 at 11:31, Marcin Wojtas <mw@semihalf.com> wrote: > > > > > > > > > > BBR 1.0 spec says that _STA is required for each device in DSDT or SSDT. > > > > > Fix that for all platforms with the Marvell SoC's. > > > > > > > > > > > > > Can we fix the BBR instead? If ACPI itself does not require _STA, BBR > > > > should not require it either. > > > > > > > > > > > > > > I consulted with ARM on the matter. SBBR has requirements of things > > > that are otherwise optional in UEFI/ACPI/SMBIOS. Also some OS's may > > > require that and I can see those methods in most of the other ACPI > > > source files in the edk2-platfoms tree. I think the BBR requirements > > > discussions can follow, but it would be great if this change can be > > > applied, so that no to block other development. > > > > > > > Do you have any feedback to the patchset and the _STA methods concerns? > > > > Yes. I would like to understand why _STA methods are now mandated by BBR. > Understood. Providing an answer may not be immediate and may possibly require further discussion on the SystemArchAC level. How about we withdraw this single patch for now and process the remaining ones? We would come back to the _STA subject, as soon as there's more information available. Best regards, Marcin > > > > > > > > > > > > > Signed-off-by: Marcin Wojtas <mw@semihalf.com> > > > > > --- > > > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 +++++++++++++++ > > > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++++++++++++++++ > > > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 72 +++++++++++++++++++ > > > > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 ++++ > > > > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 56 +++++++++++++++ > > > > > 5 files changed, 272 insertions(+) > > > > > > > > > > diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > > > > > index 345c1e4dd6..88e38efeeb 100644 > > > > > --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > > > > > +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > > > > > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > { > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > Name (_UID, 0x000) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > } > > > > > Device (CPU1) > > > > > { > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > Name (_UID, 0x001) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > } > > > > > Device (CPU2) > > > > > { > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > Name (_UID, 0x100) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > } > > > > > Device (CPU3) > > > > > { > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > Name (_UID, 0x101) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > } > > > > > > > > > > Device (AHC0) > > > > > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > > { > > > > > 0x01, > > > > > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > Name (_HID, "MRVL0002") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -96,6 +120,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -123,6 +151,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -142,6 +174,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -160,6 +196,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > { > > > > > Name (_HID, "MRVL0001") // _HID: Hardware ID > > > > > Name (_CID, "HISI0031") // _CID: Compatible ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -186,6 +226,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > { > > > > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CRS, ResourceTemplate () > > > > > { > > > > > Memory32Fixed (ReadWrite, > > > > > @@ -208,6 +252,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CRS, ResourceTemplate () > > > > > { > > > > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > > > > @@ -286,6 +334,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > { > > > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CRS, ResourceTemplate () > > > > > { > > > > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > > > > @@ -312,6 +364,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > Name (_SEG, 0x00) // _SEG: PCI Segment > > > > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_PRT, Package () // _PRT: PCI Routing Table > > > > > { > > > > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > > > > diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > > > > > index 91401c74c8..77d3aebaf1 100644 > > > > > --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > > > > > +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > > > > > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > { > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > Name (_UID, 0x000) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > } > > > > > Device (CPU1) > > > > > { > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > Name (_UID, 0x001) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > } > > > > > Device (CPU2) > > > > > { > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > Name (_UID, 0x100) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > } > > > > > Device (CPU3) > > > > > { > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > Name (_UID, 0x101) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > } > > > > > > > > > > Device (AHC0) > > > > > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > > { > > > > > 0x01, > > > > > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > > { > > > > > 0x01, > > > > > @@ -92,6 +116,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > Name (_HID, "MRVL0002") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -122,6 +150,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -151,6 +183,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -170,6 +206,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > Name (_UID, 0x02) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -207,6 +251,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > { > > > > > Name (_HID, "MRVL0001") // _HID: Hardware ID > > > > > Name (_CID, "HISI0031") // _CID: Compatible ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -233,6 +281,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > { > > > > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CRS, ResourceTemplate () > > > > > { > > > > > Memory32Fixed (ReadWrite, > > > > > @@ -251,6 +303,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CRS, ResourceTemplate () > > > > > { > > > > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > > > > @@ -309,6 +365,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > { > > > > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CRS, ResourceTemplate () > > > > > { > > > > > Memory32Fixed (ReadWrite, > > > > > @@ -327,6 +387,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CRS, ResourceTemplate () > > > > > { > > > > > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > > > > > @@ -385,6 +449,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > { > > > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CRS, ResourceTemplate () > > > > > { > > > > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > > > > @@ -405,6 +473,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > { > > > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CRS, ResourceTemplate () > > > > > { > > > > > Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) > > > > > @@ -431,6 +503,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > Name (_SEG, 0x00) // _SEG: PCI Segment > > > > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_PRT, Package () // _PRT: PCI Routing Table > > > > > { > > > > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > > > > diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > > > > > index d26945d933..1ecbd0309c 100644 > > > > > --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > > > > > +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > > > > > @@ -19,21 +19,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > { > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > Name (_UID, 0x000) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > } > > > > > Device (CPU1) > > > > > { > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > Name (_UID, 0x001) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > } > > > > > Device (CPU2) > > > > > { > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > Name (_UID, 0x100) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > } > > > > > Device (CPU3) > > > > > { > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > Name (_UID, 0x101) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > } > > > > > > > > > > Device (AHC0) > > > > > @@ -41,6 +57,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > > { > > > > > 0x01, > > > > > @@ -91,6 +111,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > Name (_HID, "MRVL0002") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -122,6 +146,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -150,6 +178,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -169,6 +201,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -188,6 +224,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > Name (_UID, 0x02) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -206,6 +246,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > { > > > > > Name (_HID, "MRVL0001") // _HID: Hardware ID > > > > > Name (_CID, "HISI0031") // _CID: Compatible ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -232,6 +276,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > { > > > > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CRS, ResourceTemplate () > > > > > { > > > > > Memory32Fixed (ReadWrite, > > > > > @@ -249,6 +297,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > { > > > > > Name (_HID, "MRVL0101") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CRS, ResourceTemplate () > > > > > { > > > > > Memory32Fixed (ReadWrite, > > > > > @@ -283,6 +335,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CRS, ResourceTemplate () > > > > > { > > > > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > > > > @@ -322,6 +378,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CRS, ResourceTemplate () > > > > > { > > > > > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > > > > > @@ -400,6 +460,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > { > > > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CRS, ResourceTemplate () > > > > > { > > > > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > > > > @@ -420,6 +484,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > { > > > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CRS, ResourceTemplate () > > > > > { > > > > > Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) > > > > > @@ -446,6 +514,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > Name (_SEG, 0x00) // _SEG: PCI Segment > > > > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_PRT, Package () // _PRT: PCI Routing Table > > > > > { > > > > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > > > > diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > > > > > index 8377b13763..d6619e367b 100644 > > > > > --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > > > > > +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > > > > > @@ -20,6 +20,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) > > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > > { > > > > > 0x01, > > > > > @@ -45,6 +49,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > Name (_UID, 0x02) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -63,6 +71,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) > > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CRS, ResourceTemplate () > > > > > { > > > > > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > > > > > diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > > > > > index d76a2a902b..536df8ab4b 100644 > > > > > --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > > > > > +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > > > > > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > { > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > Name (_UID, 0x000) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > } > > > > > Device (CPU1) > > > > > { > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > Name (_UID, 0x001) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > } > > > > > Device (CPU2) > > > > > { > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > Name (_UID, 0x100) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > } > > > > > Device (CPU3) > > > > > { > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > Name (_UID, 0x101) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > } > > > > > > > > > > Device (AHC0) > > > > > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > > { > > > > > 0x01, > > > > > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > Name (_HID, "MRVL0003") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -98,6 +122,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -126,6 +154,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -145,6 +177,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -163,6 +199,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > { > > > > > Name (_HID, "MRVL0001") // _HID: Hardware ID > > > > > Name (_CID, "HISI0031") // _CID: Compatible ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > { > > > > > @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > { > > > > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CRS, ResourceTemplate () > > > > > { > > > > > Memory32Fixed (ReadWrite, > > > > > @@ -211,6 +255,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CRS, ResourceTemplate () > > > > > { > > > > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > > > > @@ -289,6 +337,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > { > > > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_CRS, ResourceTemplate () > > > > > { > > > > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > > > > @@ -315,6 +367,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > Name (_SEG, 0x00) // _SEG: PCI Segment > > > > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > + Method (_STA) // _STA: Device status > > > > > + { > > > > > + Return (0xF) > > > > > + } > > > > > Name (_PRT, Package () // _PRT: PCI Routing Table > > > > > { > > > > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > > > > -- > > > > > 2.29.0 > > > > > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables 2021-07-30 9:57 ` Marcin Wojtas @ 2021-08-01 16:58 ` Ard Biesheuvel 2021-08-10 14:36 ` Samer El-Haj-Mahmoud 1 sibling, 0 replies; 19+ messages in thread From: Ard Biesheuvel @ 2021-08-01 16:58 UTC (permalink / raw) To: Marcin Wojtas Cc: Samer El-Haj-Mahmoud, edk2-devel-groups-io, Leif Lindholm, Ard Biesheuvel, Grzegorz Jaszczyk, Grzegorz Bernacki, upstream, Jon Nettleton On Fri, 30 Jul 2021 at 11:57, Marcin Wojtas <mw@semihalf.com> wrote: > > Hi Ard, > > czw., 29 lip 2021 o 11:58 Ard Biesheuvel <ardb@kernel.org> napisał(a): > > > > On Thu, 29 Jul 2021 at 11:46, Marcin Wojtas <mw@semihalf.com> wrote: > > > > > > Hi Ard, > > > > > > pon., 19 lip 2021 o 17:06 Marcin Wojtas <mw@semihalf.com> napisał(a): > > > > > > > > Hi Ard, > > > > > > > > pon., 19 lip 2021 o 11:54 Ard Biesheuvel <ardb@kernel.org> napisał(a): > > > > > > > > > > On Mon, 19 Jul 2021 at 11:31, Marcin Wojtas <mw@semihalf.com> wrote: > > > > > > > > > > > > BBR 1.0 spec says that _STA is required for each device in DSDT or SSDT. > > > > > > Fix that for all platforms with the Marvell SoC's. > > > > > > > > > > > > > > > > Can we fix the BBR instead? If ACPI itself does not require _STA, BBR > > > > > should not require it either. > > > > > > > > > > > > > > > > > > I consulted with ARM on the matter. SBBR has requirements of things > > > > that are otherwise optional in UEFI/ACPI/SMBIOS. Also some OS's may > > > > require that and I can see those methods in most of the other ACPI > > > > source files in the edk2-platfoms tree. I think the BBR requirements > > > > discussions can follow, but it would be great if this change can be > > > > applied, so that no to block other development. > > > > > > > > > > Do you have any feedback to the patchset and the _STA methods concerns? > > > > > > > Yes. I would like to understand why _STA methods are now mandated by BBR. > > > > Understood. Providing an answer may not be immediate and may possibly > require further discussion on the SystemArchAC level. > How about we withdraw this single patch for now and process the > remaining ones? Fair enough. > We would come back to the _STA subject, as soon as > there's more information available. > Thanks. > > > > > > > > > > > > > > > > > > Signed-off-by: Marcin Wojtas <mw@semihalf.com> > > > > > > --- > > > > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 +++++++++++++++ > > > > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++++++++++++++++ > > > > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 72 +++++++++++++++++++ > > > > > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 ++++ > > > > > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 56 +++++++++++++++ > > > > > > 5 files changed, 272 insertions(+) > > > > > > > > > > > > diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > > > > > > index 345c1e4dd6..88e38efeeb 100644 > > > > > > --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > > > > > > +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > > > > > > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > > Name (_UID, 0x000) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU1) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > > Name (_UID, 0x001) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU2) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > > Name (_UID, 0x100) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU3) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > > Name (_UID, 0x101) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > > > > > > > Device (AHC0) > > > > > > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > > > { > > > > > > 0x01, > > > > > > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > > Name (_HID, "MRVL0002") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -96,6 +120,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -123,6 +151,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -142,6 +174,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -160,6 +196,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > > { > > > > > > Name (_HID, "MRVL0001") // _HID: Hardware ID > > > > > > Name (_CID, "HISI0031") // _CID: Compatible ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -186,6 +226,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > > { > > > > > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, > > > > > > @@ -208,6 +252,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > > > > > @@ -286,6 +334,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > > { > > > > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > > > > > @@ -312,6 +364,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3) > > > > > > Name (_SEG, 0x00) // _SEG: PCI Segment > > > > > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_PRT, Package () // _PRT: PCI Routing Table > > > > > > { > > > > > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > > > > > diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > > > > > > index 91401c74c8..77d3aebaf1 100644 > > > > > > --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > > > > > > +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > > > > > > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > > Name (_UID, 0x000) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU1) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > > Name (_UID, 0x001) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU2) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > > Name (_UID, 0x100) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU3) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > > Name (_UID, 0x101) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > > > > > > > Device (AHC0) > > > > > > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > > > { > > > > > > 0x01, > > > > > > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > > > { > > > > > > 0x01, > > > > > > @@ -92,6 +116,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "MRVL0002") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -122,6 +150,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -151,6 +183,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -170,6 +206,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x02) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -207,6 +251,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "MRVL0001") // _HID: Hardware ID > > > > > > Name (_CID, "HISI0031") // _CID: Compatible ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -233,6 +281,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, > > > > > > @@ -251,6 +303,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > > > > > @@ -309,6 +365,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, > > > > > > @@ -327,6 +387,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > > > > > > @@ -385,6 +449,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > > > > > @@ -405,6 +473,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) > > > > > > @@ -431,6 +503,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_SEG, 0x00) // _SEG: PCI Segment > > > > > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_PRT, Package () // _PRT: PCI Routing Table > > > > > > { > > > > > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > > > > > diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > > > > > > index d26945d933..1ecbd0309c 100644 > > > > > > --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > > > > > > +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > > > > > > @@ -19,21 +19,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > > Name (_UID, 0x000) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU1) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > > Name (_UID, 0x001) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU2) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > > Name (_UID, 0x100) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU3) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > > Name (_UID, 0x101) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > > > > > > > Device (AHC0) > > > > > > @@ -41,6 +57,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > > > { > > > > > > 0x01, > > > > > > @@ -91,6 +111,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "MRVL0002") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -122,6 +146,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -150,6 +178,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -169,6 +201,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -188,6 +224,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x02) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -206,6 +246,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "MRVL0001") // _HID: Hardware ID > > > > > > Name (_CID, "HISI0031") // _CID: Compatible ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -232,6 +276,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, > > > > > > @@ -249,6 +297,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "MRVL0101") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, > > > > > > @@ -283,6 +335,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > > > > > @@ -322,6 +378,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > > > > > > @@ -400,6 +460,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > > > > > @@ -420,6 +484,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) > > > > > > @@ -446,6 +514,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_SEG, 0x00) // _SEG: PCI Segment > > > > > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_PRT, Package () // _PRT: PCI Routing Table > > > > > > { > > > > > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > > > > > diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > > > > > > index 8377b13763..d6619e367b 100644 > > > > > > --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > > > > > > +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > > > > > > @@ -20,6 +20,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) > > > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > > > { > > > > > > 0x01, > > > > > > @@ -45,6 +49,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x02) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -63,6 +71,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3) > > > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > > > > > > diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > > > > > > index d76a2a902b..536df8ab4b 100644 > > > > > > --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > > > > > > +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > > > > > > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > > Name (_UID, 0x000) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU1) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > > Name (_UID, 0x001) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU2) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > > Name (_UID, 0x100) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU3) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID > > > > > > Name (_UID, 0x101) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > > > > > > > Device (AHC0) > > > > > > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > > > { > > > > > > 0x01, > > > > > > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > > Name (_HID, "MRVL0003") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -98,6 +122,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -126,6 +154,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -145,6 +177,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -163,6 +199,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > > { > > > > > > Name (_HID, "MRVL0001") // _HID: Hardware ID > > > > > > Name (_CID, "HISI0031") // _CID: Compatible ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > > > > > > { > > > > > > @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > > { > > > > > > Name (_HID, "MRVL0100") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, > > > > > > @@ -211,6 +255,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > > Name (_HID, "MRVL0110") // _HID: Hardware ID > > > > > > Name (_CCA, 0x01) // Cache-coherent controller > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > > > > > @@ -289,6 +337,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > > { > > > > > > Name (_HID, "PRP0001") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > > > > > @@ -315,6 +367,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) > > > > > > Name (_SEG, 0x00) // _SEG: PCI Segment > > > > > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_PRT, Package () // _PRT: PCI Routing Table > > > > > > { > > > > > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > > > > > -- > > > > > > 2.29.0 > > > > > > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables 2021-07-30 9:57 ` Marcin Wojtas 2021-08-01 16:58 ` Ard Biesheuvel @ 2021-08-10 14:36 ` Samer El-Haj-Mahmoud 2021-08-10 14:41 ` [edk2-devel] " Ard Biesheuvel 1 sibling, 1 reply; 19+ messages in thread From: Samer El-Haj-Mahmoud @ 2021-08-10 14:36 UTC (permalink / raw) To: Marcin Wojtas, Ard Biesheuvel Cc: edk2-devel-groups-io, Leif Lindholm, Ard Biesheuvel, Grzegorz Jaszczyk, Grzegorz Bernacki, upstream@semihalf.com, Jon (jon@solid-run.com), Samer El-Haj-Mahmoud Apologies for the tardiness in replying to this. Please see my comments below. > -----Original Message----- > From: Marcin Wojtas <mw@semihalf.com> > Sent: Friday, July 30, 2021 5:57 AM > To: Ard Biesheuvel <ardb@kernel.org> > Cc: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>; edk2- > devel-groups-io <devel@edk2.groups.io>; Leif Lindholm > <leif@nuviainc.com>; Ard Biesheuvel <ardb+tianocore@kernel.org>; > Grzegorz Jaszczyk <jaz@semihalf.com>; Grzegorz Bernacki > <gjb@semihalf.com>; upstream@semihalf.com; Jon (jon@solid-run.com) > <jon@solid-run.com> > Subject: Re: [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: > Add missing _STA methods in ACPI tables > > Hi Ard, > > czw., 29 lip 2021 o 11:58 Ard Biesheuvel <ardb@kernel.org> napisał(a): > > > > On Thu, 29 Jul 2021 at 11:46, Marcin Wojtas <mw@semihalf.com> wrote: > > > > > > Hi Ard, > > > > > > pon., 19 lip 2021 o 17:06 Marcin Wojtas <mw@semihalf.com> napisał(a): > > > > > > > > Hi Ard, > > > > > > > > pon., 19 lip 2021 o 11:54 Ard Biesheuvel <ardb@kernel.org> napisał(a): > > > > > > > > > > On Mon, 19 Jul 2021 at 11:31, Marcin Wojtas <mw@semihalf.com> > wrote: > > > > > > > > > > > > BBR 1.0 spec says that _STA is required for each device in DSDT or > SSDT. > > > > > > Fix that for all platforms with the Marvell SoC's. > > > > > > > > > > > > > > > > Can we fix the BBR instead? If ACPI itself does not require _STA, BBR > > > > > should not require it either. > > > > > > > > > > > > > > > > > > I consulted with ARM on the matter. SBBR has requirements of things > > > > that are otherwise optional in UEFI/ACPI/SMBIOS. Also some OS's may > > > > require that and I can see those methods in most of the other ACPI > > > > source files in the edk2-platfoms tree. I think the BBR requirements > > > > discussions can follow, but it would be great if this change can be > > > > applied, so that no to block other development. > > > > > > > > > > Do you have any feedback to the patchset and the _STA methods > concerns? > > > > > > > Yes. I would like to understand why _STA methods are now mandated by > BBR. > > > > Understood. Providing an answer may not be immediate and may possibly > require further discussion on the SystemArchAC level. > How about we withdraw this single patch for now and process the > remaining ones? We would come back to the _STA subject, as soon as > there's more information available. > > Best regards, > Marcin > _STA has been required in SBBR since ver 1.0 (published 2016, with the 0.9 draft since 2014) https://developer.arm.com/documentation/den0044/b/?lang=en I do not have the history on why SBBR 1.0+ requires _STA, but it most likely has to do wit the Windows strong use case for it: https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/device-management-namespace-objects#device-status-changes . Windows is a key OS targeted by SBBR. > > > > > > > > > > > > > > > > > > Signed-off-by: Marcin Wojtas <mw@semihalf.com> > > > > > > --- > > > > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > | 56 +++++++++++++++ > > > > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > | 76 ++++++++++++++++++++ > > > > > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 72 > +++++++++++++++++++ > > > > > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | > 12 ++++ > > > > > > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | > 56 +++++++++++++++ > > > > > > 5 files changed, 272 insertions(+) > > > > > > > > > > > > diff --git > a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > > > > > > index 345c1e4dd6..88e38efeeb 100644 > > > > > > --- > a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > > > > > > +++ > b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl > > > > > > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA7K", 3) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: > Hardware ID > > > > > > Name (_UID, 0x000) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU1) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: > Hardware ID > > > > > > Name (_UID, 0x001) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU2) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: > Hardware ID > > > > > > Name (_UID, 0x100) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU3) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: > Hardware ID > > > > > > Name (_UID, 0x101) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > > > > > > > Device (AHC0) > > > > > > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA7K", 3) > > > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > > > { > > > > > > 0x01, > > > > > > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA7K", 3) > > > > > > Name (_HID, "MRVL0002") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -96,6 +120,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA7K", 3) > > > > > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -123,6 +151,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA7K", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -142,6 +174,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA7K", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -160,6 +196,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA7K", 3) > > > > > > { > > > > > > Name (_HID, "MRVL0001") // _HID: Hardware > ID > > > > > > Name (_CID, "HISI0031") // _CID: Compatible ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // > _ADR: Address > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -186,6 +226,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA7K", 3) > > > > > > { > > > > > > Name (_HID, "MRVL0100") // _HID: Hardware > ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, > > > > > > @@ -208,6 +252,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA7K", 3) > > > > > > Name (_HID, "MRVL0110") // _HID: Hardware > ID > > > > > > Name (_CCA, 0x01) // Cache-coherent > controller > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > > > > > @@ -286,6 +334,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA7K", 3) > > > > > > { > > > > > > Name (_HID, "PRP0001") // _HID: Hardware > ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > > > > > @@ -312,6 +364,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA7K", 3) > > > > > > Name (_SEG, 0x00) // _SEG: PCI Segment > > > > > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_PRT, Package () // _PRT: PCI Routing Table > > > > > > { > > > > > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > > > > > diff --git > a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > > > > > > index 91401c74c8..77d3aebaf1 100644 > > > > > > --- > a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > > > > > > +++ > b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl > > > > > > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: > Hardware ID > > > > > > Name (_UID, 0x000) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU1) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: > Hardware ID > > > > > > Name (_UID, 0x001) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU2) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: > Hardware ID > > > > > > Name (_UID, 0x100) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU3) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: > Hardware ID > > > > > > Name (_UID, 0x101) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > > > > > > > Device (AHC0) > > > > > > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > > > { > > > > > > 0x01, > > > > > > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > > > { > > > > > > 0x01, > > > > > > @@ -92,6 +116,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "MRVL0002") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -122,6 +150,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -151,6 +183,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -170,6 +206,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x02) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -207,6 +251,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "MRVL0001") // _HID: Hardware > ID > > > > > > Name (_CID, "HISI0031") // _CID: Compatible ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // > _ADR: Address > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -233,6 +281,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "MRVL0100") // _HID: Hardware > ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, > > > > > > @@ -251,6 +303,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "MRVL0110") // _HID: Hardware > ID > > > > > > Name (_CCA, 0x01) // Cache-coherent > controller > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > > > > > @@ -309,6 +365,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "MRVL0100") // _HID: Hardware > ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, > > > > > > @@ -327,6 +387,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "MRVL0110") // _HID: Hardware > ID > > > > > > Name (_CCA, 0x01) // Cache-coherent > controller > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > > > > > > @@ -385,6 +449,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "PRP0001") // _HID: Hardware > ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > > > > > @@ -405,6 +473,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "PRP0001") // _HID: Hardware > ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) > > > > > > @@ -431,6 +503,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_SEG, 0x00) // _SEG: PCI Segment > > > > > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_PRT, Package () // _PRT: PCI Routing Table > > > > > > { > > > > > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > > > > > diff --git > a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > > > > > > index d26945d933..1ecbd0309c 100644 > > > > > > --- > a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > > > > > > +++ > b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl > > > > > > @@ -19,21 +19,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: > Hardware ID > > > > > > Name (_UID, 0x000) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU1) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: > Hardware ID > > > > > > Name (_UID, 0x001) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU2) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: > Hardware ID > > > > > > Name (_UID, 0x100) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU3) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: > Hardware ID > > > > > > Name (_UID, 0x101) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > > > > > > > Device (AHC0) > > > > > > @@ -41,6 +57,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > > > { > > > > > > 0x01, > > > > > > @@ -91,6 +111,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "MRVL0002") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -122,6 +146,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -150,6 +178,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -169,6 +201,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -188,6 +224,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x02) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -206,6 +246,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "MRVL0001") // _HID: Hardware > ID > > > > > > Name (_CID, "HISI0031") // _CID: Compatible ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // > _ADR: Address > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -232,6 +276,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "MRVL0100") // _HID: Hardware > ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, > > > > > > @@ -249,6 +297,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "MRVL0101") // _HID: Hardware > ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, > > > > > > @@ -283,6 +335,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "MRVL0110") // _HID: Hardware > ID > > > > > > Name (_CCA, 0x01) // Cache-coherent > controller > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > > > > > @@ -322,6 +378,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_HID, "MRVL0110") // _HID: Hardware > ID > > > > > > Name (_CCA, 0x01) // Cache-coherent > controller > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > > > > > > @@ -400,6 +460,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "PRP0001") // _HID: Hardware > ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > > > > > @@ -420,6 +484,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > { > > > > > > Name (_HID, "PRP0001") // _HID: Hardware > ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) > > > > > > @@ -446,6 +514,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "ARMADA8K", 3) > > > > > > Name (_SEG, 0x00) // _SEG: PCI Segment > > > > > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_PRT, Package () // _PRT: PCI Routing Table > > > > > > { > > > > > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > > > > > diff --git > a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > > > > > > index 8377b13763..d6619e367b 100644 > > > > > > --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > > > > > > +++ > b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > > > > > > @@ -20,6 +20,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", > "SSDT", 2, "MVEBU ", "CN9131", 3) > > > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > > > { > > > > > > 0x01, > > > > > > @@ -45,6 +49,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", > "SSDT", 2, "MVEBU ", "CN9131", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x02) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -63,6 +71,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", > "SSDT", 2, "MVEBU ", "CN9131", 3) > > > > > > Name (_HID, "MRVL0110") // _HID: Hardware > ID > > > > > > Name (_CCA, 0x01) // Cache-coherent > controller > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) > > > > > > diff --git > a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > > > > > > index d76a2a902b..536df8ab4b 100644 > > > > > > --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > > > > > > +++ > b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > > > > > > @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "CN9130", 3) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: > Hardware ID > > > > > > Name (_UID, 0x000) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU1) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: > Hardware ID > > > > > > Name (_UID, 0x001) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU2) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: > Hardware ID > > > > > > Name (_UID, 0x100) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > Device (CPU3) > > > > > > { > > > > > > Name (_HID, "ACPI0007" /* Processor Device */) // _HID: > Hardware ID > > > > > > Name (_UID, 0x101) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > } > > > > > > > > > > > > Device (AHC0) > > > > > > @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "CN9130", 3) > > > > > > Name (_HID, "LNRO001E") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CLS, Package (0x03) // _CLS: Class Code > > > > > > { > > > > > > 0x01, > > > > > > @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "CN9130", 3) > > > > > > Name (_HID, "MRVL0003") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -98,6 +122,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "CN9130", 3) > > > > > > Name (_HID, "MRVL0004") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -126,6 +154,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "CN9130", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -145,6 +177,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "CN9130", 3) > > > > > > Name (_HID, "PNP0D10") // _HID: Hardware ID > > > > > > Name (_UID, 0x01) // _UID: Unique ID > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -163,6 +199,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "CN9130", 3) > > > > > > { > > > > > > Name (_HID, "MRVL0001") // _HID: Hardware > ID > > > > > > Name (_CID, "HISI0031") // _CID: Compatible ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // > _ADR: Address > > > > > > Name (_CRS, ResourceTemplate () // _CRS: Current > Resource Settings > > > > > > { > > > > > > @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "CN9130", 3) > > > > > > { > > > > > > Name (_HID, "MRVL0100") // _HID: Hardware > ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, > > > > > > @@ -211,6 +255,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "CN9130", 3) > > > > > > Name (_HID, "MRVL0110") // _HID: Hardware > ID > > > > > > Name (_CCA, 0x01) // Cache-coherent > controller > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) > > > > > > @@ -289,6 +337,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "CN9130", 3) > > > > > > { > > > > > > Name (_HID, "PRP0001") // _HID: Hardware > ID > > > > > > Name (_UID, 0x00) // _UID: Unique ID > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_CRS, ResourceTemplate () > > > > > > { > > > > > > Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) > > > > > > @@ -315,6 +367,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, > "MVEBU ", "CN9130", 3) > > > > > > Name (_SEG, 0x00) // _SEG: PCI Segment > > > > > > Name (_BBN, 0x00) // _BBN: BIOS Bus Number > > > > > > Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute > > > > > > + Method (_STA) // _STA: Device status > > > > > > + { > > > > > > + Return (0xF) > > > > > > + } > > > > > > Name (_PRT, Package () // _PRT: PCI Routing Table > > > > > > { > > > > > > Package () { 0xFFFF, 0x0, 0x0, 0x40 }, > > > > > > -- > > > > > > 2.29.0 > > > > > > IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [edk2-devel] [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables 2021-08-10 14:36 ` Samer El-Haj-Mahmoud @ 2021-08-10 14:41 ` Ard Biesheuvel 2021-08-10 15:01 ` Samer El-Haj-Mahmoud 2021-08-10 22:12 ` Marcin Wojtas 0 siblings, 2 replies; 19+ messages in thread From: Ard Biesheuvel @ 2021-08-10 14:41 UTC (permalink / raw) To: edk2-devel-groups-io, Samer El-Haj-Mahmoud Cc: Marcin Wojtas, Leif Lindholm, Ard Biesheuvel, Grzegorz Jaszczyk, Grzegorz Bernacki, upstream@semihalf.com, Jon (jon@solid-run.com) On Tue, 10 Aug 2021 at 16:36, Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com> wrote: > > Apologies for the tardiness in replying to this. Please see my comments below. > > > -----Original Message----- > > From: Marcin Wojtas <mw@semihalf.com> > > Sent: Friday, July 30, 2021 5:57 AM > > To: Ard Biesheuvel <ardb@kernel.org> > > Cc: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>; edk2- > > devel-groups-io <devel@edk2.groups.io>; Leif Lindholm > > <leif@nuviainc.com>; Ard Biesheuvel <ardb+tianocore@kernel.org>; > > Grzegorz Jaszczyk <jaz@semihalf.com>; Grzegorz Bernacki > > <gjb@semihalf.com>; upstream@semihalf.com; Jon (jon@solid-run.com) > > <jon@solid-run.com> > > Subject: Re: [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: > > Add missing _STA methods in ACPI tables > > > > Hi Ard, > > > > czw., 29 lip 2021 o 11:58 Ard Biesheuvel <ardb@kernel.org> napisał(a): > > > > > > On Thu, 29 Jul 2021 at 11:46, Marcin Wojtas <mw@semihalf.com> wrote: > > > > > > > > Hi Ard, > > > > > > > > pon., 19 lip 2021 o 17:06 Marcin Wojtas <mw@semihalf.com> napisał(a): > > > > > > > > > > Hi Ard, > > > > > > > > > > pon., 19 lip 2021 o 11:54 Ard Biesheuvel <ardb@kernel.org> napisał(a): > > > > > > > > > > > > On Mon, 19 Jul 2021 at 11:31, Marcin Wojtas <mw@semihalf.com> > > wrote: > > > > > > > > > > > > > > BBR 1.0 spec says that _STA is required for each device in DSDT or > > SSDT. > > > > > > > Fix that for all platforms with the Marvell SoC's. > > > > > > > > > > > > > > > > > > > Can we fix the BBR instead? If ACPI itself does not require _STA, BBR > > > > > > should not require it either. > > > > > > > > > > > > > > > > > > > > > > I consulted with ARM on the matter. SBBR has requirements of things > > > > > that are otherwise optional in UEFI/ACPI/SMBIOS. Also some OS's may > > > > > require that and I can see those methods in most of the other ACPI > > > > > source files in the edk2-platfoms tree. I think the BBR requirements > > > > > discussions can follow, but it would be great if this change can be > > > > > applied, so that no to block other development. > > > > > > > > > > > > > Do you have any feedback to the patchset and the _STA methods > > concerns? > > > > > > > > > > Yes. I would like to understand why _STA methods are now mandated by > > BBR. > > > > > > > Understood. Providing an answer may not be immediate and may possibly > > require further discussion on the SystemArchAC level. > > How about we withdraw this single patch for now and process the > > remaining ones? We would come back to the _STA subject, as soon as > > there's more information available. > > > > Best regards, > > Marcin > > > > _STA has been required in SBBR since ver 1.0 (published 2016, with the 0.9 draft since 2014) > https://developer.arm.com/documentation/den0044/b/?lang=en > > I do not have the history on why SBBR 1.0+ requires _STA, but it most likely has to do wit the Windows strong use case for it: https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/device-management-namespace-objects#device-status-changes . Windows is a key OS targeted by SBBR. > OK, I stand corrected again :-) Marcin, I won't object further to these additions -please respin the patch on top of current edk2-platform and I will apply it right away. ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [edk2-devel] [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables 2021-08-10 14:41 ` [edk2-devel] " Ard Biesheuvel @ 2021-08-10 15:01 ` Samer El-Haj-Mahmoud 2021-08-10 22:12 ` Marcin Wojtas 1 sibling, 0 replies; 19+ messages in thread From: Samer El-Haj-Mahmoud @ 2021-08-10 15:01 UTC (permalink / raw) To: devel@edk2.groups.io, ardb@kernel.org Cc: Marcin Wojtas, Leif Lindholm, Ard Biesheuvel, Grzegorz Jaszczyk, Grzegorz Bernacki, upstream@semihalf.com, Jon (jon@solid-run.com), Samer El-Haj-Mahmoud > -----Original Message----- > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Ard > Biesheuvel via groups.io > Sent: Tuesday, August 10, 2021 10:41 AM > To: edk2-devel-groups-io <devel@edk2.groups.io>; Samer El-Haj-Mahmoud > <Samer.El-Haj-Mahmoud@arm.com> > Cc: Marcin Wojtas <mw@semihalf.com>; Leif Lindholm <leif@nuviainc.com>; > Ard Biesheuvel <ardb+tianocore@kernel.org>; Grzegorz Jaszczyk > <jaz@semihalf.com>; Grzegorz Bernacki <gjb@semihalf.com>; > upstream@semihalf.com; Jon (jon@solid-run.com) <jon@solid-run.com> > Subject: Re: [edk2-devel] [edk2-platforms PATCH 2/7] Marvell: > Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables > > On Tue, 10 Aug 2021 at 16:36, Samer El-Haj-Mahmoud > <samer.el-haj-mahmoud@arm.com> wrote: > > > > Apologies for the tardiness in replying to this. Please see my comments > below. > > > > > -----Original Message----- > > > From: Marcin Wojtas <mw@semihalf.com> > > > Sent: Friday, July 30, 2021 5:57 AM > > > To: Ard Biesheuvel <ardb@kernel.org> > > > Cc: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>; edk2- > > > devel-groups-io <devel@edk2.groups.io>; Leif Lindholm > > > <leif@nuviainc.com>; Ard Biesheuvel <ardb+tianocore@kernel.org>; > > > Grzegorz Jaszczyk <jaz@semihalf.com>; Grzegorz Bernacki > > > <gjb@semihalf.com>; upstream@semihalf.com; Jon (jon@solid- > run.com) > > > <jon@solid-run.com> > > > Subject: Re: [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: > > > Add missing _STA methods in ACPI tables > > > > > > Hi Ard, > > > > > > czw., 29 lip 2021 o 11:58 Ard Biesheuvel <ardb@kernel.org> napisał(a): > > > > > > > > On Thu, 29 Jul 2021 at 11:46, Marcin Wojtas <mw@semihalf.com> > wrote: > > > > > > > > > > Hi Ard, > > > > > > > > > > pon., 19 lip 2021 o 17:06 Marcin Wojtas <mw@semihalf.com> > napisał(a): > > > > > > > > > > > > Hi Ard, > > > > > > > > > > > > pon., 19 lip 2021 o 11:54 Ard Biesheuvel <ardb@kernel.org> > napisał(a): > > > > > > > > > > > > > > On Mon, 19 Jul 2021 at 11:31, Marcin Wojtas <mw@semihalf.com> > > > wrote: > > > > > > > > > > > > > > > > BBR 1.0 spec says that _STA is required for each device in DSDT > or > > > SSDT. > > > > > > > > Fix that for all platforms with the Marvell SoC's. > > > > > > > > > > > > > > > > > > > > > > Can we fix the BBR instead? If ACPI itself does not require _STA, > BBR > > > > > > > should not require it either. > > > > > > > > > > > > > > > > > > > > > > > > > > I consulted with ARM on the matter. SBBR has requirements of > things > > > > > > that are otherwise optional in UEFI/ACPI/SMBIOS. Also some OS's > may > > > > > > require that and I can see those methods in most of the other ACPI > > > > > > source files in the edk2-platfoms tree. I think the BBR requirements > > > > > > discussions can follow, but it would be great if this change can be > > > > > > applied, so that no to block other development. > > > > > > > > > > > > > > > > Do you have any feedback to the patchset and the _STA methods > > > concerns? > > > > > > > > > > > > > Yes. I would like to understand why _STA methods are now mandated > by > > > BBR. > > > > > > > > > > Understood. Providing an answer may not be immediate and may > possibly > > > require further discussion on the SystemArchAC level. > > > How about we withdraw this single patch for now and process the > > > remaining ones? We would come back to the _STA subject, as soon as > > > there's more information available. > > > > > > Best regards, > > > Marcin > > > > > > > _STA has been required in SBBR since ver 1.0 (published 2016, with the 0.9 > draft since 2014) > > https://developer.arm.com/documentation/den0044/b/?lang=en > > > > I do not have the history on why SBBR 1.0+ requires _STA, but it most likely > has to do wit the Windows strong use case for it: > https://docs.microsoft.com/en-us/windows- > hardware/drivers/bringup/device-management-namespace- > objects#device-status-changes . Windows is a key OS targeted by SBBR. > > > > OK, I stand corrected again :-) > > Marcin, > > I won't object further to these additions -please respin the patch on > top of current edk2-platform and I will apply it right away. > Thank you Ard! :-) > > > IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [edk2-devel] [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables 2021-08-10 14:41 ` [edk2-devel] " Ard Biesheuvel 2021-08-10 15:01 ` Samer El-Haj-Mahmoud @ 2021-08-10 22:12 ` Marcin Wojtas 1 sibling, 0 replies; 19+ messages in thread From: Marcin Wojtas @ 2021-08-10 22:12 UTC (permalink / raw) To: Ard Biesheuvel Cc: edk2-devel-groups-io, Samer El-Haj-Mahmoud, Leif Lindholm, Ard Biesheuvel, Grzegorz Jaszczyk, Grzegorz Bernacki, upstream@semihalf.com, Jon (jon@solid-run.com) Hi, wt., 10 sie 2021 o 16:41 Ard Biesheuvel <ardb@kernel.org> napisał(a): > > On Tue, 10 Aug 2021 at 16:36, Samer El-Haj-Mahmoud > <samer.el-haj-mahmoud@arm.com> wrote: > > > > Apologies for the tardiness in replying to this. Please see my comments below. > > > > > -----Original Message----- > > > From: Marcin Wojtas <mw@semihalf.com> > > > Sent: Friday, July 30, 2021 5:57 AM > > > To: Ard Biesheuvel <ardb@kernel.org> > > > Cc: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>; edk2- > > > devel-groups-io <devel@edk2.groups.io>; Leif Lindholm > > > <leif@nuviainc.com>; Ard Biesheuvel <ardb+tianocore@kernel.org>; > > > Grzegorz Jaszczyk <jaz@semihalf.com>; Grzegorz Bernacki > > > <gjb@semihalf.com>; upstream@semihalf.com; Jon (jon@solid-run.com) > > > <jon@solid-run.com> > > > Subject: Re: [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: > > > Add missing _STA methods in ACPI tables > > > > > > Hi Ard, > > > > > > czw., 29 lip 2021 o 11:58 Ard Biesheuvel <ardb@kernel.org> napisał(a): > > > > > > > > On Thu, 29 Jul 2021 at 11:46, Marcin Wojtas <mw@semihalf.com> wrote: > > > > > > > > > > Hi Ard, > > > > > > > > > > pon., 19 lip 2021 o 17:06 Marcin Wojtas <mw@semihalf.com> napisał(a): > > > > > > > > > > > > Hi Ard, > > > > > > > > > > > > pon., 19 lip 2021 o 11:54 Ard Biesheuvel <ardb@kernel.org> napisał(a): > > > > > > > > > > > > > > On Mon, 19 Jul 2021 at 11:31, Marcin Wojtas <mw@semihalf.com> > > > wrote: > > > > > > > > > > > > > > > > BBR 1.0 spec says that _STA is required for each device in DSDT or > > > SSDT. > > > > > > > > Fix that for all platforms with the Marvell SoC's. > > > > > > > > > > > > > > > > > > > > > > Can we fix the BBR instead? If ACPI itself does not require _STA, BBR > > > > > > > should not require it either. > > > > > > > > > > > > > > > > > > > > > > > > > > I consulted with ARM on the matter. SBBR has requirements of things > > > > > > that are otherwise optional in UEFI/ACPI/SMBIOS. Also some OS's may > > > > > > require that and I can see those methods in most of the other ACPI > > > > > > source files in the edk2-platfoms tree. I think the BBR requirements > > > > > > discussions can follow, but it would be great if this change can be > > > > > > applied, so that no to block other development. > > > > > > > > > > > > > > > > Do you have any feedback to the patchset and the _STA methods > > > concerns? > > > > > > > > > > > > > Yes. I would like to understand why _STA methods are now mandated by > > > BBR. > > > > > > > > > > Understood. Providing an answer may not be immediate and may possibly > > > require further discussion on the SystemArchAC level. > > > How about we withdraw this single patch for now and process the > > > remaining ones? We would come back to the _STA subject, as soon as > > > there's more information available. > > > > > > Best regards, > > > Marcin > > > > > > > _STA has been required in SBBR since ver 1.0 (published 2016, with the 0.9 draft since 2014) > > https://developer.arm.com/documentation/den0044/b/?lang=en > > > > I do not have the history on why SBBR 1.0+ requires _STA, but it most likely has to do wit the Windows strong use case for it: https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/device-management-namespace-objects#device-status-changes . Windows is a key OS targeted by SBBR. > > > > OK, I stand corrected again :-) > > Marcin, > > I won't object further to these additions -please respin the patch on > top of current edk2-platform and I will apply it right away. I resubmitted: https://edk2.groups.io/g/devel/topic/edk2_platforms_patch_v2/84804301?p=,,,20,0,0,0::recentpostdate%2Fsticky,,,20,2,0,84804301 In a spare moment I'd appreciate taking a look at '[edk2-platforms PATCH v2 0/4] SolidRun CEx7 Evaluation Board support' patchset :) Thanks, Marcin ^ permalink raw reply [flat|nested] 19+ messages in thread
* [edk2-platforms PATCH 3/7] Marvell/Cn913xDbA: AcpiTables: Introduce DBG2 table 2021-07-19 9:30 [edk2-platforms PATCH 0/7] Marvell ACS improvements Marcin Wojtas 2021-07-19 9:30 ` [edk2-platforms PATCH 1/7] Marvell: Armada7k8k: Add missing VariablePolicyHelperLib resolution Marcin Wojtas 2021-07-19 9:30 ` [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables Marcin Wojtas @ 2021-07-19 9:30 ` Marcin Wojtas 2021-07-19 9:30 ` [edk2-platforms PATCH 4/7] SolidRun/Armada80x0McBin: " Marcin Wojtas ` (4 subsequent siblings) 7 siblings, 0 replies; 19+ messages in thread From: Marcin Wojtas @ 2021-07-19 9:30 UTC (permalink / raw) To: devel Cc: leif, ardb+tianocore, jaz, gjb, upstream, Samer.El-Haj-Mahmoud, jon, Marcin Wojtas The DBG2 table is mandatory as per SBBR v1.2 specification. Introduce it via CP0_UART0 interface. Note: in order to use it, DPR58 and DPR59 must be switched to positions 2-3. Signed-off-by: Marcin Wojtas <mw@semihalf.com> --- Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 4 +- Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 1 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf | 1 + Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h | 2 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h | 9 +++ Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h | 2 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc | 74 ++++++++++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 33 +++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc | 2 - 9 files changed, 124 insertions(+), 4 deletions(-) create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc index 33fb7ccc08..756d875f6c 100644 --- a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc +++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc @@ -32,8 +32,8 @@ gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 } gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 0x3, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x3, 0x9 } - gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x9, 0x3, 0x7, 0x6, 0x7, 0x2, 0x2, 0x2, 0x2, 0x1 } + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x3, 0xA } + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x3, 0x7, 0x6, 0x7, 0x2, 0x2, 0x2, 0x2, 0x1 } gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 } gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE } gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf index 191a747585..2cd13aa2b6 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf @@ -18,6 +18,7 @@ VERSION_STRING = 1.0 [Sources] + Cn913xDbA/Dbg2.aslc Cn913xDbA/Dsdt.asl Cn913xDbA/Mcfg.aslc Fadt.aslc diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf index bbf1b5133a..0c9fb82682 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf @@ -19,6 +19,7 @@ [Sources] Cn9131DbA/Ssdt.asl + Cn913xDbA/Dbg2.aslc Cn913xDbA/Dsdt.asl Cn913xDbA/Mcfg.aslc Fadt.aslc diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h index 283867692e..b93799dd03 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h @@ -11,6 +11,8 @@ #include <IndustryStandard/Acpi.h> +#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACPI_5_0_BYTE, Address } + #define ACPI_OEM_ID_ARRAY {'M','V','E','B','U',' '} #define ACPI_OEM_REVISION 0 #define ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O') diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h new file mode 100644 index 0000000000..4584967016 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h @@ -0,0 +1,9 @@ +/** + + Copyright (C) 2021, Semihalf. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#define CN913X_DBG2_UART_REG_BASE 0xF2702000 diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h b/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h index 6befe2ae54..83006ebd8a 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h @@ -22,6 +22,8 @@ #define CP_GIC_SPI_CP0_USB_H1 112 #define CP_GIC_SPI_CP0_USB_H0 113 #define CP_GIC_SPI_CP0_SATA_H0 114 +#define CP_GIC_SPI_CP0_UART0 121 +#define CP_GIC_SPI_CP0_UART1 122 #define CP_GIC_SPI_CP1_PCI0 288 #define CP_GIC_SPI_CP1_PCI1 289 diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc new file mode 100644 index 0000000000..bea55d0114 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc @@ -0,0 +1,74 @@ +/** @file +* Debug Port Table (DBG2) +* +* Copyright (c) 2020 Linaro Ltd. All rights reserved. +* Copyright (c) 2021 ARM Ltd. All rights reserved. +* Copyright (c) 2021 Semihalf. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include <IndustryStandard/Acpi.h> +#include <IndustryStandard/DebugPort2Table.h> +#include <Library/AcpiLib.h> +#include <Library/PcdLib.h> + +#include "AcpiHeader.h" +#include "Cn913xDbA/Dbg2.h" + +#pragma pack(1) + +#define CN913X_UART_STR { '\\', '_', 'S', 'B', '.', 'C', 'O', 'M', '2', 0x00 } + +typedef struct { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister; + UINT32 AddressSize; + UINT8 NameSpaceString[10]; +} DBG2_DEBUG_DEVICE_INFORMATION; + +typedef struct { + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description; + DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo; +} DBG2_TABLE; + + +STATIC DBG2_TABLE Dbg2 = { + { + __ACPI_HEADER ( + EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE, + DBG2_TABLE, + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION + ), + OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo), + 1 /* NumberOfDebugPorts */ + }, + { + { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, + sizeof (DBG2_DEBUG_DEVICE_INFORMATION), + 1, /* NumberofGenericAddressRegisters */ + 10, /* NameSpaceStringLength */ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString), + 0, /* OemDataLength */ + 0, /* OemDataOffset */ + EFI_ACPI_DBG2_PORT_TYPE_SERIAL, + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_SUBSET_COMPATIBLE_WITH_MS_DBGP_SPEC, + { + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + }, + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) + }, + MV_UART_AS32 (CN913X_DBG2_UART_REG_BASE), /* BaseAddress */ + SIZE_4KB, /* AddressSize */ + CN913X_UART_STR, /* NameSpaceString */ + } +}; + +#pragma pack() + +// Reference the table being generated to prevent the optimizer from removing +// the data structure from the executable +VOID* CONST ReferenceAcpiTable = &Dbg2; diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl index 536df8ab4b..7335e443c6 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl @@ -9,6 +9,7 @@ **/ +#include "Cn913xDbA/Dbg2.h" #include "Cn913xDbA/Pcie.h" #include "IcuInterrupts.h" @@ -199,6 +200,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) { Name (_HID, "MRVL0001") // _HID: Hardware ID Name (_CID, "HISI0031") // _CID: Compatible ID + Name (_UID, 0x00) // _UID: Unique ID Method (_STA) // _STA: Device status { Return (0xF) @@ -225,6 +227,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3) }) } + Device (COM2) + { + Name (_HID, "MRVL0001") // _HID: Hardware ID + Name (_CID, "HISI0031") // _CID: Compatible ID + Name (_UID, 0x01) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_ADR, CN913X_DBG2_UART_REG_BASE) // _ADR: Address + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + CN913X_DBG2_UART_REG_BASE, // Address Base + 0x00000100, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_CP0_UART0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", FixedPcdGet32 (PcdSerialClockRate) }, + Package () { "reg-io-width", 1 }, + Package () { "reg-shift", 2 }, + } + }) + } + Device (SMI0) { Name (_HID, "MRVL0100") // _HID: Hardware ID diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc index 2a3415f0a6..2dda2def81 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc @@ -15,8 +15,6 @@ #include "AcpiHeader.h" -#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACPI_5_0_BYTE, Address } - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { __ACPI_HEADER(EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, -- 2.29.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [edk2-platforms PATCH 4/7] SolidRun/Armada80x0McBin: AcpiTables: Introduce DBG2 table 2021-07-19 9:30 [edk2-platforms PATCH 0/7] Marvell ACS improvements Marcin Wojtas ` (2 preceding siblings ...) 2021-07-19 9:30 ` [edk2-platforms PATCH 3/7] Marvell/Cn913xDbA: AcpiTables: Introduce DBG2 table Marcin Wojtas @ 2021-07-19 9:30 ` Marcin Wojtas 2021-07-19 9:30 ` [edk2-platforms PATCH 5/7] Marvell: Armada7k8k/OcteonTx: Switch to MonotonicCounterRuntimeDxe Marcin Wojtas ` (3 subsequent siblings) 7 siblings, 0 replies; 19+ messages in thread From: Marcin Wojtas @ 2021-07-19 9:30 UTC (permalink / raw) To: devel Cc: leif, ardb+tianocore, jaz, gjb, upstream, Samer.El-Haj-Mahmoud, jon, Marcin Wojtas The DBG2 table is mandatory as per SBBR v1.2 specification. Expose it via J25 jumper on the Armada 8040 MacchiatoBin platform. Signed-off-by: Marcin Wojtas <mw@semihalf.com> --- Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf | 1 + Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h | 2 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h | 9 +++ Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h | 2 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc | 74 ++++++++++++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 33 +++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc | 2 - 7 files changed, 121 insertions(+), 2 deletions(-) create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf index 7cf9ecfbfd..98e5cc8b6e 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf @@ -18,6 +18,7 @@ VERSION_STRING = 1.0 [Sources] + Armada80x0McBin/Dbg2.aslc Armada80x0McBin/Dsdt.asl Armada80x0McBin/Mcfg.aslc Fadt.aslc diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h b/Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h index 90ab607845..9d83ba7837 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h @@ -11,6 +11,8 @@ #include <IndustryStandard/Acpi.h> +#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACPI_5_0_BYTE, Address } + #define ACPI_OEM_ID_ARRAY {'M','V','E','B','U',' '} #define ACPI_OEM_REVISION 0 #define ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O') diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h new file mode 100644 index 0000000000..b8ac770ed5 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h @@ -0,0 +1,9 @@ +/** + + Copyright (C) 2021, Semihalf. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#define ARMADA80X0_MCBIN_DBG2_UART_REG_BASE 0xF2702100 diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h b/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h index dd33cb5e7b..b106790913 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h @@ -22,6 +22,8 @@ #define CP_GIC_SPI_CP0_USB_H1 112 #define CP_GIC_SPI_CP0_USB_H0 113 #define CP_GIC_SPI_CP0_SATA_H0 114 +#define CP_GIC_SPI_CP0_UART0 121 +#define CP_GIC_SPI_CP0_UART1 122 #define CP_GIC_SPI_CP1_PCI0 288 #define CP_GIC_SPI_CP1_PCI1 289 diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc new file mode 100644 index 0000000000..1e6d99ee9e --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc @@ -0,0 +1,74 @@ +/** @file +* Debug Port Table (DBG2) +* +* Copyright (c) 2020 Linaro Ltd. All rights reserved. +* Copyright (c) 2021 ARM Ltd. All rights reserved. +* Copyright (c) 2021 Semihalf. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include <IndustryStandard/Acpi.h> +#include <IndustryStandard/DebugPort2Table.h> +#include <Library/AcpiLib.h> +#include <Library/PcdLib.h> + +#include "AcpiHeader.h" +#include "Armada80x0McBin/Dbg2.h" + +#pragma pack(1) + +#define ARMADA7K8K_UART_STR { '\\', '_', 'S', 'B', '.', 'C', 'O', 'M', '2', 0x00 } + +typedef struct { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister; + UINT32 AddressSize; + UINT8 NameSpaceString[10]; +} DBG2_DEBUG_DEVICE_INFORMATION; + +typedef struct { + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description; + DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo; +} DBG2_TABLE; + + +STATIC DBG2_TABLE Dbg2 = { + { + __ACPI_HEADER ( + EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE, + DBG2_TABLE, + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION + ), + OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo), + 1 /* NumberOfDebugPorts */ + }, + { + { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, + sizeof (DBG2_DEBUG_DEVICE_INFORMATION), + 1, /* NumberofGenericAddressRegisters */ + 10, /* NameSpaceStringLength */ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString), + 0, /* OemDataLength */ + 0, /* OemDataOffset */ + EFI_ACPI_DBG2_PORT_TYPE_SERIAL, + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_SUBSET_COMPATIBLE_WITH_MS_DBGP_SPEC, + { + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + }, + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) + }, + MV_UART_AS32 (ARMADA80X0_MCBIN_DBG2_UART_REG_BASE), /* BaseAddress */ + SIZE_4KB, /* AddressSize */ + ARMADA7K8K_UART_STR, /* NameSpaceString */ + } +}; + +#pragma pack() + +// Reference the table being generated to prevent the optimizer from removing +// the data structure from the executable +VOID* CONST ReferenceAcpiTable = &Dbg2; diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl index 1ecbd0309c..a7d1c76e07 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl @@ -8,6 +8,7 @@ **/ +#include "Armada80x0McBin/Dbg2.h" #include "Armada80x0McBin/Pcie.h" #include "IcuInterrupts.h" @@ -246,6 +247,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) { Name (_HID, "MRVL0001") // _HID: Hardware ID Name (_CID, "HISI0031") // _CID: Compatible ID + Name (_UID, 0x00) // _UID: Unique ID Method (_STA) // _STA: Device status { Return (0xF) @@ -272,6 +274,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3) }) } + Device (COM2) + { + Name (_HID, "MRVL0001") // _HID: Hardware ID + Name (_CID, "HISI0031") // _CID: Compatible ID + Name (_UID, 0x01) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } + Name (_ADR, ARMADA80X0_MCBIN_DBG2_UART_REG_BASE) // _ADR: Address + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + ARMADA80X0_MCBIN_DBG2_UART_REG_BASE, // Address Base + 0x00000100, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + CP_GIC_SPI_CP0_UART1 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", FixedPcdGet32 (PcdSerialClockRate) }, + Package () { "reg-io-width", 1 }, + Package () { "reg-shift", 2 }, + } + }) + } + Device (SMI0) { Name (_HID, "MRVL0100") // _HID: Hardware ID diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc b/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc index 6efc175bdf..48e6699f52 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc @@ -15,8 +15,6 @@ #include "AcpiHeader.h" -#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACPI_5_0_BYTE, Address } - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { __ACPI_HEADER(EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, -- 2.29.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [edk2-platforms PATCH 5/7] Marvell: Armada7k8k/OcteonTx: Switch to MonotonicCounterRuntimeDxe 2021-07-19 9:30 [edk2-platforms PATCH 0/7] Marvell ACS improvements Marcin Wojtas ` (3 preceding siblings ...) 2021-07-19 9:30 ` [edk2-platforms PATCH 4/7] SolidRun/Armada80x0McBin: " Marcin Wojtas @ 2021-07-19 9:30 ` Marcin Wojtas 2021-07-19 9:30 ` [edk2-platforms PATCH 6/7] Marvell/Drivers: SmbiosPlatformDxe: Update Type0 information Marcin Wojtas ` (2 subsequent siblings) 7 siblings, 0 replies; 19+ messages in thread From: Marcin Wojtas @ 2021-07-19 9:30 UTC (permalink / raw) To: devel; +Cc: leif, ardb+tianocore, jaz, gjb, upstream, Samer.El-Haj-Mahmoud, jon From: Grzegorz Bernacki <gjb@semihalf.com> Since the beginning of the EDK2 port Marvell platfroms have been using a dated EmbeddedPkg's MonotonicCounter driver. Switch to the actively maintained MonotonicCounterRuntimeDxe, what fixes ACS3.0 BS.GetNextMonotonicCount test case. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 2 +- Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc index c919d4bfab..05e7f68191 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -476,7 +476,7 @@ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf index e003623f15..bc7284652b 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf @@ -112,7 +112,7 @@ FvNameGuid = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf -- 2.29.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [edk2-platforms PATCH 6/7] Marvell/Drivers: SmbiosPlatformDxe: Update Type0 information 2021-07-19 9:30 [edk2-platforms PATCH 0/7] Marvell ACS improvements Marcin Wojtas ` (4 preceding siblings ...) 2021-07-19 9:30 ` [edk2-platforms PATCH 5/7] Marvell: Armada7k8k/OcteonTx: Switch to MonotonicCounterRuntimeDxe Marcin Wojtas @ 2021-07-19 9:30 ` Marcin Wojtas 2021-07-19 9:30 ` [edk2-platforms PATCH 7/7] Marvell: Armada7k8k/OcteonTx: Bump firmware to "EDK2 SH 1.0" revision Marcin Wojtas 2021-08-01 17:14 ` [edk2-platforms PATCH 0/7] Marvell ACS improvements Ard Biesheuvel 7 siblings, 0 replies; 19+ messages in thread From: Marcin Wojtas @ 2021-07-19 9:30 UTC (permalink / raw) To: devel Cc: leif, ardb+tianocore, jaz, gjb, upstream, Samer.El-Haj-Mahmoud, jon, Marcin Wojtas This patch updates 2 fields of the SMBIOS Type0 table. The "Vendor" and the BiosVersion strings are set according to the values of the newly introduced PCD's. Note, that the gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString could not be used, as its format does match the required by SMBIOS tables (CHAR8 *). Signed-off-by: Marcin Wojtas <mw@semihalf.com> --- Silicon/Marvell/Marvell.dec | 2 ++ Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 2 ++ Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 6 +++--- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index cdf8154d40..482a90da25 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -170,6 +170,8 @@ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035 #Platform description + gMarvellTokenSpaceGuid.PcdFirmwareVendor|"EFI Development Kit II / Semihalf"|VOID*|0x50000104 + gMarvellTokenSpaceGuid.PcdFirmwareVersion|"EDK II"|VOID*|0x50000105 gMarvellTokenSpaceGuid.PcdProductManufacturer|"Marvell"|VOID*|0x50000100 gMarvellTokenSpaceGuid.PcdProductPlatformName|"Marvell Development Board"|VOID*|0x50000101 gMarvellTokenSpaceGuid.PcdProductSerial|"Serial Not Set"|VOID*|0x50000103 diff --git a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf index 7722146292..582c0faf25 100644 --- a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf +++ b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf @@ -40,6 +40,8 @@ gMarvellTokenSpaceGuid.PcdProductPlatformName gMarvellTokenSpaceGuid.PcdProductSerial gMarvellTokenSpaceGuid.PcdProductVersion + gMarvellTokenSpaceGuid.PcdFirmwareVendor + gMarvellTokenSpaceGuid.PcdFirmwareVersion [Protocols] gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED diff --git a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c index a99291e902..ed67a39cb1 100644 --- a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c +++ b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c @@ -77,9 +77,9 @@ STATIC SMBIOS_TABLE_TYPE0 mArmadaDefaultType0 = { }; STATIC CHAR8 CONST *mArmadaDefaultType0Strings[] = { - "EFI Development Kit II / Marvell\0", /* Vendor */ - "EDK II\0", /* BiosVersion */ - __DATE__"\0", /* BiosReleaseDate */ + (CHAR8 CONST *)PcdGetPtr (PcdFirmwareVendor), /* Vendor */ + (CHAR8 CONST *)PcdGetPtr (PcdFirmwareVersion), /* BiosVersion */ + __DATE__"\0", /* BiosReleaseDate */ NULL }; -- 2.29.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [edk2-platforms PATCH 7/7] Marvell: Armada7k8k/OcteonTx: Bump firmware to "EDK2 SH 1.0" revision 2021-07-19 9:30 [edk2-platforms PATCH 0/7] Marvell ACS improvements Marcin Wojtas ` (5 preceding siblings ...) 2021-07-19 9:30 ` [edk2-platforms PATCH 6/7] Marvell/Drivers: SmbiosPlatformDxe: Update Type0 information Marcin Wojtas @ 2021-07-19 9:30 ` Marcin Wojtas 2021-08-01 17:14 ` [edk2-platforms PATCH 0/7] Marvell ACS improvements Ard Biesheuvel 7 siblings, 0 replies; 19+ messages in thread From: Marcin Wojtas @ 2021-07-19 9:30 UTC (permalink / raw) To: devel Cc: leif, ardb+tianocore, jaz, gjb, upstream, Samer.El-Haj-Mahmoud, jon, Marcin Wojtas After the recent SystemReady ES compliance fixes, ACPI enhancements and other improvements bump revision of the Marvell-based platforms to "EDK2 SH 1.0". Signed-off-by: Marcin Wojtas <mw@semihalf.com> --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc index 05e7f68191..d398d9432f 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -241,7 +241,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0xF93D0000 [PcdsFixedAtBuild.common] - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"MARVELL_EFI" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"EDK2 SH 1.0" gArmPlatformTokenSpaceGuid.PcdCoreCount|4 gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 @@ -381,6 +381,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0 gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0302 + gMarvellTokenSpaceGuid.PcdFirmwareVersion|"EDK2 SH 1.0" # TRNG gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000 -- 2.29.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [edk2-platforms PATCH 0/7] Marvell ACS improvements 2021-07-19 9:30 [edk2-platforms PATCH 0/7] Marvell ACS improvements Marcin Wojtas ` (6 preceding siblings ...) 2021-07-19 9:30 ` [edk2-platforms PATCH 7/7] Marvell: Armada7k8k/OcteonTx: Bump firmware to "EDK2 SH 1.0" revision Marcin Wojtas @ 2021-08-01 17:14 ` Ard Biesheuvel 7 siblings, 0 replies; 19+ messages in thread From: Ard Biesheuvel @ 2021-08-01 17:14 UTC (permalink / raw) To: Marcin Wojtas Cc: edk2-devel-groups-io, Leif Lindholm, Ard Biesheuvel, Grzegorz Jaszczyk, Grzegorz Bernacki, upstream, Samer El-Haj-Mahmoud, Jon Nettleton On Mon, 19 Jul 2021 at 11:30, Marcin Wojtas <mw@semihalf.com> wrote: > > Hi, > > This new series comes with the remaining improvements that allow > the ACS3.0 test suite to pass the SBSA/FWTS/SCT to the > maximum non-HW related extent. Missing _STA methods > and DBG2 description are added to the ACPI tables. > Moreover all platforms start using the maintained > MonotonicCounterRuntimeDxe. Also a build fix is added > for the VariablePolicyHelperLib resolution, that is > required after the recent changes in edk2. > Last but not least the SMBIOS Type0 description > is updated with the actual EDK2 firmare vendor and version > strings. > > More details can be found in the commit logs. > The patchest is publicly available in the github: > https://github.com/semihalf-wojtas-marcin/edk2-platforms/commits/marvell-acs-r20210719 > > Best regards, > Marcin > > > Grzegorz Bernacki (2): > Marvell: Armada7k8k: Add missing VariablePolicyHelperLib resolution > Marvell: Armada7k8k/OcteonTx: Switch to MonotonicCounterRuntimeDxe > > Marcin Wojtas (5): > Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables > Marvell/Cn913xDbA: AcpiTables: Introduce DBG2 table > SolidRun/Armada80x0McBin: AcpiTables: Introduce DBG2 table > Marvell/Drivers: SmbiosPlatformDxe: Update Type0 information > Marvell: Armada7k8k/OcteonTx: Bump firmware to "EDK2 SH 1.0" revision > Pushed as 578ec6f09a00..d84c0545f4b4 with the _STA changes removed. Thanks, > Silicon/Marvell/Marvell.dec | 2 + > Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 4 +- > Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 8 +- > Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 2 +- > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf | 1 + > Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 2 + > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 1 + > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf | 1 + > Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h | 2 + > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h | 9 ++ > Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h | 2 + > Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h | 2 + > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h | 9 ++ > Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h | 2 + > Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 6 +- > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 +++++++++++ > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++++++++++ > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc | 74 ++++++++++++++ > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 105 ++++++++++++++++++++ > Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc | 2 - > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 +++ > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc | 74 ++++++++++++++ > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 89 +++++++++++++++++ > Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc | 2 - > 24 files changed, 530 insertions(+), 13 deletions(-) > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc > > -- > 2.29.0 > ^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2021-08-10 22:12 UTC | newest] Thread overview: 19+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-07-19 9:30 [edk2-platforms PATCH 0/7] Marvell ACS improvements Marcin Wojtas 2021-07-19 9:30 ` [edk2-platforms PATCH 1/7] Marvell: Armada7k8k: Add missing VariablePolicyHelperLib resolution Marcin Wojtas 2021-07-19 9:30 ` [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables Marcin Wojtas 2021-07-19 9:54 ` Ard Biesheuvel 2021-07-19 15:06 ` Marcin Wojtas 2021-07-29 9:46 ` Marcin Wojtas 2021-07-29 9:57 ` Ard Biesheuvel 2021-07-30 9:57 ` Marcin Wojtas 2021-08-01 16:58 ` Ard Biesheuvel 2021-08-10 14:36 ` Samer El-Haj-Mahmoud 2021-08-10 14:41 ` [edk2-devel] " Ard Biesheuvel 2021-08-10 15:01 ` Samer El-Haj-Mahmoud 2021-08-10 22:12 ` Marcin Wojtas 2021-07-19 9:30 ` [edk2-platforms PATCH 3/7] Marvell/Cn913xDbA: AcpiTables: Introduce DBG2 table Marcin Wojtas 2021-07-19 9:30 ` [edk2-platforms PATCH 4/7] SolidRun/Armada80x0McBin: " Marcin Wojtas 2021-07-19 9:30 ` [edk2-platforms PATCH 5/7] Marvell: Armada7k8k/OcteonTx: Switch to MonotonicCounterRuntimeDxe Marcin Wojtas 2021-07-19 9:30 ` [edk2-platforms PATCH 6/7] Marvell/Drivers: SmbiosPlatformDxe: Update Type0 information Marcin Wojtas 2021-07-19 9:30 ` [edk2-platforms PATCH 7/7] Marvell: Armada7k8k/OcteonTx: Bump firmware to "EDK2 SH 1.0" revision Marcin Wojtas 2021-08-01 17:14 ` [edk2-platforms PATCH 0/7] Marvell ACS improvements Ard Biesheuvel
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