From: "Marcin Wojtas" <mw@semihalf.com>
To: devel@edk2.groups.io
Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com,
gjb@semihalf.com, upstream@semihalf.com,
Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com,
Marcin Wojtas <mw@semihalf.com>
Subject: [edk2-platforms PATCH 0/6] Marvell multiple PCIE support
Date: Mon, 2 Aug 2021 07:00:45 +0200 [thread overview]
Message-ID: <20210802050051.2831716-1-mw@semihalf.com> (raw)
This patchset is a preparation for adding a new platform
(CN913x CEx7 Evaluation Board). It modifies a common
Marvell code in order to enable multiple PCIE controllers.
Moreover a default interrupt map is reworked, so that to
support all CP11x south bridge units.
Last but not least, a custom initialization sequence
can be executed thanks to a new board description library
extension.
More details can be found in the commit logs.
The patchest is publicly available in the github:
https://github.com/semihalf-wojtas-marcin/edk2-platforms/commits/pcie-r20210802
Best regards,
Marcin
Kamil Koczurek (1):
Marvell: Armada7k8k/OcteonTx: Add multiple PCIE ports support
Marcin Wojtas (5):
Marvell: Armada7k8k/OcteonTx: Allow memory mapping for more config
spaces
Marvell: Armada7k8k/OcteonTx: Allow tuning PCIE config space size
Marvell: Armada7k8kPciHostBridgeLib: Remove ECAM base limitation
Marvell: Armada7k8k/OcteonTX: Enable additional board configuration
Marvell: IcuLib: Rework default interrupt map
Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 7 --
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 7 --
Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf | 1 +
Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf | 1 +
Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.inf | 11 +-
Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h | 48 ++++----
Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 10 ++
Silicon/Marvell/Library/IcuLib/IcuLib.h | 6 +-
Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h | 61 +++++++----
Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.c | 11 ++
Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDescLib.c | 11 ++
Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c | 11 ++
Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c | 11 ++
Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.c | 11 ++
Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c | 2 +
Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c | 18 ++-
Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.c | 15 ++-
Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c | 1 -
Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.c | 69 +++++++++++-
Silicon/Marvell/Library/IcuLib/IcuLib.c | 115 ++++++--------------
20 files changed, 267 insertions(+), 160 deletions(-)
--
2.29.0
next reply other threads:[~2021-08-02 5:01 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-02 5:00 Marcin Wojtas [this message]
2021-08-02 5:00 ` [edk2-platforms PATCH 1/6] Marvell: Armada7k8k/OcteonTx: Allow memory mapping for more config spaces Marcin Wojtas
2021-08-02 5:00 ` [edk2-platforms PATCH 2/6] Marvell: Armada7k8k/OcteonTx: Allow tuning PCIE config space size Marcin Wojtas
2021-08-02 5:00 ` [edk2-platforms PATCH 3/6] Marvell: Armada7k8kPciHostBridgeLib: Remove ECAM base limitation Marcin Wojtas
2021-08-02 8:43 ` Ard Biesheuvel
2021-08-02 17:00 ` Marcin Wojtas
2021-08-03 6:53 ` Ard Biesheuvel
2021-08-03 7:29 ` Marcin Wojtas
2021-08-02 5:00 ` [edk2-platforms PATCH 4/6] Marvell: Armada7k8k/OcteonTx: Add multiple PCIE ports support Marcin Wojtas
2021-08-02 5:00 ` [edk2-platforms PATCH 5/6] Marvell: Armada7k8k/OcteonTX: Enable additional board configuration Marcin Wojtas
2021-08-02 5:00 ` [edk2-platforms PATCH 6/6] Marvell: IcuLib: Rework default interrupt map Marcin Wojtas
2021-08-03 7:13 ` [edk2-platforms PATCH 0/6] Marvell multiple PCIE support Ard Biesheuvel
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