From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lj1-f178.google.com (mail-lj1-f178.google.com [209.85.208.178]) by mx.groups.io with SMTP id smtpd.web11.15929.1627880460289370327 for ; Sun, 01 Aug 2021 22:01:00 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=XjQUYsHq; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.208.178, mailfrom: mw@semihalf.com) Received: by mail-lj1-f178.google.com with SMTP id e5so22322525ljp.6 for ; Sun, 01 Aug 2021 22:01:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=gALhKU0tv7wAavPiawC3e/o/OaYIYbIA1TWyuIL7XHw=; b=XjQUYsHq5J/sWr4xqWdqJk1Q43B8gfzYLNaarPtOoSVSnLSPrUuQcHlc/FmqDDH91J RYgKEQYAEy91yf7lUjkhAycxfIF2xG//HNzuhZYTFSXPx3+QXHTfRgEcVNLU8DMJ+EJr WciLrMgaBkdY43sQpQUJ+N4K2J9A6HnxQf5XrXTIZE08zAuYETf9PYgcN6eEKLuLQkZS Fp4tVStlSsNpQGBAi0cHAnlbzeXf9EjQzGQmsSyuWO7Hr1I7AE5tAH2MG+mbllwRfEmf n86oRRv3wYuCVDwSfvfv8a+b2NOom8e0YbL6paCmvZHgZVvNFM1WYXYNGOXlxRXTLvEr Ffhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=gALhKU0tv7wAavPiawC3e/o/OaYIYbIA1TWyuIL7XHw=; b=WExdnBxlTRdFraoo8wG5VB8lpqhKiY8RieUUyRry3i2uLjen5ml+LO8AUcWA19nz2E wsrkMcljSwm1S+IZhwtEuBxBKVqKTwiaQlzgiovm+BkcwDYkKvA9df4VsxEOUJ79KEQG uoxXt/4JBZWa76LpnrCif5t/FfNm2Dbbom6mc9xRSM5HgwMFtxuIvYWqP19bqh1A7ZEm 1WE6mhPx50WAyIp5DteRTBRrx9KugcQ+YvgerQUnyknDiq1WDZXk3SL6Hyto23s/CNQw D+tkUGJKCX/JXZ2imn/f7Etipqor/02KP+L6NpYWqPcMY8FeZ3u+vmY6s/4JaH9s5oWC W5vQ== X-Gm-Message-State: AOAM530/6nNr65OpFReLciFjal80J2NobjaFzsojEBR41pCkr5BWsIdU 6C9O3k6/5Ua18VGhotaVB86klfa0h7jTKF74 X-Google-Smtp-Source: ABdhPJyHSg4izjGSxVh5ughudQZfnTJul5FpBcvu+rphUkIhCFLL6pBl2BnO6sJT44wWdRibxI2R5A== X-Received: by 2002:a2e:720f:: with SMTP id n15mr10174435ljc.333.1627880458570; Sun, 01 Aug 2021 22:00:58 -0700 (PDT) Return-Path: Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id g17sm359163lfv.210.2021.08.01.22.00.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Aug 2021 22:00:58 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Marcin Wojtas Subject: [edk2-platforms PATCH 0/6] Marvell multiple PCIE support Date: Mon, 2 Aug 2021 07:00:45 +0200 Message-Id: <20210802050051.2831716-1-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This patchset is a preparation for adding a new platform (CN913x CEx7 Evaluation Board). It modifies a common Marvell code in order to enable multiple PCIE controllers. Moreover a default interrupt map is reworked, so that to support all CP11x south bridge units. Last but not least, a custom initialization sequence can be executed thanks to a new board description library extension. More details can be found in the commit logs. The patchest is publicly available in the github: https://github.com/semihalf-wojtas-marcin/edk2-platforms/commits/pcie-r20210802 Best regards, Marcin Kamil Koczurek (1): Marvell: Armada7k8k/OcteonTx: Add multiple PCIE ports support Marcin Wojtas (5): Marvell: Armada7k8k/OcteonTx: Allow memory mapping for more config spaces Marvell: Armada7k8k/OcteonTx: Allow tuning PCIE config space size Marvell: Armada7k8kPciHostBridgeLib: Remove ECAM base limitation Marvell: Armada7k8k/OcteonTX: Enable additional board configuration Marvell: IcuLib: Rework default interrupt map Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 7 -- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 7 -- Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf | 1 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf | 1 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.inf | 11 +- Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h | 48 ++++---- Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 10 ++ Silicon/Marvell/Library/IcuLib/IcuLib.h | 6 +- Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h | 61 +++++++---- Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.c | 11 ++ Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDescLib.c | 11 ++ Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c | 11 ++ Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c | 11 ++ Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.c | 11 ++ Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c | 2 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c | 18 ++- Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.c | 15 ++- Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c | 1 - Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.c | 69 +++++++++++- Silicon/Marvell/Library/IcuLib/IcuLib.c | 115 ++++++-------------- 20 files changed, 267 insertions(+), 160 deletions(-) -- 2.29.0