From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lf1-f43.google.com (mail-lf1-f43.google.com [209.85.167.43]) by mx.groups.io with SMTP id smtpd.web08.16085.1627880461426155379 for ; Sun, 01 Aug 2021 22:01:01 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=N+rs3Lcy; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.167.43, mailfrom: mw@semihalf.com) Received: by mail-lf1-f43.google.com with SMTP id m13so31437065lfg.13 for ; Sun, 01 Aug 2021 22:01:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A7o4S8+5bULOeaEnJx7xee+1b7w1ZvjhySQzD66mueA=; b=N+rs3Lcyq1ovCjBdjp8wgBLqMhGEa00l0ci0rtQ3/eUcHXExKhgaOq6I2HKNNhHba8 9l6mM3PNRdAoXiEa5SM+s0rHj73XAobM4y2isXJbqsnPjKjTAJD/3fuadva4dGO3dmOP oKjF36n870yx07gGjCnl5u4XAWVgzy+fPGxgsjyv0cLoAKUm1ZNhHElL3hISRFlHOyMb D03FsXNtDcj1xTrta78Juds+CqVVcGGa6n4IilEy667yBNTR1TB90zWDomKr3SIlB06x v5o5Zy/BFQcoapQMBIMzyQdlAaf08gNNB+jrbkahZY2S7HIWr9lhWPIpDt91N7N9WGZv TMfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A7o4S8+5bULOeaEnJx7xee+1b7w1ZvjhySQzD66mueA=; b=Tsx/K8R4lq79MPQ3vSH3l0HGqN2Qh+MscXJFdTJ5pgvM3BjTpE12Halv9wWVdrNI8Z //nBfAMDBWgWHQeesh7Gkc4t34xMFiaEB4mdI9HXTNZaZnq4VZbt4Aad+etMI1AYd52S DpyjRBe7L+0iFkN23sVe741XiMK5iE8soBXiL7HQD8iZwHqbL+nbxJDF72aHHdKqmGjg tyRtCtOc2T758NPRIGC9mKrzffLx/3HhJ/sPfa0S2MCxo1Ukt1MrJtabMtBtJU5+wOoq cT3pZ6QxQ1Gy35QBhI356jGYPufYN6CrmYgoJ0HHFOvXPsIPgrEd7QMqvJiEUrBhMnZO 1NVQ== X-Gm-Message-State: AOAM533HTAxJ5pL0qzg4ym/lfvrzjK8kuRQ1owCcJNLLI8dnQzWTNLPx rLE6eiSGy5v219Qxbn/L3cbvBSzlJc0gSvWB X-Google-Smtp-Source: ABdhPJyBLp5EYXV1NGpEI46a0vI5Lh5m+cM3psysIdDDiNOvIpyzcOMG0iCKZ5/cTFnLUed9daGHjw== X-Received: by 2002:ac2:54a4:: with SMTP id w4mr11655857lfk.344.1627880459499; Sun, 01 Aug 2021 22:00:59 -0700 (PDT) Return-Path: Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id g17sm359163lfv.210.2021.08.01.22.00.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Aug 2021 22:00:59 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Marcin Wojtas Subject: [edk2-platforms PATCH 1/6] Marvell: Armada7k8k/OcteonTx: Allow memory mapping for more config spaces Date: Mon, 2 Aug 2021 07:00:46 +0200 Message-Id: <20210802050051.2831716-2-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210802050051.2831716-1-mw@semihalf.com> References: <20210802050051.2831716-1-mw@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Until now the virtual memory map for the single PCIE configuration space was hardcoded via PCDs and assumed adjacency to the SoC MMIO region (0xf0000000 - 4GB). Remove this limitation by splitting the regions and allowing to obtain the PCIE configuration space settings from ArmadaBoardDescLib. It is a preparation patch for adding support for multiple PCIE controllers. Signed-off-by: Marcin Wojtas --- Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 3 -= -- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 3 -= -- Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf | 1 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c | 16 += ++++++++++++++- 4 files changed, 16 insertions(+), 7 deletions(-) diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell= /Cn913xDb/Cn9130DbA.dsc.inc index 756d875f6c..41d9cb9247 100644 --- a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc +++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc @@ -100,8 +100,5 @@ # RTC=0D gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000=0D =0D - # SoC Configuration Space=0D - gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xD0000000=0D -=0D # Variable store=0D gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|FALSE=0D diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index d398d9432f..b1aa0ae4d0 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -400,9 +400,6 @@ gArmTokenSpaceGuid.PcdPciIoTranslation|0xEFF00000=0D gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000=0D =0D - # SoC Configuration Space=0D - gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xE0000000=0D -=0D !if $(CAPSULE_ENABLE)=0D [PcdsDynamicExDefault.common.DEFAULT]=0D gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor= |{0x0}|VOID*|0x100=0D diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib= .inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf index 94427177ef..8b77a07ab3 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf @@ -20,6 +20,7 @@ Silicon/Marvell/Marvell.dec=0D =0D [LibraryClasses]=0D + ArmadaBoardDescLib=0D ArmadaSoCDescLib=0D ArmLib=0D ArmSmcLib=0D diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib= Mem.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c index cc19694d37..853c1b4e56 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c @@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =0D #include =0D =0D +#include =0D #include =0D #include =0D #include =0D @@ -81,6 +82,9 @@ ArmPlatformGetVirtualMemoryMap ( UINT64 MemHighStart;=0D UINT64 MemHighSize;=0D UINT64 ConfigSpaceBaseAddr;=0D + UINTN PcieControllerCount;=0D + UINTN PcieIndex;=0D + MV_PCIE_CONTROLLER CONST *PcieControllers;=0D EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;=0D EFI_STATUS Status;=0D =0D @@ -125,12 +129,22 @@ ArmPlatformGetVirtualMemoryMap ( mVirtualMemoryTable[Index].Length =3D MemLowSize;=0D mVirtualMemoryTable[Index].Attributes =3D DDR_ATTRIBUTES_CACHED;=0D =0D - // Configuration space=0D + // SoC MMIO configuration space=0D mVirtualMemoryTable[++Index].PhysicalBase =3D ConfigSpaceBaseAddr;=0D mVirtualMemoryTable[Index].VirtualBase =3D ConfigSpaceBaseAddr;=0D mVirtualMemoryTable[Index].Length =3D SIZE_4GB - ConfigSpaceBas= eAddr;=0D mVirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBU= TE_DEVICE;=0D =0D + // PCIE ECAM=0D + Status =3D ArmadaBoardPcieControllerGet (&PcieControllers, &PcieControll= erCount);=0D + ASSERT_EFI_ERROR (Status);=0D + for (PcieIndex =3D 0; PcieIndex < PcieControllerCount; PcieIndex++) {=0D + mVirtualMemoryTable[++Index].PhysicalBase =3D PcieControllers[PcieInd= ex].ConfigSpaceAddress;=0D + mVirtualMemoryTable[Index].VirtualBase =3D PcieControllers[PcieInd= ex].ConfigSpaceAddress;=0D + mVirtualMemoryTable[Index].Length =3D SIZE_256MB;=0D + mVirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRI= BUTE_DEVICE;=0D + }=0D +=0D if (MemSize > MemLowSize) {=0D //=0D // If we have more than MemLowSize worth of DRAM, the remainder will b= e=0D --=20 2.29.0