From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lj1-f181.google.com (mail-lj1-f181.google.com [209.85.208.181]) by mx.groups.io with SMTP id smtpd.web12.16047.1627880462147930050 for ; Sun, 01 Aug 2021 22:01:02 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=MyMWSxh6; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.208.181, mailfrom: mw@semihalf.com) Received: by mail-lj1-f181.google.com with SMTP id e5so22322614ljp.6 for ; Sun, 01 Aug 2021 22:01:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4KMknqaqq/TOGPyhLyVlXcKJaqfwnA0kAyXx0yIVyLU=; b=MyMWSxh6V9r+KMLSpXA+dXeQFfNT5x3oqJno9c2C1ArMRwkBvs0R8s+SI+H7EmkvME AyyFCvSDEe3qoVe75ZL7NJwU5gdDbJZ+rRqDZJeqB2GhocSTj201DTmaw4R/KchIBT1p z+nDsfoTEVX5u7IHc1S7d/cAW2GJFEZn4xvlwpuFJfK0rTFwoOUd4PN7lCY43gxBbidD chqpyGS7OtHMeMR1K/UkcEe0zUdw41h4dDCp18W0QDRVMmLht2UI3prxjTJBcv8CiMsd Jfv8fvWnS/8RyUW4qibDnOu8tuExtea8FVCS0uNOdtqXAFOmvWP3Js8oAQzf17eCYZu4 6Rzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4KMknqaqq/TOGPyhLyVlXcKJaqfwnA0kAyXx0yIVyLU=; b=itKlo5AHj5fm4zwnAnlsqjcUO0DzxH4FVX7BHx+CyRRN7hFA6BoLlkEr6qcl9DnXrO Fap5VD8nAHClevjGj3+b9lTIvB/SKS3dNlvquL5YQb0Ov0U5hCUxRyiUX/s3AHnZ4A0c sPFVG1rzFA1oj+TgO12JrsURT3qklVTw0J3Ph6wPJ/MMw3mH0YRiaD8z8ne8oyhosjgq QBRK7ZJwvlyzumIwnmRx536TPSIbEouBspqoev2S4shMO88mdSJCrGQB1qUyaxj/1wA5 ncyqd9lfqt3ESYYzskES5wMTdgulctp2VaS3wAtgXnEm3CX85ph95gY/uShfttkPAed+ XyHw== X-Gm-Message-State: AOAM531N0UNRKzZ3QCaR0sLAogv4tzRWYcnRm8ZeJ0PrZ67vidcnm7lF Qrlin7BLz/P6QZoc4Jlg16G2M9vP5TgGUw9z X-Google-Smtp-Source: ABdhPJx4imLdIDW2nuqApoZMPc1WZvqfzyjlU3DsovT957rDEjOaHfzcI2sgpMh/WYZJ11nPCAu7Tw== X-Received: by 2002:a2e:321a:: with SMTP id y26mr9921638ljy.463.1627880460511; Sun, 01 Aug 2021 22:01:00 -0700 (PDT) Return-Path: Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id g17sm359163lfv.210.2021.08.01.22.00.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Aug 2021 22:01:00 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Marcin Wojtas Subject: [edk2-platforms PATCH 2/6] Marvell: Armada7k8k/OcteonTx: Allow tuning PCIE config space size Date: Mon, 2 Aug 2021 07:00:47 +0200 Message-Id: <20210802050051.2831716-3-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210802050051.2831716-1-mw@semihalf.com> References: <20210802050051.2831716-1-mw@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Until now it was assumed that the configuration space size is 256MB. Allow setting different values in the board description library instance for each platform. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 1 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c | 4 ++= +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index 2ad19aae7a..80c55eb3a7 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -111,6 +111,7 @@ typedef struct { typedef struct {=0D EFI_PHYSICAL_ADDRESS PcieDbiAddress;=0D EFI_PHYSICAL_ADDRESS ConfigSpaceAddress;=0D + UINT64 ConfigSpaceSize;=0D BOOLEAN HaveResetGpio;=0D MV_GPIO_PIN PcieResetGpio;=0D UINT64 PcieBusMin;=0D diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib= Mem.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c index 853c1b4e56..43aacb7a11 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c @@ -141,7 +141,9 @@ ArmPlatformGetVirtualMemoryMap ( for (PcieIndex =3D 0; PcieIndex < PcieControllerCount; PcieIndex++) {=0D mVirtualMemoryTable[++Index].PhysicalBase =3D PcieControllers[PcieInd= ex].ConfigSpaceAddress;=0D mVirtualMemoryTable[Index].VirtualBase =3D PcieControllers[PcieInd= ex].ConfigSpaceAddress;=0D - mVirtualMemoryTable[Index].Length =3D SIZE_256MB;=0D + mVirtualMemoryTable[Index].Length =3D (PcieControllers[PcieIn= dex].ConfigSpaceSize =3D=3D 0) ?=0D + SIZE_256MB :=0D + PcieControllers[PcieIndex= ].ConfigSpaceSize;=0D mVirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRI= BUTE_DEVICE;=0D }=0D =0D --=20 2.29.0