From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) by mx.groups.io with SMTP id smtpd.web10.16138.1627880463166850112 for ; Sun, 01 Aug 2021 22:01:03 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=0pVLembG; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.167.44, mailfrom: mw@semihalf.com) Received: by mail-lf1-f44.google.com with SMTP id bq29so5897074lfb.5 for ; Sun, 01 Aug 2021 22:01:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eHHsx3LtO3lpdhRyjGrHz6CoczYXNrWjIWzLvgXpZfY=; b=0pVLembGgc7tOFH6XN1QpIJea7h+67HKcYZWgX3aHn2PYHsm9SaO4foTJnyVlQMwoe HA9IKp1jTLqKtCDVhwIUOnIGKF0iI+ek7czzolxwb77VAYt0e28oGfV2lbEDKHAIF+Kc B5RsJdfLizHybTrabCdbzbMilC5glk8umCJ5UcpmubhH3wylr2txWFg09e9nGMdnLVz3 fHwagnFx3x2/zkwY6DSa/Q9tAlgASOjPnAWurMZGmmGZqIZoykB5GQl7vbms/JxRo0xt An0JNi+XUqHPpuWa+BeymBmNIG4SONwLaK/xz+SMz6qhb/f8/zIYa7EZcJVTT7eVrQ9y AJJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eHHsx3LtO3lpdhRyjGrHz6CoczYXNrWjIWzLvgXpZfY=; b=QFLOn64WtZ6ltF8O3nm9b/eyw2eFGiBIgKZQN7TW99EtjFcn0UKjkkq8Rr7daqWs4Q UpehGWNjFVptWQy9hccu+sUJ+3rZo6QT38mJiZOaN0lsVbGY8r54EXrJrU/0DGYi76xn sJo7pJo9EaheBxr/wGXzb4eDG80UI7L9XuSfVfa5VDZ5fKJ5e5JAoUFIEVS4lrsLykk1 XIUh6IpvPFFPjTgmfdrlwruOxwqEf7wp0ky9yC0OZyZSLlEhNeJbRia6jOpFGkmucr33 qY36JCC17myYJ6z7gDVx64iyYkcLtu+MAYVSsBhjS34jEEdZ4V+A2r67SB9ArzdzR05w k0bg== X-Gm-Message-State: AOAM532bv+ILKPDvsAMbN5/fcQC/FgTiPsPSKGyIAQQM2I8CaWlEPnWT i5Xh7bZlZdEDk0vtnZePZLMpPof/A/SXumhQ X-Google-Smtp-Source: ABdhPJy2M9H1pnv/O5f3f8n2ID5uuyoCScLFCXDUiVLAKG1DXBOpHk5CCww4QIgZe7OgwjgD5LrkIg== X-Received: by 2002:ac2:53ab:: with SMTP id j11mr3837004lfh.391.1627880461544; Sun, 01 Aug 2021 22:01:01 -0700 (PDT) Return-Path: Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id g17sm359163lfv.210.2021.08.01.22.01.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Aug 2021 22:01:01 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Marcin Wojtas Subject: [edk2-platforms PATCH 3/6] Marvell: Armada7k8kPciHostBridgeLib: Remove ECAM base limitation Date: Mon, 2 Aug 2021 07:00:48 +0200 Message-Id: <20210802050051.2831716-4-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210802050051.2831716-1-mw@semihalf.com> References: <20210802050051.2831716-1-mw@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable On CN913x-based platforms it is possible to have up to 9 PCIE root complexes. In such case it may be necessary to configure more configuration spaces with smaller bus count, so that to fit the memory layout constraints. For that purpose remove forcing ECAM base to be divisible by SIZE_256MB. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridg= eLibConstructor.c | 1 - 1 file changed, 1 deletion(-) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/= PciHostBridgeLibConstructor.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k= 8kPciHostBridgeLib/PciHostBridgeLibConstructor.c index 067e57a2dc..87e57aeae3 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHost= BridgeLibConstructor.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHost= BridgeLibConstructor.c @@ -219,7 +219,6 @@ Armada7k8kPciHostBridgeLibConstructor ( PcieController =3D &(BoardPcieDescription->PcieControllers[Index]);=0D =0D ASSERT (PcieController->PcieBusMin =3D=3D 0);=0D - ASSERT (PcieController->ConfigSpaceAddress % SIZE_256MB =3D=3D 0);=0D =0D if (PcieController->HaveResetGpio =3D=3D TRUE) {=0D /* Reset PCIE slot */=0D --=20 2.29.0