From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qt1-f180.google.com (mail-qt1-f180.google.com [209.85.160.180]) by mx.groups.io with SMTP id smtpd.web08.57.1628109409458706217 for ; Wed, 04 Aug 2021 13:36:49 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmail.com header.s=20161025 header.b=LINoPUXr; spf=pass (domain: gmail.com, ip: 209.85.160.180, mailfrom: benjamin.doron00@gmail.com) Received: by mail-qt1-f180.google.com with SMTP id h27so2292601qtu.9 for ; Wed, 04 Aug 2021 13:36:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/TNYSL9lCPz7etoxlVIMHPYJKA0458pfJoCsXLPsngw=; b=LINoPUXrohmRKWGEMzgkKxPNdzPa9NomqvRYlAYK94eEwMHT4i1494J7DfNNQFsFNF cavnITSQUv5WvB8Td6DdVh4TV0D6+Q/1N8+WLdYnjAhzYIYWdxocNZCovI2aeri0Yfve b0tZJ0UbtLW0aLmn68wLZn/vyX7sRp6JenCSo/kX3n2JVNp/9MRFUZbpADcrHZfBh/wh aqUo3ZBPmaQGjrllX5TlCsUYBtHM3UJyaUQHy3Y6JUE8IsFwUst6Lisb0MINgSUXRN1c eIR4Cryjjn9SbQs71JLxsnKyYVYGthHV0aUW3Wp6QAg11h39HyDBvP1ug/i5bSLwt4HA DJMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/TNYSL9lCPz7etoxlVIMHPYJKA0458pfJoCsXLPsngw=; b=MW4M0eE+znCDDTWTqj71nspT6aPCHObgas4I8WjHEK+VMgsRqlqZQVEhh2IMJYQu99 0GblouEqBTZIqbol/FA7gTHAZriubLoTBxYDbRcDt4AQt+YZZARsfnpjtEfKDvg57vy7 L/LURGfBz3BZ7HJOJu5lCJ21oqpVtsx0YPUi5dH7wwls0YVdpxq+DrV5MvbxTptakBm+ jqeFWxj8aeDYWQ4WCZ3DZbpgdIQDV6NV1D231/BOhPniVA6UnLZl7LefnCNwa6BVSRra DkQOfLGX5wY9Kx+mwL771N1Xj8MFk+xQIIEalejH9qT1/89p0do8SIY+OTgPjaF/MJFN 79KQ== X-Gm-Message-State: AOAM530etpAq909g/qIpzMO805tuh9Ewq/sOo1ewuEXjzSC8Q3AwN8uS 5/qrebz0HL0qtPrtAeqbRDDTyV/I55QsFQ== X-Google-Smtp-Source: ABdhPJx6hZM2uk7nr4rZeGUvfdT4qu8cz+LkxF+HpW4A9jyAIEgParF/MuJVCXNY7wVu082vBPWbpg== X-Received: by 2002:ac8:7c44:: with SMTP id o4mr1310346qtv.191.1628109408124; Wed, 04 Aug 2021 13:36:48 -0700 (PDT) Return-Path: Received: from benjamind-benjamindomain.. ([2607:f2c0:e98c:24:3070:df1c:bdc9:1783]) by smtp.gmail.com with ESMTPSA id c18sm1256679qtb.61.2021.08.04.13.36.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Aug 2021 13:36:47 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Michael Kubacki Subject: [edk2-platforms][PATCH v1 4/4] KabylakeOpenBoardPkg/AspireVn7Dash572G: Add initial support Date: Wed, 4 Aug 2021 16:36:30 -0400 Message-Id: <20210804203630.7080-5-benjamin.doron00@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804203630.7080-1-benjamin.doron00@gmail.com> References: <20210804203630.7080-1-benjamin.doron00@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Add initial support for Acer Aspire VN7-572G (also, "Rayleigh"). Support for the somewhat similar Aspire VN7-792G ("Newgate") - using PCH-H - may be added in the future. This commit squashes local changes to ACPI tables, FSP configuration, flashmap, GPIOs and HDA verb tables. Working: - Board support should be taken as working at boot stage 5 - Security. Additional patches: - "Implement Reset services": Apply https://edk2.groups.io/g/devel/message/= 77743 in advance. This may later be squashed into the "duplicate RVP" commit. - TODO: FspsWrapperPeim must request the global reset properly. Furthermore, PeiPchGlobalReset() must issue the HECI command. - Some other patches in this fork are required for proper functioning. - In-memory debug logging infrastructure uses libraries from https://github.com/benjamindoron/edk2/tree/master In progress: - ACPI and EC support in SMM. - Some specifics are given in the code. Not working: - Dispatch mode: Memory initialisation fails, suspect that MchBar=3D0 is the cause. Since entry offsets in policy header (SaMiscPreMem) mismatch FSP internal definitions (S3Data pointer is missing here), dispatch mode support is now on-hold. - OS drivers for the dGPU will also require ACPI _ROM method. I am (slowly) working on a driver to implement this. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Michael Kubacki Signed-off-by: Benjamin Doron --- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardAcpiTables= .inf | 18 + Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardSsdt.asl = | 35 + Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.asl = | 12 + Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/battery.asl = | 354 ++++++++= ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.asl = | 424 ++++++++= ++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mainboard.asl = | 76 +++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/thermal.asl = | 95 +++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c | 15 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c | 283 ++++++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 6 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c | 35 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c | 16 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h | 3 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c | 4 - Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c | 6 - Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h | 14 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c | 12 - Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 20 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/EcCommands.h= | 5 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/FlashMap= Include.fdf | 60 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library/Boar= dEcLib.h | 112 +++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatform= HookLib/BasePlatformHookLib.c | 662 --------= ---------- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatform= HookLib/BasePlatformHookLib.inf | 51 -- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /DxeAspireVn7Dash572GAcpiTableLib.c | 27 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /DxeBoardAcpiTableLib.c | 11 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /DxeBoardAcpiTableLib.inf | 6 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /DxeMultiBoardAcpiSupportLib.c | 43 -- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /DxeMultiBoardAcpiSupportLib.inf | 49 -- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /SmmAspireVn7Dash572GAcpiEnableLib.c | 50 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /SmmBoardAcpiEnableLib.c | 17 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /SmmBoardAcpiEnableLib.inf | 5 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /SmmMultiBoardAcpiSupportLib.c | 81 --- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /SmmMultiBoardAcpiSupportLib.inf | 48 -- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /SmmSiliconAcpiEnableLib.c | 2 - Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/B= oardEcLib.inf | 28 + Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/E= cCommands.c | 221 ++++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /AspireVn7Dash572GGpioTable.c | 715 ++++++++= ++---------- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /AspireVn7Dash572GHdaVerbTables.c | 321 ++++----- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /AspireVn7Dash572GHsioPtssTables.c | 98 +-- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /AspireVn7Dash572GSpdTable.c | 541 --------= ------- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiAspireVn7Dash572GDetect.c | 121 ++-- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiAspireVn7Dash572GInitLib.h | 35 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiAspireVn7Dash572GInitPostMemLib.c | 177 ++--- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiAspireVn7Dash572GInitPreMemLib.c | 345 +++++---= -- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiBoardInitPostMemLib.c | 11 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiBoardInitPostMemLib.inf | 19 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiBoardInitPreMemLib.c | 36 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiBoardInitPreMemLib.inf | 41 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiMultiBoardInitPostMemLib.c | 40 -- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiMultiBoardInitPostMemLib.inf | 56 -- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiMultiBoardInitPreMemLib.c | 82 --- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiMultiBoardInitPreMemLib.inf | 136 ---- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc = | 169 ++++- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.fdf = | 23 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgBuildOpt= ion.dsc | 2 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc = | 105 ++- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSi= liconPolicyUpdateLib/DxeGopPolicyInit.c | 21 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSi= liconPolicyUpdateLib/DxeSaPolicyUpdate.c | 24 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSi= liconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c | 32 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSi= liconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf | 2 + Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiBoardPolicyUpdate.c | 328 +++++++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c | 41 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf | 16 + Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_board.py = | 68 -- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.cfg = | 15 +- 65 files changed, 3365 insertions(+), 3161 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/Boa= rdAcpiTables.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Ac= pi/BoardAcpiTables.inf new file mode 100644 index 000000000000..0104439b529d --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardAcpiT= ables.inf @@ -0,0 +1,18 @@ +## @file=0D +# Component description file for the Acer Aspire VN7-572G board ACPI tabl= es=0D +#=0D +# Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010005=0D +BASE_NAME =3D BoardAcpiTables=0D +FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD=0D +MODULE_TYPE =3D USER_DEFINED=0D +VERSION_STRING =3D 1.0=0D +=0D +[Sources]=0D + BoardSsdt.asl=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/Boa= rdSsdt.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/Boa= rdSsdt.asl new file mode 100644 index 000000000000..761f8f364b7c --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardSsdt.= asl @@ -0,0 +1,35 @@ +/** @file=0D + This file contains the Aspire VN7-572G SSDT Table ASL code.=0D +=0D +Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +DefinitionBlock (=0D + "Board.aml",=0D + "SSDT",=0D + 0x02,=0D + "ACRSKL",=0D + "AcerSKL ",=0D + 0x20141018=0D + )=0D +{=0D + External (\MDBG, MethodObj)=0D +=0D + // Debug print helper=0D + Method (DBGH, 1)=0D + {=0D + // If present, print to ACPI debug feature's buffer=0D + If (CondRefOf (\MDBG))=0D + {=0D + \MDBG (Arg0)=0D + }=0D + // Always use "Debug" object for operating system=0D + Debug =3D Arg0=0D + }=0D +=0D + // TODO: Add HID support for touchpad, etc.=0D + Include ("ec.asl")=0D + Include ("mainboard.asl")=0D +}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.= asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.asl new file mode 100644 index 000000000000..6fddd9ce602e --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-2-Clause-Patent */=0D +=0D +Device (ADP1)=0D +{=0D + Name (_HID, "ACPI0003" /* Power Source Device */) // _HID: Hardware ID= =0D + Name (_PCL, Package () { \_SB }) // _PCL: Power Consumer List=0D +=0D + Method (_PSR, 0, NotSerialized) // _PSR: Power Source=0D + {=0D + Return (EACS)=0D + }=0D +}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/bat= tery.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/batte= ry.asl new file mode 100644 index 000000000000..f03062a85f07 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/battery.asl @@ -0,0 +1,354 @@ +/* SPDX-License-Identifier: BSD-2-Clause-Patent */=0D +=0D +// TODO: Consider actually enforcing mutex?=0D +Mutex (BMTX, 0)=0D +Name (B0ST, 0) /* Battery 0 status */=0D +=0D +/*=0D + * EC Registers=0D + *=0D + * "EBID" is the battery page selector.=0D + *=0D + *=0D + * Data on the 128 bits following offset=0D + * 0xE0 is accessed in the following order:=0D + *=0D + * Information:=0D + * Page 0: EBCM # start on page 0 #=0D + * Page 0: EBFC=0D + * Page 1: EBDC # switch to page 1 #=0D + * Page 1: EBDV=0D + * Page 1: EBSN=0D + * Page 3: EBDN # switch to page 3 #=0D + * Page 4: EBCH # switch to page 4 #=0D + * Page 2: EBMN # switch to page 2 #=0D + *=0D + * Status:=0D + * Page 0: EBAC # start on page 0 #=0D + * Page 0: EBRC=0D + * Page 0: EBFC=0D + * Page 0: EBVO=0D + */=0D +/* Page 0 */=0D +Field (RAM, ByteAcc, Lock, Preserve)=0D +{=0D + Offset (0xE0),=0D + EBRC, 16, /* Battery remaining capacity */=0D + EBFC, 16, /* Battery full charge capacity */=0D + EBPE, 16,=0D + EBAC, 16, /* Battery present rate */=0D + EBVO, 16, /* Battery voltage */=0D + , 15,=0D + EBCM, 1, /* Battery charging */=0D + EBCU, 16,=0D + EBTV, 16,=0D +}=0D +=0D +/* Page 1 */=0D +Field (RAM, ByteAcc, Lock, Preserve)=0D +{=0D + Offset (0xE0),=0D + EBDC, 16, /* Battery design capacity */=0D + EBDV, 16, /* Battery design voltage */=0D + EBSN, 16, /* Battery serial number */=0D +}=0D +=0D +/* Page 2 */=0D +Field (RAM, ByteAcc, NoLock, Preserve)=0D +{=0D + Offset (0xE0),=0D + EBMN, 128, /* Battery manufacturer */=0D +}=0D +=0D +/* Page 3 */=0D +Field (RAM, ByteAcc, NoLock, Preserve)=0D +{=0D + Offset (0xE0),=0D + EBDN, 128, /* Battery model */=0D +}=0D +=0D +/* Page 4 */=0D +Field (RAM, ByteAcc, NoLock, Preserve)=0D +{=0D + Offset (0xE0),=0D + EBCH, 128, /* Battery type */=0D +}=0D +=0D +#if 0 // TODO: Hook up LGMR (instead of I/O accesses)=0D +OperationRegion (MBB0, SystemMemory, (LGMR + 0x80), 0xFF)=0D +Field (MBB0, ByteAcc, Lock, Preserve)=0D +{=0D + MBRC, 16,=0D + MBFC, 16,=0D + MBPE, 16,=0D + MBAC, 16,=0D + MBVO, 16,=0D + , 15,=0D + MBCM, 1,=0D + MBCU, 16,=0D + MBTV, 16,=0D +}=0D +=0D +Field (MBB0, ByteAcc, Lock, Preserve)=0D +{=0D + Offset (0x10),=0D + MBDC, 16,=0D + MBDV, 16,=0D + MBSN, 16,=0D +}=0D +=0D +Field (MBB0, ByteAcc, Lock, Preserve)=0D +{=0D + Offset (0x40),=0D + MBMN, 128,=0D +}=0D +=0D +Field (MBB0, ByteAcc, Lock, Preserve)=0D +{=0D + Offset (0x50),=0D + MBDN, 256,=0D +}=0D +=0D +Field (MBB0, ByteAcc, Lock, Preserve)=0D +{=0D + Offset (0x70),=0D + MBCH, 128,=0D +}=0D +#endif=0D +=0D +/*=0D + * Arg0: Battery number=0D + * Arg1: Battery Information Package=0D + * Arg2: Status=0D + */=0D +Method (GBIF, 3, Serialized)=0D +{=0D + Acquire (BMTX, 0xFFFF) // Due to EC paging, don't run this with another= function=0D + If (Arg2)=0D + {=0D + Arg1[1] =3D 0xFFFFFFFF=0D + Arg1[2] =3D 0xFFFFFFFF=0D + Arg1[4] =3D 0xFFFFFFFF=0D + Arg1[5] =3D 0=0D + Arg1[6] =3D 0=0D + }=0D + Else=0D + {=0D + EBID =3D 0 // We don't know which page was active=0D + Local0 =3D EBCM=0D + Arg1[0] =3D (Local0 ^ 1)=0D +=0D + Local2 =3D EBFC=0D + EBID =3D 1=0D + Local1 =3D EBDC=0D + If (Local0)=0D + {=0D + Local2 *=3D 10=0D + Local1 *=3D 10=0D + }=0D +=0D + Arg1[1] =3D Local1 // Design capacity=0D + Arg1[2] =3D Local2 // Last full charge capacity=0D + Arg1[4] =3D EBDV // Design voltage=0D + Local6 =3D (Local2 / 100) // Warning capacities; Remainders ignored=0D + Arg1[5] =3D (Local6 * 7) /* Low: 7% */=0D + Arg1[6] =3D ((Local6 * 11) / 2) /* Very low: 5.5% */=0D + Local7 =3D EBSN=0D + Name (SERN, Buffer (0x06) { " " })=0D + Local6 =3D 4=0D + While (Local7)=0D + {=0D + Divide (Local7, 10, Local5, Local7)=0D + SERN[Local6] =3D (Local5 + 0x30) // Add ASCII 0x30 to get character= =0D + Local6--=0D + }=0D +=0D + Arg1[10] =3D SERN // Serial number=0D + EBID =3D 3=0D + Arg1[9] =3D EBDN // Model number=0D + EBID =3D 4=0D + Arg1[11] =3D EBCH // Battery type=0D + EBID =3D 2=0D + Arg1[12] =3D EBMN // OEM information=0D + }=0D +=0D + Release (BMTX)=0D + Return (Arg1)=0D +}=0D +=0D +/*=0D + * Arg0: Battery number=0D + * Arg1: State information=0D + * Arg2: Power units=0D + * Arg3: Battery Status Package=0D + */=0D +Method (GBST, 4, NotSerialized) // All on one page=0D +{=0D + Acquire (BMTX, 0xFFFF) // Due to EC paging, don't run this with another= function=0D + If (Arg1 & 0x02) // BIT1 in "EB0S"=0D + {=0D + Local0 =3D 2=0D + If (Arg1 & 0x20) // "EB0F"=0D + {=0D + Local0 =3D 0=0D + }=0D + }=0D + ElseIf (Arg1 & 0x04) // BIT2 in "EB0S"=0D + {=0D + Local0 =3D 1=0D + }=0D + Else=0D + {=0D + Local0 =3D 0=0D + }=0D +=0D + If (Arg1 & 0x10) // "EB0L"=0D + {=0D + Local0 |=3D 0x04=0D + }=0D +=0D + If (Arg1 & 1) // "EB0A"=0D + {=0D + /*=0D + * Present rate is a 16bit signed int, positive while charging=0D + * and negative while discharging.=0D + */=0D + EBID =3D 0 // We don't know which page was active=0D + Local1 =3D EBAC=0D + Local2 =3D EBRC=0D + If (EACS) // Charging=0D + {=0D + If (Arg1 & 0x20) // "EB0F"=0D + {=0D + Local2 =3D EBFC=0D + }=0D + }=0D +=0D + If (Arg2)=0D + {=0D + Local2 *=3D 10=0D + }=0D +=0D + Local3 =3D EBVO=0D + /*=0D + * The present rate value should be positive unless discharging. If so= ,=0D + * negate present rate.=0D + */=0D + If (Local1 >=3D 0x8000)=0D + {=0D + If (Local0 & 1)=0D + {=0D + Local1 =3D (0x00010000 - Local1)=0D + }=0D + Else=0D + {=0D + Local1 =3D 0 // Full battery, force to 0=0D + }=0D + }=0D + /*=0D + * If that was not the case, we have an EC bug or inconsistency=0D + * and force the value to 0.=0D + */=0D + ElseIf ((Local0 & 0x02) =3D=3D 0)=0D + {=0D + Local1 =3D 0=0D + }=0D +=0D + If (Arg2)=0D + {=0D + Local1 *=3D Local3=0D + Local1 /=3D 1000 /* Remainder ignored */=0D + }=0D + }=0D + Else=0D + {=0D + Local0 =3D 0=0D + Local1 =3D 0xFFFFFFFF=0D + Local2 =3D 0xFFFFFFFF=0D + Local3 =3D 0xFFFFFFFF=0D + }=0D +=0D + Arg3[0] =3D Local0=0D + Arg3[1] =3D Local1=0D + Arg3[2] =3D Local2=0D + Arg3[3] =3D Local3=0D +=0D + Release (BMTX)=0D + Return (Arg3)=0D +}=0D +=0D +Device (BAT0)=0D +{=0D + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: H= ardware ID=0D + Name (_UID, 0) // _UID: Unique ID=0D + Name (_PCL, Package () { \_SB }) // _PCL: Power Consumer List=0D +=0D + Name (B0IP, Package (0x0D)=0D + {=0D + 1, /* 0x00: Power Unit: mAh */=0D + 0xFFFFFFFF, /* 0x01: Design Capacity */=0D + 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */=0D + 1, /* 0x03: Battery Technology: Rechargeable */=0D + 0xFFFFFFFF, /* 0x04: Design Voltage */=0D + 0, /* 0x05: Design Capacity of Warning */=0D + 0, /* 0x06: Design Capacity of Low */=0D + 1, /* 0x07: Capacity Granularity 1 */=0D + 1, /* 0x08: Capacity Granularity 2 */=0D + "", /* 0x09: Model Number */=0D + "100", /* 0x0a: Serial Number */=0D + "Lion", /* 0x0b: Battery Type */=0D + 0 /* 0x0c: OEM Information */=0D + })=0D + Name (B0SP, Package (0x04)=0D + {=0D + 0, /* 0x00: Battery State */=0D + 0xFFFFFFFF, /* 0x01: Battery Present Rate */=0D + 0xFFFFFFFF, /* 0x02: Battery Remaining Capacity */=0D + 0xFFFFFFFF /* 0x03: Battery Present Voltage */=0D + })=0D + Method (_STA, 0, NotSerialized) // _STA: Status=0D + {=0D + Local1 =3D EB0A=0D + If (Local1 & 0x40)=0D + {=0D + Local1 =3D 0=0D + }=0D +=0D + B0ST =3D Local1=0D + If (Local1)=0D + {=0D + Return (0x1F)=0D + }=0D + Else=0D + {=0D + Return (0x0F)=0D + }=0D + }=0D +=0D + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information=0D + {=0D + Local6 =3D B0ST=0D + Local7 =3D 20=0D + While (Local6 && Local7)=0D + {=0D + If (EB0R)=0D + {=0D + Local6 =3D 0=0D + }=0D + Else=0D + {=0D + Sleep (500)=0D + Local7--=0D + }=0D + }=0D +=0D + Return (GBIF (0, B0IP, Local6))=0D + }=0D +=0D + Method (_BST, 0, NotSerialized) // _BST: Battery Status=0D + {=0D + Local0 =3D (DerefOf (B0IP[0]) ^ 1)=0D + Local5 =3D EB0S=0D + Return (GBST (0, Local5, Local0, B0SP))=0D + }=0D +}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.= asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.asl new file mode 100644 index 000000000000..91e606c28e81 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.asl @@ -0,0 +1,424 @@ +/* SPDX-License-Identifier: BSD-2-Clause-Patent */=0D +=0D +/* Global TODO: TRPS, WMI, (externally: Optimus GC6 and GPS) */=0D +/* TODO: Capitalise on iGFX reference code (except, check BoardAcpiDxe fir= st) */=0D +=0D +External (\_SB.PCI0.GFX0.DD1F, DeviceObj) // FIXME: Would use "BRTN" meth= od, but=0D + // "DIDX" - "DeviceIdX" is unin= itialised=0D +External (\_SB.PCI0.GFX0.GHDS, MethodObj) // FIXME: Might need fixed VBT = - didn't port=0D + // display toggle tables previo= usly=0D +External (\_SB.PCI0.LPCB, DeviceObj)=0D +=0D +Device (\_SB.PCI0.LPCB.EC0)=0D +{=0D + Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HI= D: Hardware ID=0D + Name (_GPE, 0x50) // _GPE: General Purpose Events=0D + Name (\ECOK, 0)=0D +//Name (LGMR, 0x55AA55AA) // Will be patched at runtime=0D +=0D + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings=0D + {=0D + IO (Decode16, 0x62, 0x62, 0, 1)=0D + IO (Decode16, 0x66, 0x66, 0, 1)=0D + })=0D +=0D + OperationRegion (ECO1, SystemIO, 0x62, 1)=0D + Field (ECO1, ByteAcc, Lock, Preserve)=0D + {=0D + PX62, 8=0D + }=0D +=0D + OperationRegion (ECO2, SystemIO, 0x66, 1)=0D + Field (ECO2, ByteAcc, Lock, Preserve)=0D + {=0D + PX66, 8=0D + }=0D +=0D +//OperationRegion (ECMB, SystemMemory, LGMR, 0x200)=0D + OperationRegion (RAM, EmbeddedControl, 0, 0xFF)=0D + Field (RAM, ByteAcc, Lock, Preserve)=0D + {=0D + CMDB, 8, /* EC commands */=0D + ETID, 8, /* Thermal page selector */=0D + EBID, 8, /* Battery page selector */=0D + Offset (0x06),=0D + CMD2, 8, /* param 2: UNUSED */=0D + CMD1, 8, /* param 1: UNUSED */=0D + CMD0, 8, /* param 0 to EC command */=0D + Offset (0x0A),=0D + , 1,=0D + , 1,=0D + Offset (0x10),=0D + EQEN, 1, /* EQ enable */=0D + ETEE, 1, /* TODO */=0D + Offset (0x4E),=0D + ISEN, 1, /* TODO */=0D + Offset (0x4F),=0D + ECTP, 8, /* Touchpad ID */=0D + Offset (0x51),=0D + , 3,=0D + TPEN, 1, /* Touchpad enable */=0D + Offset (0x52),=0D + WLEX, 1, /* WLAN present */=0D + BTEX, 1, /* Bluetooth present */=0D + EX3G, 1, /* 3G */=0D + , 3,=0D + RFEX, 1, /* RF present */=0D +#if 0 // Merely a guess=0D + Offset (0x55),=0D + BTH0, 8, /* Battery threshold? TODO: Actually diff in modified = vendor FW */=0D +#endif=0D + Offset (0x57),=0D + , 7,=0D + AHKB, 1, /* Hotkey triggered */=0D + AHKE, 8, /* Hotkey data */=0D + Offset (0x5C),=0D + Offset (0x5D),=0D + Offset (0x6C),=0D + PWLT, 1, /* NVIDIA GPS: Panel? */=0D + , 3,=0D + GCON, 1, /* Enter Optimus GC6 */=0D + Offset (0x70),=0D + , 1,=0D + ELID, 1, /* Lid state */=0D + , 3,=0D + EACS, 1, /* AC state */=0D + Offset (0x71),=0D + WLEN, 1, /* WLAN enable */=0D + BTEN, 1, /* Bluetooth enable */=0D + , 3,=0D + ISS3, 1,=0D + ISS4, 1,=0D + ISS5, 1,=0D + , 4,=0D + EIDW, 1, /* Device wake */=0D + Offset (0x74),=0D + , 2,=0D + , 1,=0D + TPEX, 1, /* Touchpad present */=0D + Offset (0x75),=0D + BLST, 1, /* Bluetooth state */=0D + LMIB, 1, /* TODO */=0D + Offset (0x76),=0D + ECSS, 4, /* EC Notify of power state */=0D + EOSS, 4, /* EC Notify of power state */=0D + Offset (0x88), /* TODO: Aliased to "EB0S" */=0D + EB0A, 1,=0D + , 2,=0D + EB0R, 1,=0D + EB0L, 1,=0D + EB0F, 1,=0D + EB0N, 1,=0D + Offset (0x90),=0D + SCPM, 1, /* Set cooling policy */=0D + Offset (0x92), /* TODO: Aliased to "ETAF" */=0D + ESSF, 1,=0D + ECTT, 1,=0D + EDTT, 1,=0D + EOSD, 1, /* Trip */=0D + EVTP, 1,=0D + ECP1, 1,=0D + , 1,=0D + ECP2, 1,=0D + Offset (0xA8),=0D + ES0T, 8, /* Temperature */=0D + ES1T, 8, /* Temperature */=0D + Offset (0xD0),=0D + ESP0, 8, /* Passive temp */=0D + ESC0, 8, /* Critical temp */=0D + ESP1, 8, /* Passive temp */=0D + ESC1, 8, /* Critical temp */=0D + }=0D + /* Aliases several battery registers */=0D + Field (RAM, ByteAcc, Lock, Preserve)=0D + {=0D + Offset (0x88),=0D + EB0S, 8, /* Battery 0 state */=0D + }=0D + /* Aliases several thermal registers */=0D + Field (RAM, ByteAcc, Lock, Preserve)=0D + {=0D + Offset (0x92),=0D + ETAF, 8,=0D + }=0D +=0D +#if 0 // TODO: Hook up LGMR (instead of I/O accesses)=0D + Field (ECMB, ByteAcc, Lock, Preserve)=0D + {=0D + Offset (0x02),=0D + , 1,=0D + MLID, 1,=0D + , 3,=0D + MACS, 1,=0D + Offset (0x06),=0D + MBTP, 8,=0D + Offset (0x08),=0D + MB0S, 8,=0D + Offset (0x20),=0D + MS0T, 8,=0D + MS1T, 8,=0D + MS2T, 8,=0D + MS3T, 8,=0D + MS4T, 8,=0D + MS5T, 8,=0D + Offset (0x53),=0D + MCSS, 1,=0D + MCTT, 1,=0D + MDTT, 1,=0D + MOSD, 1,=0D + MVTP, 1,=0D + Offset (0x54),=0D + MSP0, 8,=0D + MSC0, 8,=0D + MCC0, 8,=0D + MSC1, 8,=0D + }=0D +#endif=0D +=0D + Method (_REG, 2, NotSerialized) // _REG: Region Availability=0D + {=0D + If (Arg0 =3D=3D 3)=0D + {=0D + ECOK =3D Arg1 // OS can clear region availability=0D + If (Arg1 =3D=3D 1) // On initialise=0D + {=0D + TINI ()=0D + EOSS =3D 0x05=0D +// OSIN ()=0D +=0D + /* Other pages return valid data too, but this seems to be the pag= e=0D + * we are expecting - persistently in ectool dump with vendor firm= ware=0D + * FIXME: Contents of other pages? */=0D + ETID =3D 0x20=0D + }=0D + }=0D + }=0D +=0D + Method (TINI, 0, NotSerialized)=0D + {=0D + If (ECOK)=0D + {=0D + ETAF =3D 0=0D + ETEE =3D 1=0D + }=0D + Else=0D + {=0D + /* WBEC: Called SMI function 0x11 */=0D +// EC_WRITE (0x92, 0) // ETAF =3D 0=0D + /* MBEC: Called SMI function 0x12 */=0D +// MBEC (0x10, 0xFD, 0x02) // ETEE =3D 1=0D + }=0D + }=0D +=0D + Name (RFST, 0) /* RF state */=0D + Method (ECPS, 1, NotSerialized) // _PTS: Prepare To Sleep=0D + {=0D + ECSS =3D Arg0=0D +// COSI =3D OSYS=0D +// SPR1 =3D Arg0=0D + /* TRPS: Generic SMI trap handler */=0D +// TRPS (0x82, 0x02)=0D + If ((Arg0 =3D=3D 3) || (Arg0 =3D=3D 4))=0D + {=0D + RFST =3D RFEX=0D + }=0D + }=0D +=0D + Method (ECWK, 1, NotSerialized) // _WAK: Wake=0D + {=0D + EQEN =3D 1=0D + EOSS =3D Arg0=0D + TINI ()=0D + Notify (BAT0, 0x81) // Information Change=0D +// COSI =3D OSYS=0D +// SPR1 =3D Arg0=0D + /* TRPS: Generic SMI trap handler */=0D +// TRPS (0x82, 0x03)=0D + If ((Arg0 =3D=3D 3) || (Arg0 =3D=3D 4))=0D + {=0D + RFEX =3D RFST=0D + Notify (SLPB, 0x02) // Device Wake=0D + }=0D + }=0D +=0D +#if 0 // TODO: Figure out what this is for=0D + Method (OSIN, 0, NotSerialized)=0D + {=0D + COSI =3D OSYS=0D + /* TRPS: Generic SMI trap handler */=0D + TRPS (0x82, 1)=0D + }=0D +#endif=0D +=0D +#if 0 // TODO: Implement=0D + Method (MBEC, 3, Serialized) // Read-Modify-Write=0D + {=0D + /* Based on similar methods/tables at=0D + * https://github.com/linuxhw/ACPI/blob/master/Notebook/Sony/SVE1713/S= VE1713S1RW/506CDC50E671#L9359=0D + * which use ASL instead of SMM calls */=0D + Local0 =3D EC_READ (Arg0)=0D + Local0 &=3D Arg1=0D + Local0 |=3D Arg2=0D + EC_WRITE (Arg0, Local0)=0D + }=0D +#endif=0D +=0D + /* Graphical hotkey */=0D + Method (_Q19, 0, NotSerialized)=0D + {=0D + ^^^GFX0.GHDS (0x03)=0D + }=0D +=0D + /* Increase brightness */=0D + Method (_Q1C, 0, NotSerialized)=0D + {=0D + Notify (^^^GFX0.DD1F, 0x86)=0D + }=0D +=0D + /* Decrease brightness */=0D + Method (_Q1D, 0, NotSerialized)=0D + {=0D + Notify (^^^GFX0.DD1F, 0x87)=0D + }=0D +=0D + /* Hotkeys */=0D + Method (_Q2C, 0, NotSerialized)=0D + {=0D + If (LMIB)=0D + {=0D + If (!AHKB) /* Else, WMI clears its buffer? */=0D + {=0D + Local1 =3D AHKE=0D + If ((Local1 > 0) && (Local1 < 0x80))=0D + {=0D + \DBGH ("Hotkeys - TODO: Airplane mode?")=0D + /* WMI -> "GCMS" method */=0D + }=0D + ElseIf ((Local1 > 0x80) && (Local1 < 0xA0))=0D + {=0D + TPEN ^=3D 1 /* TODO: Not working. What else does WMI do here? *= /=0D + }=0D + }=0D + }=0D + }=0D +=0D + Method (_Q36, 0, NotSerialized)=0D + {=0D + If (ECOK)=0D + {=0D + EOSD =3D 1 // Thermal trip=0D + }=0D + Else=0D + {=0D + /* MBEC: Called SMI function 0x12 */=0D +// MBEC (0x92, 0xF7, 0x08) // EOSD =3D 1=0D + }=0D +=0D + Sleep (500)=0D + Notify (\_TZ.TZ01, 0x80) // Thermal Status Change=0D + Notify (\_TZ.TZ00, 0x80) // Thermal Status Change=0D + }=0D +=0D + Method (_Q3F, 0, NotSerialized)=0D + {=0D + \DBGH ("EC Query: 0x3F - TRPS")=0D + /* TRPS: Generic SMI trap handler */=0D +// TRPS (0x80, 0)=0D + }=0D +=0D + Method (_Q40, 0, NotSerialized)=0D + {=0D + Notify (BAT0, 0x81) // Information Change=0D + }=0D +=0D + Method (_Q41, 0, NotSerialized)=0D + {=0D + Notify (BAT0, 0x81) // Information Change=0D + }=0D +=0D + /* Battery status change */=0D + Method (_Q48, 0, NotSerialized)=0D + {=0D + Notify (BAT0, 0x80)=0D + }=0D +=0D + /* Battery critical? */=0D + Method (_Q4C, 0, NotSerialized)=0D + {=0D + If (B0ST)=0D + {=0D + Notify (BAT0, 0x80) // Status Change=0D + }=0D + }=0D +=0D + /* AC status change: present */=0D + Method (_Q50, 0, NotSerialized)=0D + {=0D + Notify (ADP1, 0x80)=0D + }=0D +=0D + /* AC status change: not present */=0D + Method (_Q51, 0, NotSerialized)=0D + {=0D + Notify (ADP1, 0x80)=0D + }=0D +=0D + /* Lid status change: open */=0D + Method (_Q52, 0, NotSerialized)=0D + {=0D + Notify (LID0, 0x80)=0D + }=0D +=0D + /* Lid status change: close */=0D + Method (_Q53, 0, NotSerialized)=0D + {=0D + Notify (LID0, 0x80)=0D + }=0D +=0D + Method (_Q60, 0, NotSerialized)=0D + {=0D + \DBGH ("EC Query: 0x60 -> WMI")=0D + }=0D +=0D + Method (_Q61, 0, NotSerialized)=0D + {=0D + \DBGH ("EC Query: 0x61 -> WMI")=0D + }=0D +=0D + Method (_Q62, 0, NotSerialized)=0D + {=0D + \DBGH ("EC Query: 0x62 -> Optimus GC6")=0D + }=0D +=0D + Method (_Q63, 0, NotSerialized)=0D + {=0D + \DBGH ("EC Query: 0x63 -> Optimus GC6")=0D + }=0D +=0D + Method (_Q67, 0, NotSerialized)=0D + {=0D + \DBGH ("EC Query: 0x67 -> NVIDIA GPS")=0D + }=0D +=0D + Method (_Q68, 0, NotSerialized)=0D + {=0D + \DBGH ("EC Query: 0x68 -> NVIDIA GPS")=0D + }=0D +=0D + Method (_Q6C, 0, NotSerialized)=0D + {=0D + \DBGH ("EC Query: 0x6C - TRPS")=0D + /* TRPS: Generic SMI trap handler */=0D +// TRPS (0x81, 0)=0D + }=0D +=0D + Method (_Q6D, 0, NotSerialized)=0D + {=0D + \DBGH ("EC Query: 0x6D - TRPS")=0D + /* TRPS: Generic SMI trap handler */=0D +// TRPS (0x81, 1)=0D + }=0D +=0D + #include "ac.asl"=0D + #include "battery.asl"=0D +}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mai= nboard.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mai= nboard.asl new file mode 100644 index 000000000000..3e156f3da8ee --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mainboard.= asl @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: BSD-2-Clause-Patent */=0D +=0D +External (\_SB.SLPB, DeviceObj)=0D +=0D +#include "thermal.asl"=0D +=0D +// TODO: Need hooks from BoardAcpiDxe=0D +=0D +Scope (_SB)=0D +{=0D + Method (MPTS, 1, NotSerialized) // _PTS: Prepare To Sleep=0D + {=0D + ^PCI0.LPCB.EC0.ECPS (Arg0)=0D + }=0D +=0D + Method (MWAK, 1, Serialized) // _WAK: Wake=0D + {=0D + ^PCI0.LPCB.EC0.ECWK (Arg0)=0D +=0D + If ((Arg0 =3D=3D 3) || (Arg0 =3D=3D 4))=0D + {=0D + Notify (LID0, 0x80) // Status Change=0D + }=0D + }=0D +=0D + Method (MS0X, 1, Serialized) // S0ix hook. Porting "GUAM" method - "Glo= bal User Absent Mode"=0D + {=0D + If (Arg0 =3D=3D 0)=0D + {=0D + /* Exit "Connected Standby" */=0D +#if 1 // EC Notification=0D + ^PCI0.LPCB.EC0.EOSS =3D 0=0D +#endif=0D + /* TODO: P-state capping, PL setting? */=0D + }=0D + ElseIf (Arg0 =3D=3D 1)=0D + {=0D + /* Enter "Connected Standby" */=0D +#if 1 // EC Notification=0D + ^PCI0.LPCB.EC0.ECSS =3D 0x08=0D +#endif=0D + /* TODO: P-state capping, PL setting? */=0D + }=0D + }=0D +=0D + Device (LID0)=0D + {=0D + Name (_HID, EisaId ("PNP0C0D") /* Lid Device */) // _HID: Hardware ID= =0D + Method (_LID, 0, NotSerialized) // _LID: Lid Status=0D + {=0D + Return (^^PCI0.LPCB.EC0.ELID)=0D + }=0D +=0D + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake=0D + {=0D + ^^PCI0.LPCB.EC0.EIDW =3D Arg0=0D + }=0D +=0D + Name (_PRW, Package () { 0x0A, 3 }) // _PRW: Power Resources for Wake= =0D + }=0D +=0D + // Add a GPE to device=0D + Scope (SLPB)=0D + {=0D + Name (_PRW, Package () { 0x0A, 3 }) // _PRW: Power Resources for Wake= =0D + }=0D +}=0D +=0D +Scope (_GPE)=0D +{=0D + /* TODO - Remaining Level-Triggered GPEs: PCH GPE, PCIe PME, TBT, DTS, G= FX SCI and tier-2 (RTD3) */=0D + Method (_L0A, 0, NotSerialized)=0D + {=0D + Notify (\_SB.SLPB, 0x02) // Device Wake=0D + }=0D +}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/the= rmal.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/therm= al.asl new file mode 100644 index 000000000000..ab4b3acf3573 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/thermal.asl @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: BSD-2-Clause-Patent */=0D +=0D +Scope (_TZ)=0D +{=0D + Name (CRT0, 0)=0D + Name (PSV0, 0)=0D + ThermalZone (TZ01)=0D + {=0D + Method (_TMP, 0, Serialized) // _TMP: Temperature=0D + {=0D + Local0 =3D \_SB.PCI0.LPCB.EC0.ES0T=0D +// Local1 =3D \_SB.PCI0.LPCB.EC0.ESSF // "MCSS": By bit offset, likely= "ESSF"=0D + // in thermals, not "ECSS" in noti= fy=0D + Local2 =3D \_SB.PCI0.LPCB.EC0.EOSD=0D + If (Local2) // Thermal trip=0D + {=0D + If (Local0 <=3D CRT0)=0D + {=0D + Local0 =3D (CRT0 + 2)=0D + }=0D + }=0D +=0D + Return (C2K (Local0))=0D + }=0D +=0D + Method (_CRT, 0, Serialized) // _CRT: Critical Temperature=0D + {=0D + Local0 =3D \_SB.PCI0.LPCB.EC0.ESC0=0D + If ((Local0 >=3D 128) || (Local0 < 30))=0D + {=0D + Local0 =3D 120=0D + }=0D +=0D + CRT0 =3D Local0=0D + Return (C2K (Local0))=0D + }=0D +=0D + Method (_SCP, 1, Serialized) // _SCP: Set Cooling Policy=0D + {=0D + If (ECOK)=0D + {=0D + \_SB.PCI0.LPCB.EC0.SCPM =3D Arg0=0D + }=0D + Else=0D + {=0D + /* MBEC: Called SMI function 0x12 */=0D +// \_SB.PCI0.LPCB.EC0.MBEC (0x90, 0xFE, Arg0) // SCPM =3D Arg0=0D + }=0D + }=0D +=0D + Method (_PSV, 0, Serialized) // _PSV: Passive Temperature=0D + {=0D + Local0 =3D \_SB.PCI0.LPCB.EC0.ESP0=0D + If ((Local0 >=3D 128) || (Local0 < 30))=0D + {=0D + Local0 =3D 30=0D + }=0D +=0D + PSV0 =3D Local0=0D + Return (C2K (Local0))=0D + }=0D + }=0D +=0D + ThermalZone (TZ00)=0D + {=0D + Method (_TMP, 0, Serialized) // _TMP: Temperature=0D + {=0D + Local0 =3D \_SB.PCI0.LPCB.EC0.ES1T=0D + Return (C2K (Local0))=0D + }=0D +=0D + Method (_CRT, 0, Serialized) // _CRT: Critical Temperature=0D + {=0D + Local0 =3D \_SB.PCI0.LPCB.EC0.ESC1=0D + If ((Local0 >=3D 128) || (Local0 < 30))=0D + {=0D + Local0 =3D 120=0D + }=0D +=0D + Return (C2K (Local0))=0D + }=0D + }=0D +=0D + Method (C2K, 1, NotSerialized)=0D + {=0D + Local0 =3D Arg0=0D + If ((Local0 >=3D 127) || (Local0 <=3D 16))=0D + {=0D + Local0 =3D 30=0D + }=0D +=0D + Local0 =3D ((Local0 * 10) + 2732) // Celsius to Kelvin=0D + Return (Local0)=0D + }=0D +}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c b/Platform/Intel/= KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyU= pdateLibFsp/PcieDeviceTable.c index 155dfdaf623f..7fc972b41f87 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c @@ -7,25 +7,14 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/=0D =0D #include "PeiPchPolicyUpdate.h"=0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D #include =0D -#include =0D -#include =0D -#include =0D -#include =0D =0D #define PCI_CLASS_NETWORK 0x02=0D #define PCI_CLASS_NETWORK_ETHERNET 0x00=0D #define PCI_CLASS_NETWORK_OTHER 0x80=0D =0D +/* BUGBUG: Tested, table entries cannot configure PCI config space - FspsU= pd.h: "only used in PostMem phase" */=0D +=0D GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = =3D {=0D //=0D // Intel PRO/Wireless=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c b/Platform/I= ntel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPo= licyUpdateLibFsp/PeiBoardPolicyUpdate.c new file mode 100644 index 000000000000..814c3e4e2b4b --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c @@ -0,0 +1,283 @@ +/** @file=0D + This file configures Aspire VN7-572G board-specific FSP UPDs.=0D +=0D +Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "PeiPchPolicyUpdate.h"=0D +#include =0D +#include =0D +#include =0D +=0D +/* TODO:=0D + * - Some disabled devices are likely fuse-disabled. Remove such entries=0D + * - These overrides duplicate some Config Blocks. Remove when refactoring= =0D + * - Consume ConfigBlockLib and update those? It could be factored into = BoardInitLib=0D + * for deduplication=0D + * - Copy initialised array, where sane=0D + * - Set IgdDvmt50PreAlloc? */=0D +=0D +#define SA_VR 0=0D +#define IA_VR 1=0D +#define GT_UNSLICED_VR 2=0D +#define GT_SLICED_VR 3=0D +=0D +/**=0D + Performs the remainder of board-specific FSP Policy initialization.=0D +=0D + @param[in][out] FspmUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspBoardPolicyUpdatePreMem (=0D + IN OUT FSPM_UPD *FspmUpd=0D + )=0D +{=0D + // BUGBUG: Preserve FSP defaults - PeiSiliconPolicyInitLibFsp ultimately= overrides to 0.=0D + FspmUpd->FspmConfig.PchHpetBusNumber =3D 0xF0;=0D + FspmUpd->FspmConfig.PchHpetDeviceNumber =3D 0x1F;=0D +// FspmUpd->FspmConfig.PchHpetFunctionNumber =3D 0;=0D + FspmUpd->FspmConfig.PeciC10Reset =3D 1;=0D + FspmUpd->FspmConfig.RefClk =3D 1; // Maybe "auto" is safe, but that isn= 't the FSP default=0D +=0D + // TODO: Why should this be here?=0D + FspmUpd->FspmConfig.TsegSize =3D PcdGet32(PcdTsegSize);=0D + // TODO: Is IED nochoice and nocare?=0D + // FSP should program it's default BDF value=0D + FspmUpd->FspmConfig.PchHpetBdfValid =3D 1;=0D +=0D + /* System Agent config */=0D + FspmUpd->FspmConfig.UserBd =3D PcdGet8(PcdSaMiscUserBd);=0D + FspmUpd->FspmConfig.DqPinsInterleaved =3D (UINT8)PcdGetBool(PcdMrcDqPins= Interleaved);=0D + FspmUpd->FspmConfig.CaVrefConfig =3D PcdGet8(PcdMrcCaVrefConfig);=0D + FspmUpd->FspmConfig.SaGv =3D 3; // Enabled=0D +=0D + /* iGFX config */=0D + FspmUpd->FspmConfig.PrimaryDisplay =3D 4; // Switchable Graphics=0D +=0D + /* PCIe config */=0D + FspmUpd->FspmConfig.PcieRpEnableMask =3D 0x341; // Ports 1, 7, 9 and 10= =0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Performs the remainder of board-specific FSP Policy initialization.=0D +=0D + @param[in][out] FspsUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspBoardPolicyUpdate (=0D + IN OUT FSPS_UPD *FspsUpd=0D + )=0D +{=0D + // - Board has no GPIO expander on I2C4 (despite SetupUtility claim that= it does=0D + // (this appears to be static text?)=0D + // - Is UART0 merely supporting the UART2 devfn (but PcieRpFunctionSwap = =3D=3D 1)?=0D + UINT8 NewSerialIoDevMode[] =3D {0x02, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00= , 0x00, 0x00, 0x00, 0x04};=0D +=0D + // FIXME/NB: This is insecure and not production-ready!=0D + // TODO: Configure SPI lockdown by variable on FrontPage?=0D + // Later, also configure stronger protection: PRRs=0D + FspsUpd->FspsConfig.PchLockDownBiosLock =3D 0;=0D + FspsUpd->FspsConfig.PchLockDownSpiEiss =3D 0;=0D + // This may be PWRM+0x18[BIT22], causing HSTI "PCH Security Configuratio= n - Reserved Check failure"=0D + // I think the intel_pmc_core kernel module requires this to populate de= bugfs?=0D + FspsUpd->FspsTestConfig.PchPmPmcReadDisable =3D 0;=0D +=0D + // BUGBUG: Preserve FSP defaults - Pei*PolicyLib ultimately overrides=0D + FspsUpd->FspsConfig.PchIoApicBusNumber =3D 0xF0;=0D + FspsUpd->FspsConfig.PchIoApicDeviceNumber =3D 0x1F;=0D +// FspsUpd->FspsConfig.PchIoApicFunctionNumber =3D 0;=0D + // Apparently deprecated and configured by FSP-M?=0D + FspsUpd->FspsConfig.CpuConfig.Bits.VmxEnable =3D 1;=0D + // Requires HW support?=0D + FspsUpd->FspsConfig.PchPmSlpS0VmEnable =3D 0;=0D + CopyMem (&FspsUpd->FspsConfig.SerialIoDevMode, &NewSerialIoDevMode, size= of(FspsUpd->FspsConfig.SerialIoDevMode));=0D + FspsUpd->FspsConfig.SerialIoEnableDebugUartAfterPost =3D 1;=0D + FspsUpd->FspsTestConfig.TStates =3D 1;=0D + FspsUpd->FspsTestConfig.ProcHotResponse =3D 1;=0D + FspsUpd->FspsTestConfig.AutoThermalReporting =3D 0;=0D +=0D + // TODO: Why should this be here?=0D + // FSP should program it's default BDF value=0D + FspsUpd->FspsConfig.PchIoApicBdfValid =3D 1;=0D +=0D + // Acer IDs (TODO: "Newgate" IDs)=0D + FspsUpd->FspsConfig.DefaultSvid =3D 0x1025;=0D + FspsUpd->FspsConfig.DefaultSid =3D 0x1037;=0D + FspsUpd->FspsConfig.PchSubSystemVendorId =3D 0x1025;=0D + FspsUpd->FspsConfig.PchSubSystemId =3D 0x1037;=0D +=0D + /* System Agent config */=0D + // Set the Thermal Control Circuit (TCC) activation value to 97C=0D + // even though FSP integration guide says to set it to 100C for SKL-U=0D + // (offset at 0), because when the TCC activates at 100C, the CPU=0D + // will have already shut itself down from overheating protection.=0D + FspsUpd->FspsTestConfig.TccActivationOffset =3D 3;=0D +=0D + // VR Slew rate setting for improving audible noise=0D + FspsUpd->FspsConfig.AcousticNoiseMitigation =3D 1;=0D + FspsUpd->FspsConfig.SlowSlewRateForIa =3D 3; // Fast/16=0D + FspsUpd->FspsConfig.SlowSlewRateForGt =3D 3; // Fast/16=0D + FspsUpd->FspsConfig.SlowSlewRateForSa =3D 0; // Fast/2=0D + FspsUpd->FspsConfig.FastPkgCRampDisableIa =3D 0;=0D + FspsUpd->FspsConfig.FastPkgCRampDisableGt =3D 0;=0D + FspsUpd->FspsConfig.FastPkgCRampDisableSa =3D 0;=0D +=0D + // VR domain configuration (copied from board port, before VR config mov= ed=0D + // to SoC. Should match SKL-U (GT2, 15W) in the SKL-U datasheet, vol. 1= =0D + FspsUpd->FspsConfig.AcLoadline[SA_VR] =3D 1030; // 10.3mOhm (in 1/100 i= ncrements)=0D + FspsUpd->FspsConfig.DcLoadline[SA_VR] =3D 1030; // 10.3mOhm (in 1/100 i= ncrements)=0D + FspsUpd->FspsConfig.Psi1Threshold[SA_VR] =3D 80; // 20A (in 1/4 incremen= ts)=0D + FspsUpd->FspsConfig.Psi2Threshold[SA_VR] =3D 16; // 4A (in 1/4 increment= s)=0D + FspsUpd->FspsConfig.Psi3Threshold[SA_VR] =3D 4; // 1A (in 1/4 increment= s)=0D + FspsUpd->FspsConfig.IccMax[SA_VR] =3D 18; // 4.5A (in 1/4 increme= nts)=0D + FspsUpd->FspsConfig.VrVoltageLimit[SA_VR] =3D 1520; // 1520mV=0D +=0D + FspsUpd->FspsConfig.AcLoadline[IA_VR] =3D 240; // 2.4mOhm (in 1/100 inc= rements)=0D + FspsUpd->FspsConfig.DcLoadline[IA_VR] =3D 240; // 2.4mOhm (in 1/100 inc= rements)=0D + FspsUpd->FspsConfig.Psi1Threshold[IA_VR] =3D 80; // 20A (in 1/4 incremen= ts)=0D + FspsUpd->FspsConfig.Psi2Threshold[IA_VR] =3D 20; // 5A (in 1/4 increment= s)=0D + FspsUpd->FspsConfig.Psi3Threshold[IA_VR] =3D 4; // 1A (in 1/4 increment= s)=0D + FspsUpd->FspsConfig.IccMax[IA_VR] =3D 116; // 29A (in 1/4 incremen= ts)=0D + FspsUpd->FspsConfig.VrVoltageLimit[IA_VR] =3D 1520; // 1520mV=0D +=0D + FspsUpd->FspsConfig.AcLoadline[GT_UNSLICED_VR] =3D 310; // 3.1mOhm (in = 1/100 increments)=0D + FspsUpd->FspsConfig.DcLoadline[GT_UNSLICED_VR] =3D 310; // 3.1mOhm (in = 1/100 increments)=0D + FspsUpd->FspsConfig.Psi1Threshold[GT_UNSLICED_VR] =3D 80; // 20A (in 1/4= increments)=0D + FspsUpd->FspsConfig.Psi2Threshold[GT_UNSLICED_VR] =3D 20; // 5A (in 1/4 = increments)=0D + FspsUpd->FspsConfig.Psi3Threshold[GT_UNSLICED_VR] =3D 4; // 1A (in 1/4 = increments)=0D + FspsUpd->FspsConfig.IccMax[GT_UNSLICED_VR] =3D 124; // 31A (in 1/4= increments)=0D + FspsUpd->FspsConfig.VrVoltageLimit[GT_UNSLICED_VR] =3D 1520; // 1520mV= =0D +=0D + FspsUpd->FspsConfig.AcLoadline[GT_SLICED_VR] =3D 310; // 3.1mOhm (in 1/= 100 increments)=0D + FspsUpd->FspsConfig.DcLoadline[GT_SLICED_VR] =3D 310; // 3.1mOhm (in 1/= 100 increments)=0D + FspsUpd->FspsConfig.Psi1Threshold[GT_SLICED_VR] =3D 80; // 20A (in 1/4 i= ncrements)=0D + FspsUpd->FspsConfig.Psi2Threshold[GT_SLICED_VR] =3D 20; // 5A (in 1/4 in= crements)=0D + FspsUpd->FspsConfig.Psi3Threshold[GT_SLICED_VR] =3D 4; // 1A (in 1/4 in= crements)=0D + FspsUpd->FspsConfig.IccMax[GT_SLICED_VR] =3D 124; // 31A (in 1/4 i= ncrements)=0D + FspsUpd->FspsConfig.VrVoltageLimit[GT_SLICED_VR] =3D 1520; // 1520mV=0D +=0D + // PL1, PL2 override 35W, PL4 override 43W (converted to processor units= , then 125 mW increments)=0D + // BUGBUG: PL1 and PL2 not reflected in MSR 0x610?=0D + FspsUpd->FspsTestConfig.PowerLimit1 =3D 35000;=0D + FspsUpd->FspsTestConfig.PowerLimit2Power =3D 35000;=0D + FspsUpd->FspsTestConfig.PowerLimit4 =3D 43000;=0D +=0D + // ISL95857 VR=0D + // Send VR specific command for PS4 exit issue=0D + FspsUpd->FspsConfig.SendVrMbxCmd1 =3D 2;=0D + // Send VR mailbox command for IA/GT/SA rails=0D + FspsUpd->FspsConfig.IslVrCmd =3D 2;=0D +=0D + /* Skycam config */=0D + FspsUpd->FspsConfig.SaImguEnable =3D 0;=0D + FspsUpd->FspsConfig.PchCio2Enable =3D 0;=0D +=0D + /* Sensor hub config */=0D + FspsUpd->FspsConfig.PchIshEnable =3D 0;=0D +=0D + /* xHCI config */=0D + FspsUpd->FspsConfig.SsicPortEnable =3D 0;=0D + // Configure USB2 ports in two blocks=0D + for (int i =3D 0; i < 3; i++) {=0D + FspsUpd->FspsConfig.Usb2AfeTxiset[i] =3D 0x2; // 16.9mV=0D + FspsUpd->FspsConfig.Usb2AfePredeemp[i] =3D 1; // De-emphasis on=0D + FspsUpd->FspsConfig.Usb2AfePetxiset[i] =3D 0x3;// 28.15mV=0D + FspsUpd->FspsConfig.Usb2AfePehalfbit[i] =3D 1; // Half-bit=0D + }=0D + for (int i =3D 3; i < 9; i++) {=0D + FspsUpd->FspsConfig.Usb2AfeTxiset[i] =3D 0; // 0mV=0D + FspsUpd->FspsConfig.Usb2AfePredeemp[i] =3D 0x2;// Pre-emphasis and de-= emphasis on=0D + FspsUpd->FspsConfig.Usb2AfePetxiset[i] =3D 0x7;// 56.3mV=0D + FspsUpd->FspsConfig.Usb2AfePehalfbit[i] =3D 1; // Half-bit=0D + }=0D + // Configure all USB3 ports=0D + for (int i =3D 0; i < 4; i++) {=0D + FspsUpd->FspsConfig.Usb3HsioTxDeEmphEnable[i] =3D 1;=0D + FspsUpd->FspsConfig.Usb3HsioTxDeEmph[i] =3D 0x29; // Default (approxi= mately -3.5dB de-emphasis)=0D + }=0D + // Disable all OC pins=0D + for (int i =3D 0; i < 9; i++) {=0D + FspsUpd->FspsConfig.Usb2OverCurrentPin[i] =3D PchUsbOverCurrentPinSkip= ;=0D + }=0D + for (int i =3D 0; i < 4; i++) {=0D + FspsUpd->FspsConfig.Usb3OverCurrentPin[i] =3D PchUsbOverCurrentPinSkip= ;=0D + }=0D + // Disable supported, but not present, ports=0D + for (int i =3D 9; i < 12; i++) {=0D + FspsUpd->FspsConfig.PortUsb20Enable[i] =3D 0;=0D + }=0D + for (int i =3D 4; i < 6; i++) {=0D + FspsUpd->FspsConfig.PortUsb30Enable[i] =3D 0;=0D + }=0D +=0D + /* xDCI config */=0D + FspsUpd->FspsConfig.XdciEnable =3D 0;=0D +=0D + /* SATA config */=0D + // This is a hard silicon requirement, discovered several times by coreb= oot boards=0D + FspsUpd->FspsConfig.SataPwrOptEnable =3D 1;=0D + // Disable supported, but not present, ports=0D + FspsUpd->FspsConfig.SataPortsEnable[0] =3D 0;=0D +=0D + /* PCIe config */=0D + // Port 1 (dGPU; x4)=0D + FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[0] =3D 1;=0D + FspsUpd->FspsConfig.PcieRpLtrEnable[0] =3D 1;=0D + FspsUpd->FspsConfig.PcieRpClkReqSupport[0] =3D 1;=0D + FspsUpd->FspsConfig.PcieRpClkReqNumber[0] =3D 0;=0D + FspsUpd->FspsConfig.PcieRpMaxPayload[0] =3D PchPcieMaxPayload256;=0D + FspsUpd->FspsConfig.PcieRpClkSrcNumber[0] =3D 0x1F; // CLKSRC pin inval= id=0D + // Port 7 (NGFF; x2)=0D + FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[6] =3D 1;=0D + FspsUpd->FspsConfig.PcieRpLtrEnable[6] =3D 1;=0D + FspsUpd->FspsConfig.PcieRpClkReqSupport[6] =3D 1;=0D + FspsUpd->FspsConfig.PcieRpClkReqNumber[6] =3D 3;=0D + FspsUpd->FspsConfig.PcieRpMaxPayload[6] =3D PchPcieMaxPayload256;=0D + FspsUpd->FspsConfig.PcieRpClkSrcNumber[6] =3D 0x1F; // CLKSRC pin inval= id=0D + // Port 9 (LAN)=0D + FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[8] =3D 1;=0D + FspsUpd->FspsConfig.PcieRpLtrEnable[8] =3D 1;=0D + FspsUpd->FspsConfig.PcieRpClkReqSupport[8] =3D 1;=0D + FspsUpd->FspsConfig.PcieRpClkReqNumber[8] =3D 1;=0D + FspsUpd->FspsConfig.PcieRpMaxPayload[8] =3D PchPcieMaxPayload256;=0D + FspsUpd->FspsConfig.PcieRpClkSrcNumber[8] =3D 0x1F; // CLKSRC pin inval= id=0D + // Port 10 (WLAN)=0D + FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[9] =3D 1;=0D + FspsUpd->FspsConfig.PcieRpLtrEnable[9] =3D 1;=0D + FspsUpd->FspsConfig.PcieRpClkReqSupport[9] =3D 1;=0D + FspsUpd->FspsConfig.PcieRpClkReqNumber[9] =3D 2;=0D + FspsUpd->FspsConfig.PcieRpMaxPayload[9] =3D PchPcieMaxPayload256;=0D + FspsUpd->FspsConfig.PcieRpClkSrcNumber[9] =3D 0x1F; // CLKSRC pin inval= id=0D + // ASPM L0s is broken/unsupported on Qualcomm Atheros QCA6174 (AER: corr= ected errors)=0D + // BUGBUG: PcieDeviceTable.c entries aren't setting PCI config space=0D + FspsUpd->FspsConfig.PcieRpAspm[9] =3D PchPcieAspmL1;=0D +=0D + /* LPC config */=0D + // EC/KBC requires continuous mode=0D + FspsUpd->FspsConfig.PchPmLpcClockRun =3D 1;=0D + FspsUpd->FspsConfig.PchSirqMode =3D PchContinuousMode;=0D +=0D + /* SCS config */=0D + // Although platform NVS area shows this enabled, the SD card reader is = connected over USB, not SCS=0D + FspsUpd->FspsConfig.ScsEmmcEnabled =3D 0;=0D + FspsUpd->FspsConfig.ScsSdCardEnabled =3D 0;=0D +=0D + /* GbE config */=0D + FspsUpd->FspsConfig.PchLanEnable =3D 0;=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform= /Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSilicon= PolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c index d8aff1960f0b..c9cf8da1de9c 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c @@ -9,17 +9,13 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =0D =0D #include =0D +#include =0D #include =0D -#include =0D =0D #include =0D #include =0D #include =0D =0D -#include =0D -#include =0D -#include =0D -#include =0D #include =0D #include =0D =0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c b/Platform/= Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiFspPolicyUpdateLib.c index 55be16265e99..d808f5d2359f 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c @@ -7,10 +7,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/=0D =0D #include =0D -#include =0D #include =0D -#include =0D -#include =0D #include =0D #include =0D =0D @@ -91,6 +88,36 @@ PeiFspSaPolicyUpdate ( IN OUT FSPS_UPD *FspsUpd=0D );=0D =0D +/**=0D + Performs the remainder of board-specific FSP Policy initialization.=0D +=0D + @param[in][out] FspmUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspBoardPolicyUpdatePreMem (=0D + IN OUT FSPM_UPD *FspmUpd=0D + );=0D +=0D +/**=0D + Performs the remainder of board-specific FSP Policy initialization.=0D +=0D + @param[in][out] FspsUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspBoardPolicyUpdate (=0D + IN OUT FSPS_UPD *FspsUpd=0D + );=0D +=0D VOID=0D InternalPrintVariableData (=0D IN UINT8 *Data8,=0D @@ -140,6 +167,7 @@ SiliconPolicyUpdatePreMem ( PeiFspSaPolicyUpdatePreMem (FspmUpdDataPtr);=0D PeiFspPchPolicyUpdatePreMem (FspmUpdDataPtr);=0D PeiFspMiscUpdUpdatePreMem (FspmUpdDataPtr);=0D + PeiFspBoardPolicyUpdatePreMem (FspmUpdDataPtr);=0D =0D InternalPrintVariableData ((VOID *)FspmUpdDataPtr, sizeof(FSPM_UPD));=0D =0D @@ -177,6 +205,7 @@ SiliconPolicyUpdatePostMem ( FspsUpdDataPtr =3D FspsUpd;=0D PeiFspSaPolicyUpdate (FspsUpdDataPtr);=0D PeiFspPchPolicyUpdate (FspsUpdDataPtr);=0D + PeiFspBoardPolicyUpdate (FspsUpdDataPtr);=0D =0D InternalPrintVariableData ((VOID *)FspsUpdDataPtr, sizeof(FSPS_UPD));=0D =0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c b/Platform/Int= el/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPoli= cyUpdateLibFsp/PeiPchPolicyUpdate.c index b469720ac657..cd4822052e3a 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c @@ -9,18 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PeiPchPolicyUpdate.h"=0D #include =0D #include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D #include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D =0D extern PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[];=0D =0D @@ -103,6 +92,7 @@ InternalAddPlatformVerbTables ( InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (= UINTN) PcdGet32 (PcdHdaVerbTable));=0D InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (= UINTN) PcdGet32 (PcdHdaVerbTable2));=0D InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL);=0D + DEBUG ((DEBUG_INFO, "HDA: No external codecs to install!\n"));=0D }=0D } else {=0D DEBUG ((DEBUG_INFO, "HDA Policy: External codec kit selected\n"));=0D @@ -133,10 +123,6 @@ PeiFspPchPolicyUpdate ( IN OUT FSPS_UPD *FspsUpd=0D )=0D {=0D -=0D - FspsUpd->FspsConfig.PchSubSystemVendorId =3D V_PCH_INTEL_VENDOR_ID;=0D - FspsUpd->FspsConfig.PchSubSystemId =3D V_PCH_DEFAULT_SID;=0D -=0D FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr =3D (UINT32) mPcieDevi= ceTable;=0D =0D InternalAddPlatformVerbTables (FspsUpd, PchHdaCodecPlatformOnboard, PcdG= et8 (PcdAudioConnector));=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h b/Platform/Int= el/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPoli= cyUpdateLibFsp/PeiPchPolicyUpdate.h index 30d2f99e1dde..5e720b0041e8 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h @@ -16,9 +16,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =0D #include =0D #include =0D -#include =0D -#include =0D #include =0D +#include =0D =0D #include =0D #include =0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c b/Platfo= rm/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSilic= onPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c index f6390ee12c17..50f872048ad7 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c @@ -8,15 +8,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =0D #include "PeiPchPolicyUpdate.h"=0D #include =0D -#include =0D -#include =0D -#include =0D #include =0D #include =0D #include =0D #include =0D #include =0D -#include =0D =0D VOID=0D InstallPlatformHsioPtssTable (=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Inte= l/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolic= yUpdateLibFsp/PeiSaPolicyUpdate.c index d6ec3e38dd7e..b9c12f6e575a 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c @@ -7,12 +7,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/=0D =0D #include "PeiSaPolicyUpdate.h"=0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D #include =0D #include =0D #include =0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h b/Platform/Inte= l/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolic= yUpdateLibFsp/PeiSaPolicyUpdate.h index 3abf3fc8fd2f..fc96e6e600a5 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h @@ -12,18 +12,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // External include files do NOT need to be explicitly specified in real E= DKII=0D // environment=0D //=0D -#include =0D -#include =0D -#include =0D -#include =0D -#include "PeiPchPolicyUpdate.h"=0D -#include =0D -#include =0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D =0D #include =0D #include =0D #include =0D =0D +#include =0D +=0D extern EFI_GUID gTianoLogoGuid;=0D =0D #endif=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c b/Platfor= m/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSilico= nPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c index f95f82a25ca5..ec5f78cd8a64 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c @@ -7,20 +7,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/=0D =0D #include "PeiSaPolicyUpdate.h"=0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D #include =0D -#include =0D #include =0D -#include =0D -#include =0D -=0D =0D /**=0D Performs FSP SA PEI Policy initialization in pre-memory.=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/= Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/Pe= iSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf index f8bec0c852d6..adcb6f32ad90 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf @@ -41,6 +41,7 @@ PeiSaPolicyUpdate.c=0D PeiFspMiscUpdUpdateLib.c=0D PcieDeviceTable.c=0D + PeiBoardPolicyUpdate.c=0D =0D ##########################################################################= ######=0D #=0D @@ -55,43 +56,35 @@ IntelFsp2Pkg/IntelFsp2Pkg.dec=0D IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec=0D IntelSiliconPkg/IntelSiliconPkg.dec=0D - KabylakeSiliconPkg/SiPkg.dec=0D KabylakeFspBinPkg/KabylakeFspBinPkg.dec=0D + KabylakeSiliconPkg/SiPkg.dec=0D KabylakeOpenBoardPkg/OpenBoardPkg.dec=0D MinPlatformPkg/MinPlatformPkg.dec=0D =0D [LibraryClasses.IA32]=0D FspWrapperApiLib=0D - OcWdtLib=0D - PchResetLib=0D FspWrapperPlatformLib=0D BaseMemoryLib=0D - CpuPlatformLib=0D DebugLib=0D HobLib=0D IoLib=0D PcdLib=0D - PostCodeLib=0D - SmbusLib=0D MmPciLib=0D ConfigBlockLib=0D PeiSaPolicyLib=0D - PchGbeLib=0D PchInfoLib=0D PchHsioLib=0D PchPcieRpLib=0D MemoryAllocationLib=0D - CpuMailboxLib=0D - DebugPrintErrorLevelLib=0D SiPolicyLib=0D - PchGbeLib=0D - TimerLib=0D - GpioLib=0D PeiLib=0D =0D [Pcd]=0D + gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUME= S=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd ## CONSUME= S=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSUME= S=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSUME= S=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved ## CONSUME= S=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## CONSUME= S=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUME= S=0D =0D @@ -101,6 +94,9 @@ gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 ## CONSUME= S=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 ## CONSUME= S=0D =0D + # CA Vref Configuration=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig ## CONSUME= S=0D +=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize=0D =0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/= EcCommands.h b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Includ= e/EcCommands.h index be56d134edc7..57314d9a1678 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/EcComma= nds.h +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/EcComma= nds.h @@ -25,6 +25,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent //=0D // Status Port 0x62=0D //=0D +// FIXME: Some bits may be reserved=0D #define EC_S_OVR_TMP 0x80 // Current CPU temperature exceeds the th= reshold=0D #define EC_S_SMI_EVT 0x40 // SMI event is pending=0D #define EC_S_SCI_EVT 0x20 // SCI event is pending=0D @@ -39,6 +40,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // New commands and command parameters should only be written by the host = when IBF=3D0.=0D // Data read from the EC data port is valid only when OBF=3D1.=0D //=0D -#define EC_C_FAB_ID 0x0D // Get the board fab ID in = the lower 3 bits=0D +// TODO: It's unclear if the EC has such a command. Currently, we read mod= el ID from ADCs.=0D +// As a definition is required for build, use a known safe command: EC que= ry will do nicely.=0D +#define EC_C_FAB_ID 0x84 // Get the board fab ID in = the lower 3 bits=0D =0D #endif // EC_COMMANDS_H_=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/= Fdf/FlashMapInclude.fdf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash= 572G/Include/Fdf/FlashMapInclude.fdf index b5e3f66ceafc..aac4d83f6480 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/Fla= shMapInclude.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/Fla= shMapInclude.fdf @@ -1,5 +1,5 @@ ## @file=0D -# FDF file for the KabylakeRvp3 board.=0D +# FDF file for the Acer Aspire VN7-572G board.=0D #=0D # Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D #=0D @@ -8,41 +8,43 @@ ##=0D =0D #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D#=0D -# 8 M BIOS - for FSP wrapper=0D +# 6 M BIOS - for FSP wrapper=0D #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D#=0D -DEFINE FLASH_BASE =3D 0x= FF800000 #=0D -DEFINE FLASH_SIZE =3D 0x= 00800000 #=0D +DEFINE FLASH_BASE =3D 0x= FFA00000 #=0D +DEFINE FLASH_SIZE =3D 0x= 00600000 #=0D DEFINE FLASH_BLOCK_SIZE =3D 0x= 00010000 #=0D -DEFINE FLASH_NUM_BLOCKS =3D 0x= 00000080 #=0D +DEFINE FLASH_NUM_BLOCKS =3D 0x= 00000060 #=0D #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D#=0D =0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset =3D 0x= 00000000 # Flash addr (0xFF800000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset =3D 0x= 00000000 # Flash addr (0xFFA00000)=0D SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize =3D 0x= 00040000 #=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset =3D 0x= 00000000 # Flash addr (0xFF800000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset =3D 0x= 00000000 # Flash addr (0xFFA00000)=0D SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =3D 0x= 0001E000 #=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset =3D 0x= 0001E000 # Flash addr (0xFF81E000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset =3D 0x= 0001E000 # Flash addr (0xFFA1E000)=0D SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =3D 0x= 00002000 #=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset =3D 0x= 00020000 # Flash addr (0xFF820000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset =3D 0x= 00020000 # Flash addr (0xFFA20000)=0D SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D 0x= 00020000 #=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =3D 0x= 00040000 # Flash addr (0xFF840000)=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize =3D 0x= 00050000 #=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =3D 0x= 00090000 # Flash addr (0xFF890000)=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =3D 0x= 00070000 #=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =3D 0x= 00100000 # Flash addr (0xFF900000)=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize =3D 0x= 00090000 #=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =3D 0x= 00190000 # Flash addr (0xFF990000)=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D 0x= 001E0000 #=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D 0x= 00370000 # Flash addr (0xFFB70000)=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D 0x= 00180000 #=0D -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D 0x= 004F0000 # Flash addr (0xFFCF0000)=0D -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D 0x= 000A0000 #=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D 0x= 00590000 # Flash addr (0xFFD90000)=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D 0x= 00060000 #=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D 0x= 005F0000 # Flash addr (0xFFDF0000)=0D +SET gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageOffset=3D 0x= 00040000 # Flash addr (0xFFA40000)=0D +SET gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageSize =3D 0x= 00010000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =3D 0x= 00050000 # Flash addr (0xFFA50000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize =3D 0x= 000C0000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =3D 0x= 00110000 # Flash addr (0xFFB10000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =3D 0x= 00080000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =3D 0x= 00190000 # Flash addr (0xFFB90000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize =3D 0x= 000B0000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =3D 0x= 00240000 # Flash addr (0xFFC40000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D 0x= 00180000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D 0x= 003C0000 # Flash addr (0xFFDC0000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D 0x= 00020000 #=0D +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D 0x= 003E0000 # Flash addr (0xFFDE0000)=0D +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D 0x= 00080000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D 0x= 00460000 # Flash addr (0xFFE60000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D 0x= 0004C000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D 0x= 004AC000 # Flash addr (0xFFEAC000)=0D SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D 0x= 000BC000 #=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D 0x= 006AC000 # Flash addr (0xFFEAC000)=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D 0x= 00014000 #=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset =3D 0x= 006C0000 # Flash addr (0xFFEC0000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D 0x= 00568000 # Flash addr (0xFFF68000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D 0x= 00008000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset =3D 0x= 00570000 # Flash addr (0xFFF70000)=0D SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize =3D 0x= 00010000 #=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D 0x= 006D0000 # Flash addr (0xFFED0000)=0D -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D 0x= 00130000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D 0x= 00580000 # Flash addr (0xFFF80000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D 0x= 00080000 #=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/= Library/BoardEcLib.h b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572= G/Include/Library/BoardEcLib.h new file mode 100644 index 000000000000..682492e7d1c9 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library= /BoardEcLib.h @@ -0,0 +1,112 @@ +/** @file=0D + EC library functions and definitions.=0D +=0D + This library provides basic EC interface.=0D +=0D + There may be different libraries for different environments (PEI, BS, RT= , SMM).=0D + Make sure you meet the requirements for the library (protocol dependenci= es, use=0D + restrictions, etc).=0D +=0D +Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef _BOARD_EC_LIB_H_=0D +#define _BOARD_EC_LIB_H_=0D +=0D +/**=0D + Reads a byte of EC RAM.=0D +=0D + @param[in] Address Address to read=0D + @param[out] Data Data received=0D +=0D + @retval EFI_SUCCESS Command success=0D + @retval EFI_DEVICE_ERROR Command error=0D + @retval EFI_TIMEOUT Command timeout=0D +**/=0D +EFI_STATUS=0D +EcCmd90Read (=0D + IN UINT8 Address,=0D + OUT UINT8 *Data=0D + );=0D +=0D +/**=0D + Writes a byte of EC RAM.=0D +=0D + @param[in] Address Address to write=0D + @param[in] Data Data to write=0D +=0D + @retval EFI_SUCCESS Command success=0D + @retval EFI_DEVICE_ERROR Command error=0D + @retval EFI_TIMEOUT Command timeout=0D +**/=0D +EFI_STATUS=0D +EcCmd91Write (=0D + IN UINT8 Address,=0D + IN UINT8 Data=0D + );=0D +=0D +/**=0D + Query the EC status.=0D +=0D + @param[out] Status EC status byte=0D +=0D + @retval EFI_SUCCESS Command success=0D + @retval EFI_DEVICE_ERROR Command error=0D + @retval EFI_TIMEOUT Command timeout=0D +**/=0D +EFI_STATUS=0D +EcCmd94Query (=0D + OUT UINT8 *Data=0D + );=0D +=0D +/**=0D + Reads a byte of EC (index) RAM.=0D + TODO: Validate errors?=0D +=0D + @param[in] Address Address to read=0D + @param[out] Data Data received=0D +=0D + @retval EFI_SUCCESS Command success=0D + @retval EFI_DEVICE_ERROR Command error=0D + @retval EFI_TIMEOUT Command timeout=0D +**/=0D +VOID=0D +EcIdxRead (=0D + IN UINT16 Address,=0D + OUT UINT8 *Data=0D + );=0D +=0D +/**=0D + Writes a byte of EC (index) RAM.=0D + TODO: Validate errors?=0D +=0D + @param[in] Address Address to read=0D + @param[out] Data Data received=0D +=0D + @retval EFI_SUCCESS Command success=0D + @retval EFI_DEVICE_ERROR Command error=0D + @retval EFI_TIMEOUT Command timeout=0D +**/=0D +VOID=0D +EcIdxWrite (=0D + IN UINT16 Address,=0D + IN UINT8 Data=0D + );=0D +=0D +/**=0D + Read EC analog-digital converter.=0D +=0D + @param[out] DataBuffer=0D +=0D + @retval EFI_SUCCESS Command success=0D + @retval EFI_DEVICE_ERROR Command error=0D +**/=0D +EFI_STATUS=0D +ReadEcAdcConverter (=0D + IN UINT8 Adc,=0D + OUT UINT16 *DataBuffer=0D + );=0D +=0D +#endif=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/KabylakeOpenBoar= dPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.c deleted file mode 100644 index c7fc6986f547..000000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePla= tformHookLib/BasePlatformHookLib.c +++ /dev/null @@ -1,662 +0,0 @@ -/** @file=0D - Platform Hook Library instances=0D -=0D -Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D -SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -=0D -#define COM1_BASE 0x3f8=0D -#define COM2_BASE 0x2f8=0D -=0D -#define SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS 0x0690=0D -=0D -#define LPC_SIO_INDEX_DEFAULT_PORT_2 0x2E=0D -#define LPC_SIO_DATA_DEFAULT_PORT_2 0x2F=0D -#define LPC_SIO_GPIO_REGISTER_ADDRESS_2 0x0A20=0D -=0D -#define LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT 0x2E=0D -#define LEGACY_DAUGHTER_CARD_SIO_DATA_PORT 0x2F=0D -#define LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT 0x4E=0D -#define LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT 0x4F=0D -=0D -typedef struct {=0D - UINT8 Register;=0D - UINT8 Value;=0D -} EFI_SIO_TABLE;=0D -=0D -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTable[] =3D {=0D - {0x002, 0x88}, // Power On UARTs=0D - {0x024, COM1_BASE >> 2},=0D - {0x025, COM2_BASE >> 2},=0D - {0x028, 0x043}, // IRQ of UARTs, UART2 IRQ=3D3,UART1 IRQ=3D4,=0D - {0x029, 0x080}, // SIRQ_CLKRUN_EN=0D - {0x02A, 0x000},=0D - {0x02B, 0x0DE},=0D - {0x00A, 0x040},=0D - {0x00C, 0x00E},=0D - {0x02c, 0x002},=0D - {0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4},=0D - {0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8},=0D - {0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff},=0D - {0x03a, 0x00A}, // LPC Docking Enabling=0D - {0x031, 0x01f},=0D - {0x032, 0x000},=0D - {0x033, 0x004},=0D - {0x038, 0x0FB},=0D - {0x035, 0x0FE},=0D - {0x036, 0x000},=0D - {0x037, 0x0FF},=0D - {0x039, 0x000},=0D - {0x034, 0x001},=0D - {0x012, FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & 0xFF}, //= Relocate configuration ports base address=0D - {0x013, (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) >> 8) & 0xFF} //= to ensure SIO config address can be accessed in OS=0D -};=0D -=0D -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableSmsc1000[] =3D {=0D - {0x002, 0x88}, // Power On UARTs=0D - {0x007, 0x00},=0D - {0x024, COM1_BASE >> 2},=0D - {0x025, COM2_BASE >> 2},=0D - {0x028, 0x043}, // IRQ of UARTs, UART2 IRQ=3D3,UART1 IRQ=3D4,=0D - {0x029, 0x080}, // SIRQ_CLKRUN_EN=0D - {0x02A, 0x000},=0D - {0x02B, 0x0DE},=0D - {0x00A, 0x040},=0D - {0x00C, 0x00E},=0D - {0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4},=0D - {0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8},=0D - {0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff},=0D - {0x03a, 0x00A}, // LPC Docking Enabling=0D - {0x031, 0x01f},=0D - {0x032, 0x000},=0D - {0x033, 0x004},=0D - {0x038, 0x0FB},=0D - {0x035, 0x0FE},=0D - {0x036, 0x000},=0D - {0x037, 0x0FE},=0D - {0x039, 0x000},=0D - {0x034, 0x001}=0D -};=0D -=0D -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWpcn381u[] =3D {=0D - {0x29, 0x0A0}, // Enable super I/O clock and set to 48M= Hz=0D - {0x22, 0x003}, //=0D - {0x07, 0x003}, // Select UART0 device=0D - {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB=0D - {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB=0D - {0x70, 0x004}, // Set to IRQ4=0D - {0x30, 0x001}, // Enable it with Activation bit=0D - {0x07, 0x002}, // Select UART1 device=0D - {0x60, (COM2_BASE >> 8)}, // Set Base Address MSB=0D - {0x61, (COM2_BASE & 0x00FF)}, // Set Base Address LSB=0D - {0x70, 0x003}, // Set to IRQ3=0D - {0x30, 0x001}, // Enable it with Activation bit=0D - {0x07, 0x007}, // Select GPIO device=0D - {0x60, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 >> 8)}, // Set Base Address= MSB=0D - {0x61, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 & 0x00FF)}, // Set Base Address= LSB=0D - {0x30, 0x001}, // Enable it with Activation bit=0D - {0x21, 0x001}, // Global Device Enable=0D - {0x26, 0x000} // Fast Enable UART 0 & 1 as their enabl= e & activation bit=0D -};=0D -=0D -//=0D -// National PC8374L=0D -//=0D -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mDesktopSioTable[] =3D {=0D - {0x007, 0x03}, // Select Com1=0D - {0x061, 0xF8}, // 0x3F8=0D - {0x060, 0x03}, // 0x3F8=0D - {0x070, 0x04}, // IRQ4=0D - {0x030, 0x01} // Active=0D -};=0D -=0D -//=0D -// IT8628=0D -//=0D -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableSerialPort[] = =3D {=0D - {0x023, 0x09}, // Clock Selection register=0D - {0x007, 0x01}, // Com1 Logical Device Number select=0D - {0x061, 0xF8}, // Serial Port 1 Base Address MSB Register=0D - {0x060, 0x03}, // Serial Port 1 Base Address LSB Register=0D - {0x070, 0x04}, // Serial Port 1 Interrupt Level Select=0D - {0x030, 0x01}, // Serial Port 1 Activate=0D - {0x007, 0x02}, // Com1 Logical Device Number select=0D - {0x061, 0xF8}, // Serial Port 2 Base Address MSB Register=0D - {0x060, 0x02}, // Serial Port 2 Base Address MSB Register=0D - {0x070, 0x03}, // Serial Port 2 Interrupt Level Select=0D - {0x030, 0x01} // Serial Port 2 Activate=0D -};=0D -=0D -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableParallelPort[] = =3D {=0D - {0x007, 0x03}, // Parallel Port Logical Device Number select=0D - {0x030, 0x00}, // Parallel port Activate=0D - {0x061, 0x78}, // Parallel Port Base Address 1 MSB Register=0D - {0x060, 0x03}, // Parallel Port Base Address 1 LSB Register=0D - {0x063, 0x78}, // Parallel Port Base Address 2 MSB Register=0D - {0x062, 0x07}, // Parallel Port Base Address 1 LSB Register=0D - {0x0F0, 0x03} // Special Configuration register=0D -};=0D -=0D -=0D -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWinbondX374[] =3D {=0D - {0x07, 0x03}, // Select UART0 device=0D - {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB=0D - {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB=0D - {0x70, 0x04}, // Set to IRQ4=0D - {0x30, 0x01} // Enable it with Activation bit=0D -};=0D -=0D -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTablePilot3[] =3D {=0D - {0x07, 0x02}, // Set logical device SP Serial port Com0=0D - {0x61, 0xF8}, // Write Base Address LSB register 0x3F8=0D - {0x60, 0x03}, // Write Base Address MSB register 0x3F8=0D - {0x70, 0x04}, // Write IRQ1 value (IRQ 1) keyboard=0D - {0x30, 0x01} // Enable serial port with Activation bit=0D -};=0D -=0D -/**=0D - Detect if a National 393 SIO is docked. If yes, enable the docked SIO=0D - and its serial port, and disable the onboard serial port.=0D -=0D - @retval EFI_SUCCESS Operations performed successfully.=0D -**/=0D -STATIC=0D -VOID=0D -CheckNationalSio (=0D - VOID=0D - )=0D -{=0D - UINT8 Data8;=0D -=0D - //=0D - // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f).=0D - // We use (0x2e, 0x2f) which is determined by BADD default strapping=0D - //=0D -=0D - //=0D - // Read the Pc87393 signature=0D - //=0D - IoWrite8 (0x2e, 0x20);=0D - Data8 =3D IoRead8 (0x2f);=0D -=0D - if (Data8 =3D=3D 0xea) {=0D - //=0D - // Signature matches - National PC87393 SIO is docked=0D - //=0D -=0D - //=0D - // Enlarge the LPC decode scope to accommodate the Docking LPC Switch= =0D - // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated at=0D - // SIO_BASE_ADDRESS + 0x10)=0D - //=0D - PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & (UINT16)~0x7= F), 0x20);=0D -=0D - //=0D - // Enable port switch=0D - //=0D - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06);=0D -=0D - //=0D - // Turn on docking power=0D - //=0D - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c);=0D -=0D - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c);=0D -=0D - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc);=0D -=0D - //=0D - // Enable port switch=0D - //=0D - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7);=0D -=0D - //=0D - // GPIO setting=0D - //=0D - IoWrite8 (0x2e, 0x24);=0D - IoWrite8 (0x2f, 0x29);=0D -=0D - //=0D - // Enable chip clock=0D - //=0D - IoWrite8 (0x2e, 0x29);=0D - IoWrite8 (0x2f, 0x1e);=0D -=0D -=0D - //=0D - // Enable serial port=0D - //=0D -=0D - //=0D - // Select com1=0D - //=0D - IoWrite8 (0x2e, 0x7);=0D - IoWrite8 (0x2f, 0x3);=0D -=0D - //=0D - // Base address: 0x3f8=0D - //=0D - IoWrite8 (0x2e, 0x60);=0D - IoWrite8 (0x2f, 0x03);=0D - IoWrite8 (0x2e, 0x61);=0D - IoWrite8 (0x2f, 0xf8);=0D -=0D - //=0D - // Interrupt: 4=0D - //=0D - IoWrite8 (0x2e, 0x70);=0D - IoWrite8 (0x2f, 0x04);=0D -=0D - //=0D - // Enable bank selection=0D - //=0D - IoWrite8 (0x2e, 0xf0);=0D - IoWrite8 (0x2f, 0x82);=0D -=0D - //=0D - // Activate=0D - //=0D - IoWrite8 (0x2e, 0x30);=0D - IoWrite8 (0x2f, 0x01);=0D -=0D - //=0D - // Disable onboard serial port=0D - //=0D - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55);=0D -=0D - //=0D - // Power Down UARTs=0D - //=0D - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2);=0D - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00);=0D -=0D - //=0D - // Dissable COM1 decode=0D - //=0D - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24);=0D - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);=0D -=0D - //=0D - // Disable COM2 decode=0D - //=0D - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25);=0D - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);=0D -=0D - //=0D - // Disable interrupt=0D - //=0D - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28);=0D - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0);=0D -=0D - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);=0D -=0D - //=0D - // Enable floppy=0D - //=0D -=0D - //=0D - // Select floppy=0D - //=0D - IoWrite8 (0x2e, 0x7);=0D - IoWrite8 (0x2f, 0x0);=0D -=0D - //=0D - // Base address: 0x3f0=0D - //=0D - IoWrite8 (0x2e, 0x60);=0D - IoWrite8 (0x2f, 0x03);=0D - IoWrite8 (0x2e, 0x61);=0D - IoWrite8 (0x2f, 0xf0);=0D -=0D - //=0D - // Interrupt: 6=0D - //=0D - IoWrite8 (0x2e, 0x70);=0D - IoWrite8 (0x2f, 0x06);=0D -=0D - //=0D - // DMA 2=0D - //=0D - IoWrite8 (0x2e, 0x74);=0D - IoWrite8 (0x2f, 0x02);=0D -=0D - //=0D - // Activate=0D - //=0D - IoWrite8 (0x2e, 0x30);=0D - IoWrite8 (0x2f, 0x01);=0D -=0D - } else {=0D -=0D - //=0D - // No National pc87393 SIO is docked, turn off dock power and=0D - // disable port switch=0D - //=0D - // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf);=0D - // IoWrite8 (0x690, 0);=0D -=0D - //=0D - // If no National pc87393, just return=0D - //=0D - return;=0D - }=0D -}=0D -=0D -=0D -/**=0D -Check whether the IT8628 SIO present on LPC. If yes, enable its serial=0D -ports, parallel port, and port 80.=0D -=0D -@retval EFI_SUCCESS Operations performed successfully.=0D -**/=0D -STATIC=0D -VOID=0D -It8628SioSerialPortInit (=0D - VOID=0D - )=0D -{=0D - UINT8 ChipId0 =3D 0;=0D - UINT8 ChipId1 =3D 0;=0D - UINT16 LpcIoDecondeRangeSet =3D 0;=0D - UINT16 LpcIoDecoodeSet =3D 0;=0D - UINT8 Index;=0D - UINTN LpcBaseAddr;=0D -=0D -=0D - //=0D - // Enable I/O decoding for COM1 (3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2= Eh/2Fh.=0D - //=0D - LpcBaseAddr =3D MmPciBase (=0D - DEFAULT_PCI_BUS_NUMBER_PCH,=0D - PCI_DEVICE_NUMBER_PCH_LPC,=0D - PCI_FUNCTION_NUMBER_PCH_LPC=0D - );=0D -=0D - LpcIoDecondeRangeSet =3D (UINT16) MmioRead16 (LpcBaseAddr + R_PCH_LPC_IO= D);=0D - LpcIoDecoodeSet =3D (UINT16) MmioRead16 (LpcBaseAddr + R_PCH_LPC_IOE);=0D - MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOD), (LpcIoDecondeRangeSet | ((V_= PCH_LPC_IOD_COMB_2F8 << 4) | V_PCH_LPC_IOD_COMA_3F8)));=0D - MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOE), (LpcIoDecoodeSet | (B_PCH_LP= C_IOE_SE | B_PCH_LPC_IOE_CBE | B_PCH_LPC_IOE_CAE)));=0D -=0D - //=0D - // Enter MB PnP Mode=0D - //=0D - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x87);=0D - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x01);=0D - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55);=0D - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55);=0D -=0D - //=0D - // Read Chip Id of SIO IT8628 (registers 0x20 and 0x21)=0D - //=0D - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x20);=0D - ChipId0 =3D IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);=0D -=0D - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x21);=0D - ChipId1 =3D IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);=0D -=0D - //=0D - // Enable Serial Port 1, Port 2=0D - //=0D - if ((ChipId0 =3D=3D 0x86) && (ChipId1 =3D=3D 0x28)) {=0D - for (Index =3D 0; Index < sizeof (mSioIt8628TableSerialPort) / sizeof = (EFI_SIO_TABLE); Index++) {=0D - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, mSioIt8628TableSerialPort[In= dex].Register);=0D - IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Ind= ex].Value);=0D - }=0D - }=0D -=0D - //=0D - // Exit MB PnP Mode=0D - //=0D - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x02);=0D - IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, 0x02);=0D -=0D - return;=0D -}=0D -=0D -=0D -/**=0D - Performs platform specific initialization required for the CPU to access= =0D - the hardware associated with a SerialPortLib instance. This function do= es=0D - not initialize the serial port hardware itself. Instead, it initializes= =0D - hardware devices that are required for the CPU to access the serial port= =0D - hardware. This function may be called more than once.=0D -=0D - @retval RETURN_SUCCESS The platform specific initialization succee= ded.=0D - @retval RETURN_DEVICE_ERROR The platform specific initialization could = not be completed.=0D -=0D -**/=0D -RETURN_STATUS=0D -EFIAPI=0D -PlatformHookSerialPortInitialize (=0D - VOID=0D - )=0D -{=0D - UINT16 ConfigPort;=0D - UINT16 IndexPort;=0D - UINT16 DataPort;=0D - UINT16 DeviceId;=0D - UINT8 Index;=0D - UINT16 AcpiBase;=0D -=0D - //=0D - // Set the ICH ACPI Base Address (Reg#40h) and ACPI Enable bit=0D - // in ACPI Controll (Reg#44h bit7) for PrePpiStall function use.=0D - //=0D - IndexPort =3D 0;=0D - DataPort =3D 0;=0D - Index =3D 0;=0D - AcpiBase =3D 0;=0D - PchAcpiBaseGet (&AcpiBase);=0D - if (AcpiBase =3D=3D 0) {=0D - PchAcpiBaseSet (PcdGet16 (PcdAcpiBaseAddress));=0D - }=0D -=0D - //=0D - // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2E= h/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h.=0D - //=0D - PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));=0D - PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));=0D -=0D - // Configure Sio IT8628=0D - It8628SioSerialPortInit ();=0D -=0D - DeviceId =3D MmioRead16 (MmPciBase (SA_MC_BUS, 0, 0) + R_SA_MC_DEVICE_ID= );=0D - if (IS_SA_DEVICE_ID_MOBILE (DeviceId)) {=0D - //=0D - // if no EC, it is SV Bidwell Bar board=0D - //=0D - if ((IoRead8 (0x66) !=3D 0xFF) && (IoRead8 (0x62) !=3D 0xFF)) {=0D - //=0D - // Super I/O initialization for SMSC SI1007=0D - //=0D - ConfigPort =3D FixedPcdGet16 (PcdLpcSioConfigDefaultPort);=0D - DataPort =3D PcdGet16 (PcdLpcSioDataDefaultPort);=0D - IndexPort =3D PcdGet16 (PcdLpcSioIndexDefaultPort);=0D -=0D - //=0D - // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF;=0D - //=0D - PchLpcGenIoRangeSet (FixedPcdGet16 (PcdSioBaseAddress) & (~0x7F), 0x= 10);=0D -=0D - //=0D - // Program and Enable Default Super IO Configuration Port Addresses = and range=0D - //=0D - PchLpcGenIoRangeSet (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & (~= 0xF), 0x10);=0D -=0D - //=0D - // Enter Config Mode=0D - //=0D - IoWrite8 (ConfigPort, 0x55);=0D -=0D - //=0D - // Check for SMSC SIO1007=0D - //=0D - IoWrite8 (IndexPort, 0x0D); // SMSC SIO1007 Device ID register is = 0x0D=0D - if (IoRead8 (DataPort) =3D=3D 0x20) { // SMSC SIO1007 Device ID is= 0x20=0D - //=0D - // Configure SIO=0D - //=0D - for (Index =3D 0; Index < sizeof (mSioTable) / sizeof (EFI_SIO_TAB= LE); Index++) {=0D - IoWrite8 (IndexPort, mSioTable[Index].Register);=0D - IoWrite8 (DataPort, mSioTable[Index].Value);=0D - }=0D -=0D - //=0D - // Exit Config Mode=0D - //=0D - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);=0D -=0D - //=0D - // GPIO 15-17:IN 10-14:OUT Enable RS232 ref: Page42 of CRB_SCH= =0D - //=0D - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0c, 0x1f);=0D - }=0D -=0D - //=0D - // Check if a National Pc87393 SIO is docked=0D - //=0D - CheckNationalSio ();=0D -=0D - //=0D - // Super I/O initialization for SMSC SIO1000=0D - //=0D - ConfigPort =3D PcdGet16 (PcdLpcSioIndexPort);=0D - IndexPort =3D PcdGet16 (PcdLpcSioIndexPort);=0D - DataPort =3D PcdGet16 (PcdLpcSioDataPort);=0D -=0D - //=0D - // Enter Config Mode=0D - //=0D - IoWrite8 (ConfigPort, 0x55);=0D -=0D - //=0D - // Check for SMSC SIO1000=0D - //=0D - if (IoRead8 (ConfigPort) !=3D 0xFF) {=0D - //=0D - // Configure SIO=0D - //=0D - for (Index =3D 0; Index < sizeof (mSioTableSmsc1000) / sizeof (EFI= _SIO_TABLE); Index++) {=0D - IoWrite8 (IndexPort, mSioTableSmsc1000[Index].Register);=0D - IoWrite8 (DataPort, mSioTableSmsc1000[Index].Value);=0D - }=0D -=0D - //=0D - // Exit Config Mode=0D - //=0D - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);=0D - }=0D -=0D - //=0D - // Super I/O initialization for Winbond WPCN381U=0D - //=0D - IndexPort =3D LPC_SIO_INDEX_DEFAULT_PORT_2;=0D - DataPort =3D LPC_SIO_DATA_DEFAULT_PORT_2;=0D -=0D - //=0D - // Check for Winbond WPCN381U=0D - //=0D - IoWrite8 (IndexPort, 0x20); // Winbond WPCN381U Device ID re= gister is 0x20=0D - if (IoRead8 (DataPort) =3D=3D 0xF4) { // Winbond WPCN381U Device I= D is 0xF4=0D - //=0D - // Configure SIO=0D - //=0D - for (Index =3D 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI= _SIO_TABLE); Index++) {=0D - IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);=0D - IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);=0D - }=0D - }=0D - } //EC is not exist, skip mobile board detection for SV board=0D -=0D - //=0D - //add for SV Bidwell Bar board=0D - //=0D - if (IoRead8 (COM1_BASE) =3D=3D 0xFF) {=0D - //=0D - // Super I/O initialization for Winbond WPCD374 (LDC2) and 8374 (LDC= )=0D - // Looking for LDC2 card first=0D - //=0D - IoWrite8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT, 0x55);=0D - if (IoRead8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT) =3D=3D 0x55) {=0D - IndexPort =3D LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;=0D - DataPort =3D LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT;=0D - } else {=0D - IndexPort =3D LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT;=0D - DataPort =3D LEGACY_DAUGHTER_CARD_SIO_DATA_PORT;=0D - }=0D -=0D - IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID regist= er is 0x20=0D - if (IoRead8 (DataPort) =3D=3D 0xF1) { // Winbond x374 Device ID is= 0xF1=0D - for (Index =3D 0; Index < sizeof (mSioTableWinbondX374) / sizeof (= EFI_SIO_TABLE); Index++) {=0D - IoWrite8 (IndexPort, mSioTableWinbondX374[Index].Register);=0D - IoWrite8 (DataPort, mSioTableWinbondX374[Index].Value);=0D - }=0D - }=0D - }// end of Bidwell Bar SIO initialization=0D - } else if (IS_SA_DEVICE_ID_DESKTOP (DeviceId) || IS_SA_DEVICE_ID_SERVER= (DeviceId)) {=0D - //=0D - // If we are in debug mode, we will allow serial status codes=0D - //=0D -=0D - //=0D - // National PC8374 SIO & Winbond WPCD374 (LDC2)=0D - //=0D - IndexPort =3D LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;=0D -=0D - IoWrite8 (IndexPort, 0x55);=0D - if (IoRead8 (IndexPort) =3D=3D 0x55) {=0D - IndexPort =3D LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;=0D - DataPort =3D LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT;=0D - } else {=0D - IndexPort =3D LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT;=0D - DataPort =3D LEGACY_DAUGHTER_CARD_SIO_DATA_PORT;=0D - }=0D -=0D - //=0D - // Configure SIO=0D - //=0D - IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID register= is 0x20=0D - if (IoRead8 (DataPort) =3D=3D 0xF1) { // Winbond x374 Device ID is 0= xF1=0D - for (Index =3D 0; Index < sizeof (mDesktopSioTable) / sizeof (EFI_SI= O_TABLE); Index++) {=0D - IoWrite8 (IndexPort, mDesktopSioTable[Index].Register);=0D - //PrePpiStall (200);=0D - IoWrite8 (DataPort, mDesktopSioTable[Index].Value);=0D - //PrePpiStall (200);=0D - }=0D - return RETURN_SUCCESS;=0D - }=0D - //=0D - // Configure Pilot3 SIO=0D - //=0D - IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_UNLOCK); //Enter config mo= de.=0D - IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_CHIP_ID_REG); // Pilot= 3 SIO Device ID register is 0x20.=0D - if (IoRead8 (PILOTIII_SIO_DATA_PORT) =3D=3D PILOTIII_CHIP_ID) { // = Pilot3 SIO Device ID register is 0x03.=0D - //=0D - // Configure SIO=0D - //=0D - for (Index =3D 0; Index < sizeof (mSioTablePilot3) / sizeof (EFI_SIO= _TABLE); Index++) {=0D - IoWrite8 (PILOTIII_SIO_INDEX_PORT, mSioTablePilot3[Index].Register= );=0D - IoWrite8 (PILOTIII_SIO_DATA_PORT, mSioTablePilot3[Index].Value);=0D - }=0D - }=0D - IoWrite8 (PILOTIII_SIO_INDEX_PORT , PILOTIII_LOCK); //Exit config mode= .=0D - }=0D -=0D -=0D - return RETURN_SUCCESS;=0D -}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/KabylakeOpenBo= ardPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.inf deleted file mode 100644 index 7a5e290657f2..000000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePla= tformHookLib/BasePlatformHookLib.inf +++ /dev/null @@ -1,51 +0,0 @@ -### @file=0D -# Platform Hook Library instance for Kaby Lake RVP3.=0D -#=0D -# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D -#=0D -# SPDX-License-Identifier: BSD-2-Clause-Patent=0D -#=0D -###=0D -=0D -[Defines]=0D - INF_VERSION =3D 0x00010017=0D - BASE_NAME =3D BasePlatformHookLib=0D - FILE_GUID =3D E22ADCC6-ED90-4A90-9837-C8E7FF9E963D= =0D - VERSION_STRING =3D 1.0=0D - MODULE_TYPE =3D BASE=0D - LIBRARY_CLASS =3D PlatformHookLib=0D -#=0D -# The following information is for reference only and not required by the = build tools.=0D -#=0D -# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D -#=0D -=0D -[LibraryClasses]=0D - BaseLib=0D - IoLib=0D - MmPciLib=0D - PciLib=0D - PchCycleDecodingLib=0D -=0D -[Packages]=0D - MdePkg/MdePkg.dec=0D - MdeModulePkg/MdeModulePkg.dec=0D - MinPlatformPkg/MinPlatformPkg.dec=0D - KabylakeOpenBoardPkg/OpenBoardPkg.dec=0D - KabylakeSiliconPkg/SiPkg.dec=0D -=0D -[Pcd]=0D - gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSU= MES=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## CONSU= MES=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## CONSU= MES=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## CONSU= MES=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataDefaultPort ## CONSU= MES=0D -=0D -[FixedPcd]=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSU= MES=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress ## CONSU= MES=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSU= MES=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSU= MES=0D -=0D -[Sources]=0D - BasePlatformHookLib.c=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/DxeAspireVn7Dash572GAcpiTableLib.c b/Platform/Intel/KabylakeOp= enBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeAspireVn7Dash572GAcpiT= ableLib.c index d66283f7e830..3af2a83927fa 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/DxeAspireVn7Dash572GAcpiTableLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/DxeAspireVn7Dash572GAcpiTableLib.c @@ -1,5 +1,5 @@ /** @file=0D - Kaby Lake RVP 3 Board ACPI Library=0D + Aspire VN7-572G Board ACPI Library=0D =0D Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D @@ -7,26 +7,21 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/=0D =0D #include =0D -#include =0D #include =0D -#include =0D -#include =0D #include =0D +#include =0D #include =0D -#include =0D -#include =0D -#include =0D #include =0D =0D -#include =0D -=0D GLOBAL_REMOVE_IF_UNREFERENCED EFI_GLOBAL_NVS_AREA_PROTOCOL mG= lobalNvsArea;=0D =0D VOID=0D -KabylakeRvp3UpdateGlobalNvs (=0D +AspireVn7Dash572GUpdateGlobalNvs (=0D VOID=0D )=0D {=0D + EFI_STATUS Status;=0D + UINT8 PowerRegister;=0D =0D //=0D // Allocate and initialize the NVS area for SMM and ASL communication.=0D @@ -40,7 +35,11 @@ KabylakeRvp3UpdateGlobalNvs ( //=0D // Enable PowerState=0D //=0D - mGlobalNvsArea.Area->PowerState =3D 1; // AC =3D1; for mobile platform, = will update this value in SmmPlatform.c=0D + Status =3D EcRead(0x70, &PowerRegister);=0D + if (EFI_ERROR(Status)) {=0D + PowerRegister =3D 0;=0D + }=0D + mGlobalNvsArea.Area->PowerState =3D (PowerRegister & BIT5) =3D=3D BIT5;= =0D =0D mGlobalNvsArea.Area->NativePCIESupport =3D PcdGet8 (PcdPciExpNati= ve);=0D =0D @@ -54,7 +53,7 @@ KabylakeRvp3UpdateGlobalNvs ( //=0D mGlobalNvsArea.Area->LowPowerS0Idle =3D PcdGet8 (PcdLowPowerS0Idle);=0D =0D - mGlobalNvsArea.Area->Ps2MouseEnable =3D FALSE;=0D + mGlobalNvsArea.Area->Ps2MouseEnable =3D PcdGet8 (PcdPs2KbMsEnable);= =0D mGlobalNvsArea.Area->Ps2KbMsEnable =3D PcdGet8 (PcdPs2KbMsEnable);= =0D =0D mGlobalNvsArea.Area->BoardId =3D (UINT8) LibPcdGetSku ();=0D @@ -62,13 +61,13 @@ KabylakeRvp3UpdateGlobalNvs ( =0D EFI_STATUS=0D EFIAPI=0D -KabylakeRvp3BoardUpdateAcpiTable (=0D +AspireVn7Dash572GBoardUpdateAcpiTable (=0D IN OUT EFI_ACPI_COMMON_HEADER *Table,=0D IN OUT EFI_ACPI_TABLE_VERSION *Version=0D )=0D {=0D if (Table->Signature =3D=3D EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTI= ON_TABLE_SIGNATURE) {=0D - KabylakeRvp3UpdateGlobalNvs ();=0D + AspireVn7Dash572GUpdateGlobalNvs ();=0D }=0D =0D return EFI_SUCCESS;=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/DxeBoardAcpiTableLib.c b/Platform/Intel/KabylakeOpenBoardPkg/A= spireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c index 8699f8d4033f..37d15be76f76 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/DxeBoardAcpiTableLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/DxeBoardAcpiTableLib.c @@ -1,5 +1,5 @@ /** @file=0D - Kaby Lake RVP 3 Board ACPI library=0D + Aspire VN7-572G Board ACPI library=0D =0D Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D @@ -7,17 +7,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/=0D =0D #include =0D -#include =0D #include =0D -#include =0D -#include =0D #include =0D -#include =0D -#include =0D =0D EFI_STATUS=0D EFIAPI=0D -KabylakeRvp3BoardUpdateAcpiTable (=0D +AspireVn7Dash572GBoardUpdateAcpiTable (=0D IN OUT EFI_ACPI_COMMON_HEADER *Table,=0D IN OUT EFI_ACPI_TABLE_VERSION *Version=0D );=0D @@ -29,7 +24,7 @@ BoardUpdateAcpiTable ( IN OUT EFI_ACPI_TABLE_VERSION *Version=0D )=0D {=0D - KabylakeRvp3BoardUpdateAcpiTable (Table, Version);=0D + AspireVn7Dash572GBoardUpdateAcpiTable (Table, Version);=0D =0D return EFI_SUCCESS;=0D }=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/DxeBoardAcpiTableLib.inf b/Platform/Intel/KabylakeOpenBoardPkg= /AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf index e0bf5823d8c6..7b526ffcddad 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/DxeBoardAcpiTableLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/DxeBoardAcpiTableLib.inf @@ -1,5 +1,5 @@ ### @file=0D -# Kaby Lake RVP 3 Board ACPI library=0D +# Acer Aspire VN7-572G Board ACPI library=0D #=0D # Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D #=0D @@ -26,6 +26,7 @@ IoLib=0D PciLib=0D AslUpdateLib=0D + EcLib=0D =0D [Packages]=0D MdePkg/MdePkg.dec=0D @@ -38,11 +39,10 @@ [Pcd]=0D gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress=0D =0D [Sources]=0D - DxeKabylakeRvp3AcpiTableLib.c=0D + DxeAspireVn7Dash572GAcpiTableLib.c=0D DxeBoardAcpiTableLib.c=0D =0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c b/Platform/Intel/KabylakeOpenBoa= rdPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c deleted file mode 100644 index dfb1b028f18f..000000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/DxeMultiBoardAcpiSupportLib.c +++ /dev/null @@ -1,43 +0,0 @@ -/** @file=0D - Kaby Lake RVP 3 Multi-Board ACPI Support library=0D -=0D -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D -SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -=0D -#include =0D -=0D -EFI_STATUS=0D -EFIAPI=0D -KabylakeRvp3BoardUpdateAcpiTable (=0D - IN OUT EFI_ACPI_COMMON_HEADER *Table,=0D - IN OUT EFI_ACPI_TABLE_VERSION *Version=0D - );=0D -=0D -BOARD_ACPI_TABLE_FUNC mKabylakeRvp3BoardAcpiTableFunc =3D {=0D - KabylakeRvp3BoardUpdateAcpiTable=0D -};=0D -=0D -EFI_STATUS=0D -EFIAPI=0D -DxeKabylakeRvp3MultiBoardAcpiSupportLibConstructor (=0D - VOID=0D - )=0D -{=0D - if ((LibPcdGetSku () =3D=3D BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSku= () =3D=3D BoardIdSkylakeRvp3)) {=0D - return RegisterBoardAcpiTableFunc (&mKabylakeRvp3BoardAcpiTableFunc);= =0D - }=0D - return EFI_SUCCESS;=0D -}=0D -=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf b/Platform/Intel/KabylakeOpenB= oardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.= inf deleted file mode 100644 index e5de9268e71e..000000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/DxeMultiBoardAcpiSupportLib.inf +++ /dev/null @@ -1,49 +0,0 @@ -### @file=0D -# Kaby Lake RVP 3 Multi-Board ACPI Support library=0D -#=0D -# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D -#=0D -# SPDX-License-Identifier: BSD-2-Clause-Patent=0D -#=0D -###=0D -=0D -[Defines]=0D - INF_VERSION =3D 0x00010017=0D - BASE_NAME =3D DxeKabylakeRvp3MultiBoardAcpiTableLib= =0D - FILE_GUID =3D 8E6A3B38-53E0-48C0-970F-058F380FCB80= =0D - VERSION_STRING =3D 1.0=0D - MODULE_TYPE =3D BASE=0D - LIBRARY_CLASS =3D NULL=0D - CONSTRUCTOR =3D DxeKabylakeRvp3MultiBoardAcpiSupportL= ibConstructor=0D -=0D -#=0D -# The following information is for reference only and not required by the = build tools.=0D -#=0D -# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D -#=0D -=0D -[LibraryClasses]=0D - BaseLib=0D - IoLib=0D - PciLib=0D - AslUpdateLib=0D -=0D -[Packages]=0D - MdePkg/MdePkg.dec=0D - MdeModulePkg/MdeModulePkg.dec=0D - MinPlatformPkg/MinPlatformPkg.dec=0D - KabylakeOpenBoardPkg/OpenBoardPkg.dec=0D - KabylakeSiliconPkg/SiPkg.dec=0D - BoardModulePkg/BoardModulePkg.dec=0D -=0D -[Pcd]=0D - gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress=0D -=0D -[Sources]=0D - DxeKabylakeRvp3AcpiTableLib.c=0D - DxeMultiBoardAcpiSupportLib.c=0D -=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/SmmAspireVn7Dash572GAcpiEnableLib.c b/Platform/Intel/KabylakeO= penBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmAspireVn7Dash572GAcpi= EnableLib.c index 54755dd17695..8c7585f3c573 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/SmmAspireVn7Dash572GAcpiEnableLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/SmmAspireVn7Dash572GAcpiEnableLib.c @@ -1,5 +1,5 @@ /** @file=0D - Kaby Lake RVP 3 SMM Board ACPI Enable library=0D + Acer Aspire VN7-572G SMM Board ACPI Enable library=0D =0D Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D @@ -7,33 +7,59 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/=0D =0D #include =0D -#include =0D #include =0D -#include =0D -#include =0D -#include =0D -#include =0D #include =0D -=0D -#include =0D +#include =0D =0D EFI_STATUS=0D EFIAPI=0D -KabylakeRvp3BoardEnableAcpi (=0D +AspireVn7Dash572GBoardEnableAcpi (=0D IN BOOLEAN EnableSci=0D )=0D {=0D - // enable additional board register=0D + EFI_STATUS Status;=0D +=0D + /* Tests at runtime show this re-enables charging and battery reporting = */=0D + Status =3D SendEcCommand(0xE9); /* Vendor implements using ACPI "CMDB" = register" */=0D + if (EFI_ERROR(Status)) {=0D + DEBUG((DEBUG_ERROR, "%a(): SendEcCommand(0xE9) failed!\n", __func__));= =0D + return EFI_DEVICE_ERROR;=0D + }=0D +=0D + Status =3D SendEcData(0x81);=0D + if (EFI_ERROR(Status)) {=0D + DEBUG((DEBUG_ERROR, "%a(): SendEcData(0x81) failed!\n", __func__));=0D + return EFI_DEVICE_ERROR;=0D + }=0D +=0D + /* TODO: Set touchpad GPP owner to ACPI? */=0D +=0D return EFI_SUCCESS;=0D }=0D =0D EFI_STATUS=0D EFIAPI=0D -KabylakeRvp3BoardDisableAcpi (=0D +AspireVn7Dash572GBoardDisableAcpi (=0D IN BOOLEAN DisableSci=0D )=0D {=0D - // enable additional board register=0D + EFI_STATUS Status;=0D +=0D + /* Tests at runtime show this disables charging and battery reporting */= =0D + Status =3D SendEcCommand(0xE9); /* Vendor implements using ACPI "CMDB" = register" */=0D + if (EFI_ERROR(Status)) {=0D + DEBUG((DEBUG_ERROR, "%a(): SendEcCommand(0xE9) failed!\n", __func__));= =0D + return EFI_DEVICE_ERROR;=0D + }=0D +=0D + Status =3D SendEcData(0x80);=0D + if (EFI_ERROR(Status)) {=0D + DEBUG((DEBUG_ERROR, "%a(): SendEcData(0x80) failed!\n", __func__));=0D + return EFI_DEVICE_ERROR;=0D + }=0D +=0D + /* TODO: Set touchpad GPP owner to GPIO? */=0D +=0D return EFI_SUCCESS;=0D }=0D =0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/SmmBoardAcpiEnableLib.c b/Platform/Intel/KabylakeOpenBoardPkg/= AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c index e89624ea0372..c6a3154d0657 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/SmmBoardAcpiEnableLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/SmmBoardAcpiEnableLib.c @@ -1,5 +1,5 @@ /** @file=0D - Kaby Lake RVP 3 SMM Board ACPI Enable library=0D + Acer Aspire VN7-572G SMM Board ACPI Enable library=0D =0D Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D @@ -7,23 +7,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/=0D =0D #include =0D -#include =0D #include =0D -#include =0D -#include =0D #include =0D -#include =0D -#include =0D =0D EFI_STATUS=0D EFIAPI=0D -KabylakeRvp3BoardEnableAcpi (=0D +AspireVn7Dash572GBoardEnableAcpi (=0D IN BOOLEAN EnableSci=0D );=0D =0D EFI_STATUS=0D EFIAPI=0D -KabylakeRvp3BoardDisableAcpi (=0D +AspireVn7Dash572GBoardDisableAcpi (=0D IN BOOLEAN DisableSci=0D );=0D =0D @@ -46,7 +41,7 @@ BoardEnableAcpi ( )=0D {=0D SiliconEnableAcpi (EnableSci);=0D - return KabylakeRvp3BoardEnableAcpi (EnableSci);=0D + return AspireVn7Dash572GBoardEnableAcpi (EnableSci);=0D }=0D =0D EFI_STATUS=0D @@ -56,7 +51,5 @@ BoardDisableAcpi ( )=0D {=0D SiliconDisableAcpi (DisableSci);=0D - return KabylakeRvp3BoardDisableAcpi (DisableSci);=0D + return AspireVn7Dash572GBoardDisableAcpi (DisableSci);=0D }=0D -=0D -=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/SmmBoardAcpiEnableLib.inf b/Platform/Intel/KabylakeOpenBoardPk= g/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf index 46a714dc1d97..fb6fcf974f44 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/SmmBoardAcpiEnableLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/SmmBoardAcpiEnableLib.inf @@ -1,5 +1,5 @@ ### @file=0D -# Kaby Lake RVP 3 SMM Board ACPI Enable library=0D +# Acer Aspire VN7-572G SMM Board ACPI Enable library=0D #=0D # Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D #=0D @@ -23,6 +23,7 @@ =0D [LibraryClasses]=0D BaseLib=0D + EcLib=0D IoLib=0D PciLib=0D MmPciLib=0D @@ -41,7 +42,7 @@ [Protocols]=0D =0D [Sources]=0D - SmmKabylakeRvp3AcpiEnableLib.c=0D + SmmAspireVn7Dash572GAcpiEnableLib.c=0D SmmSiliconAcpiEnableLib.c=0D SmmBoardAcpiEnableLib.c=0D =0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/KabylakeOpenBoa= rdPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c deleted file mode 100644 index fb678a19bcf9..000000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/SmmMultiBoardAcpiSupportLib.c +++ /dev/null @@ -1,81 +0,0 @@ -/** @file=0D - Kaby Lake RVP 3 SMM Multi-Board ACPI Support library=0D -=0D -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D -SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -=0D -#include =0D -=0D -EFI_STATUS=0D -EFIAPI=0D -KabylakeRvp3BoardEnableAcpi (=0D - IN BOOLEAN EnableSci=0D - );=0D -=0D -EFI_STATUS=0D -EFIAPI=0D -KabylakeRvp3BoardDisableAcpi (=0D - IN BOOLEAN DisableSci=0D - );=0D -=0D -EFI_STATUS=0D -EFIAPI=0D -SiliconEnableAcpi (=0D - IN BOOLEAN EnableSci=0D - );=0D -=0D -EFI_STATUS=0D -EFIAPI=0D -SiliconDisableAcpi (=0D - IN BOOLEAN DisableSci=0D - );=0D -=0D -EFI_STATUS=0D -EFIAPI=0D -KabylakeRvp3MultiBoardEnableAcpi (=0D - IN BOOLEAN EnableSci=0D - )=0D -{=0D - SiliconEnableAcpi (EnableSci);=0D - return KabylakeRvp3BoardEnableAcpi (EnableSci);=0D -}=0D -=0D -EFI_STATUS=0D -EFIAPI=0D -KabylakeRvp3MultiBoardDisableAcpi (=0D - IN BOOLEAN DisableSci=0D - )=0D -{=0D - SiliconDisableAcpi (DisableSci);=0D - return KabylakeRvp3BoardDisableAcpi (DisableSci);=0D -}=0D -=0D -BOARD_ACPI_ENABLE_FUNC mKabylakeRvp3BoardAcpiEnableFunc =3D {=0D - KabylakeRvp3MultiBoardEnableAcpi,=0D - KabylakeRvp3MultiBoardDisableAcpi,=0D -};=0D -=0D -EFI_STATUS=0D -EFIAPI=0D -SmmKabylakeRvp3MultiBoardAcpiSupportLibConstructor (=0D - VOID=0D - )=0D -{=0D - if ((LibPcdGetSku () =3D=3D BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSk= u () =3D=3D BoardIdSkylakeRvp3)) {=0D - return RegisterBoardAcpiEnableFunc (&mKabylakeRvp3BoardAcpiEnableFunc= );=0D - }=0D - return EFI_SUCCESS;=0D -}=0D -=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/KabylakeOpenB= oardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.= inf deleted file mode 100644 index fca63c831431..000000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/SmmMultiBoardAcpiSupportLib.inf +++ /dev/null @@ -1,48 +0,0 @@ -### @file=0D -# Kaby Lake RVP 3 SMM Multi-Board ACPI Support library=0D -#=0D -# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D -#=0D -# SPDX-License-Identifier: BSD-2-Clause-Patent=0D -#=0D -###=0D -=0D -[Defines]=0D - INF_VERSION =3D 0x00010017=0D - BASE_NAME =3D SmmKabylakeRvp3MultiBoardAcpiSupportL= ib=0D - FILE_GUID =3D 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5= =0D - VERSION_STRING =3D 1.0=0D - MODULE_TYPE =3D BASE=0D - LIBRARY_CLASS =3D NULL=0D - CONSTRUCTOR =3D SmmKabylakeRvp3MultiBoardAcpiSupportL= ibConstructor=0D -=0D -#=0D -# The following information is for reference only and not required by the = build tools.=0D -#=0D -# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D -#=0D -=0D -[LibraryClasses]=0D - BaseLib=0D - IoLib=0D - PciLib=0D - MmPciLib=0D - PchCycleDecodingLib=0D -=0D -[Packages]=0D - MdePkg/MdePkg.dec=0D - MdeModulePkg/MdeModulePkg.dec=0D - MinPlatformPkg/MinPlatformPkg.dec=0D - KabylakeOpenBoardPkg/OpenBoardPkg.dec=0D - KabylakeSiliconPkg/SiPkg.dec=0D -=0D -[Pcd]=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUME= S=0D -=0D -[Protocols]=0D -=0D -[Sources]=0D - SmmKabylakeRvp3AcpiEnableLib.c=0D - SmmSiliconAcpiEnableLib.c=0D - SmmMultiBoardAcpiSupportLib.c=0D -=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/KabylakeOpenBoardPk= g/AspireVn7Dash572G/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c index 7f63a12bf461..ca7e1326347e 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/SmmSiliconAcpiEnableLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/SmmSiliconAcpiEnableLib.c @@ -7,11 +7,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/=0D =0D #include =0D -#include =0D #include =0D #include =0D #include =0D -#include =0D #include =0D #include =0D #include =0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardEcLib/BoardEcLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Da= sh572G/Library/BoardEcLib/BoardEcLib.inf new file mode 100644 index 000000000000..ffe6a64571a4 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEc= Lib/BoardEcLib.inf @@ -0,0 +1,28 @@ +## @file=0D +# Component information file for Aspire VN7-572G EC library=0D +#=0D +# Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D BoardEcLib=0D + FILE_GUID =3D 2406A521-A06B-4B48-ADBF-81E737771979= =0D + VERSION_STRING =3D 1.0=0D + MODULE_TYPE =3D BASE=0D + LIBRARY_CLASS =3D BoardEcLib=0D +=0D +[LibraryClasses]=0D + DebugLib=0D + EcLib=0D + IoLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + KabylakeOpenBoardPkg/OpenBoardPkg.dec=0D +=0D +[Sources]=0D + EcCommands.c=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardEcLib/EcCommands.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash= 572G/Library/BoardEcLib/EcCommands.c new file mode 100644 index 000000000000..85249b9f18cd --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEc= Lib/EcCommands.c @@ -0,0 +1,221 @@ +/** @file=0D + Board EC commands.=0D +=0D +Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/* TODO - Implement:=0D + * - Commands: 0x58, 0xE1 and 0xE2=0D + * - 0x51, 0x52: EC flash write?=0D + * - ACPI CMDB: 0x63 and 0x64, 0xC7=0D + * - 0x0B: Flash write (Boolean argument? Set in offset 0x0B?)=0D + *=0D + * NB: Consider that if UEFI driver consumes=0D + * unimplemented PPI/protocol, the driver is dead code.=0D + *=0D + * NOTE: Check protocol use.=0D + * - Commands delivered across modules=0D + * - EC writes also control behaviour=0D + */=0D +=0D +#define EC_INDEX_IO_PORT 0x1200=0D +#define EC_INDEX_IO_HIGH_ADDR_PORT EC_INDEX_IO_PORT+1=0D +#define EC_INDEX_IO_LOW_ADDR_PORT EC_INDEX_IO_PORT+2=0D +#define EC_INDEX_IO_DATA_PORT EC_INDEX_IO_PORT+3=0D +=0D +/**=0D + Reads a byte of EC RAM.=0D +=0D + @param[in] Address Address to read=0D + @param[out] Data Data received=0D +=0D + @retval EFI_SUCCESS Command success=0D + @retval EFI_DEVICE_ERROR Command error=0D + @retval EFI_TIMEOUT Command timeout=0D +**/=0D +EFI_STATUS=0D +EcCmd90Read (=0D + IN UINT8 Address,=0D + OUT UINT8 *Data=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + Status =3D SendEcCommand(0x90);=0D + if (EFI_ERROR(Status)) {=0D + DEBUG((DEBUG_ERROR, "%a(): SendEcCommand(0x90) failed!\n", __func__));= =0D + return Status;=0D + }=0D +=0D + Status =3D SendEcData(Address);=0D + if (EFI_ERROR(Status)) {=0D + DEBUG((DEBUG_ERROR, "%a(): SendEcData(Address) failed!\n", __func__));= =0D + return Status;=0D + }=0D +=0D + Status =3D ReceiveEcData(Data);=0D + if (EFI_ERROR(Status)) {=0D + DEBUG((DEBUG_ERROR, "%a(): ReceiveEcData(Data) failed!\n", __func__));= =0D + return Status;=0D + }=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Writes a byte of EC RAM.=0D +=0D + @param[in] Address Address to write=0D + @param[in] Data Data to write=0D +=0D + @retval EFI_SUCCESS Command success=0D + @retval EFI_DEVICE_ERROR Command error=0D + @retval EFI_TIMEOUT Command timeout=0D +**/=0D +EFI_STATUS=0D +EcCmd91Write (=0D + IN UINT8 Address,=0D + IN UINT8 Data=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + Status =3D SendEcCommand(0x91);=0D + if (EFI_ERROR(Status)) {=0D + DEBUG((DEBUG_ERROR, "%a(): SendEcCommand(0x91) failed!\n", __func__));= =0D + return Status;=0D + }=0D +=0D + Status =3D SendEcData(Address);=0D + if (EFI_ERROR(Status)) {=0D + DEBUG((DEBUG_ERROR, "%a(): SendEcData(Address) failed!\n", __func__));= =0D + return Status;=0D + }=0D +=0D + Status =3D SendEcData(Data);=0D + if (EFI_ERROR(Status)) {=0D + DEBUG((DEBUG_ERROR, "%a(): SendEcData(Data) failed!\n", __func__));=0D + return Status;=0D + }=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Query the EC status.=0D +=0D + @param[out] Status EC status byte=0D +=0D + @retval EFI_SUCCESS Command success=0D + @retval EFI_DEVICE_ERROR Command error=0D + @retval EFI_TIMEOUT Command timeout=0D +**/=0D +EFI_STATUS=0D +EcCmd94Query (=0D + OUT UINT8 *Data=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + Status =3D SendEcCommand(0x94);=0D + if (EFI_ERROR(Status)) {=0D + DEBUG((DEBUG_ERROR, "%a(): SendEcCommand(0x94) failed!\n", __func__));= =0D + return Status;=0D + }=0D +=0D + Status =3D ReceiveEcData(Data);=0D + if (EFI_ERROR(Status)) {=0D + DEBUG((DEBUG_ERROR, "%a(): ReceiveEcData(Data) failed!\n", __func__));= =0D + return Status;=0D + }=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Reads a byte of EC (index) RAM.=0D + TODO: Validate errors?=0D +=0D + @param[in] Address Address to read=0D + @param[out] Data Data received=0D +=0D + @retval EFI_SUCCESS Command success=0D + @retval EFI_DEVICE_ERROR Command error=0D + @retval EFI_TIMEOUT Command timeout=0D +**/=0D +VOID=0D +EcIdxRead (=0D + IN UINT16 Address,=0D + OUT UINT8 *Data=0D + )=0D +{=0D + IoWrite8(EC_INDEX_IO_HIGH_ADDR_PORT, Address >> 8);=0D + IoWrite8(EC_INDEX_IO_LOW_ADDR_PORT, Address);=0D + *Data =3D IoRead8(EC_INDEX_IO_DATA_PORT);=0D +}=0D +=0D +/**=0D + Writes a byte of EC (index) RAM.=0D + TODO: Validate errors?=0D +=0D + @param[in] Address Address to read=0D + @param[out] Data Data received=0D +=0D + @retval EFI_SUCCESS Command success=0D + @retval EFI_DEVICE_ERROR Command error=0D + @retval EFI_TIMEOUT Command timeout=0D +**/=0D +VOID=0D +EcIdxWrite (=0D + IN UINT16 Address,=0D + IN UINT8 Data=0D + )=0D +{=0D + IoWrite8(EC_INDEX_IO_HIGH_ADDR_PORT, Address >> 8);=0D + IoWrite8(EC_INDEX_IO_LOW_ADDR_PORT, Address);=0D + IoWrite8(EC_INDEX_IO_DATA_PORT, Data);=0D +}=0D +=0D +/**=0D + Read EC analog-digital converter.=0D +=0D + @param[out] DataBuffer=0D +=0D + @retval EFI_SUCCESS Command success=0D + @retval EFI_DEVICE_ERROR Command error=0D +**/=0D +EFI_STATUS=0D +ReadEcAdcConverter (=0D + IN UINT8 Adc,=0D + OUT UINT16 *DataBuffer=0D + )=0D +{=0D + UINT8 AdcConvertersEnabled; // Contains some ADCs and some D= ACs=0D + UINT8 IdxData;=0D +=0D + // Backup enabled ADCs=0D + EcIdxRead(0xff15, &AdcConvertersEnabled); // ADDAEN=0D +=0D + // Enable desired ADC in bitmask (not enabled by EC FW, not used by vend= or FW)=0D + EcIdxWrite(0xff15, AdcConvertersEnabled | ((1 << Adc) & 0xf)); // ADDAE= N=0D +=0D + // Sample the desired ADC in binary field; OR the start bit=0D + EcIdxWrite(0xff18, ((Adc << 1) & 0xf) | 1); // ADCTRL=0D +=0D + // Read the desired ADC=0D + EcIdxRead(0xff19, &IdxData); // ADCDAT=0D + *DataBuffer =3D (IdxData << 2);=0D + // Lower 2-bits of 10-bit ADC are in high bits of next register=0D + EcIdxRead(0xff1a, &IdxData); // ECIF=0D + *DataBuffer |=3D ((IdxData & 0xc0) >> 6);=0D +=0D + // Restore enabled ADCs=0D + EcIdxWrite(0xff15, AdcConvertersEnabled); // ADDAEN=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/AspireVn7Dash572GGpioTable.c b/Platform/Intel/KabylakeOpenBoar= dPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GGpioTable.c index 2439c6bc1edc..bbf6b75f4d9a 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/AspireVn7Dash572GGpioTable.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/AspireVn7Dash572GGpioTable.c @@ -1,381 +1,398 @@ /** @file=0D - GPIO definition table for KabylakeRvp3=0D + GPIO definition table for Acer Aspire VN7-572G=0D =0D Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D =0D -#ifndef _KABYLAKE_RVP3_GPIO_TABLE_H_=0D -#define _KABYLAKE_RVP3_GPIO_TABLE_H_=0D +#ifndef _ASPIRE_VN7_572G_GPIO_TABLE_H_=0D +#define _ASPIRE_VN7_572G_GPIO_TABLE_H_=0D =0D #include =0D +#include =0D #include =0D #include =0D -#include =0D -#include =0D =0D =0D #define END_OF_GPIO_TABLE 0xFFFFFFFF=0D =0D -GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] =3D=0D -{=0D -//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHo= stOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, Gp= ioTermNone}},//H_RCIN_N=0D -//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHo= stOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, Gp= ioTermWpd20K}},//LPC_AD0_ESPI_IO0=0D -//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHo= stOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, Gp= ioTermWpd20K}},//LPC_AD1_ESPI_IO1=0D -//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHo= stOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, Gp= ioTermWpd20K}},//LPC_AD2_ESPI_IO2=0D -//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHo= stOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, Gp= ioTermWpd20K}},//LPC_AD3_ESPI_IO3=0D -//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioH= ostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, G= pioTermNone}},//LPC_FRAME_ESPI_CS_N=0D -//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioH= ostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, G= pioTermNone}},//INT_SERIRQ=0D - {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S= 0ix_R_N=0D -// skip for PM_CLKRUN_N {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHos= tOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, Gpi= oTermNone}},//PM_CLKRUN_N=0D -//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, Gpi= oHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, = GpioTermWpd20K}},//LPC_CLK_ESPI_CLK=0D -// skip for PCH_CLK_PCI_TPM {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, Gpi= oHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, = GpioTermWpd20K}},//PCH_CLK_PCI_TPM=0D - {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermN= one}},//EC_HID_INTR=0D - {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone}},//M.2_WWAN_GN= SS_UART_RST_N=0D -//skip for SUS_PWR_ACK_R {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioH= ostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, G= pioTermNone}},//SUS_PWR_ACK_R=0D -//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, Gpi= oHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, = GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N=0D -//skip for SUSACK_R_N {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHost= OwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, Gpio= TermWpd20K}},//SUSACK_R_N=0D - {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_S= EL=0D - {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_E= N_N=0D - {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0= _SENSOR=0D - {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1= _SENSOR=0D - {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2= _SENSOR=0D - {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHU= B_IRQ=0D - {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_= N=0D - {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermN= one}},//FPS_DRDY=0D - {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_V= ID0=0D - {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_V= ID1=0D - {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALE= RTB=0D - {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermN= one}},//TCH_PAD_INTR_R_N=0D - {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KI= LL_N=0D - {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermN= one}},//M.2_BT_UART_WAKE_N=0D - // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_R= EQ_SLOT1_N=0D - // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_R= EQ_SLOT2_LAN_N=0D - // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_R= EQ_M.2_SSD_SLOT3_N=0D - // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_R= EQ_M.2_WIGIG_N=0D - // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_R= EQ_M.2_WLAN_N=0D - {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT= _PWR_GATEB=0D - {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_= S0_N=0D - {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_= N=0D - {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PN= L_PWREN=0D - // {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_N= FC_DFU, NOT OWNED BY BIOS=0D - {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv= , GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNo= ne}},//M.2_WLAN_WIFI_WAKE_N=0D - {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv= , GpioOutDefault, GpioIntEdge | GpioIntSci, GpioPlatformReset, GpioTermWpu= 20K}},//TBT_CIO_PLUG_EVENT_N=0D - {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv= , GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWp= u20K}},//PCH_SLOT1_WAKE_N=0D - {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSP= I1_CS_R1_N=0D - {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GS= PI1_CLK_R1=0D - {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GS= PI1_MISO_R1=0D - {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GS= PI1_MOSI_R1=0D - {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRE= TE_GNSS_RESET_N=0D - {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK= =0D - {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DA= TA=0D - {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_T= HRM_SNSR_ALERT_N=0D - {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK= =0D - {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DAT= A=0D - {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv= , GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWp= d20K}},//M.2_WIGIG_WAKE_N=0D - {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK= , OWNED BY ME=0D - {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_D= ATA, OWNED BY ME=0D - {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART0_RXD=0D - {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART0_TXD=0D - {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART0_RTS_N=0D - {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART0_CTS_N=0D - {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART1_ISH_UART1_RXD=0D - {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART1_ISH_UART1_TXD=0D - {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART1_ISH_UART1_RTS_N=0D - {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART1_ISH_UART1_CTS_N=0D - {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _I2C0_SDA=0D - {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _I2C0_SCL=0D - {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _I2C1_SDA=0D - {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _I2C1_SCL=0D - {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART2_RXD=0D - {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART2_TXD=0D - {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART2_RTS_N=0D - {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART2_CTS_N=0D - {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCH= PNL_CS_N=0D - {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCH= PNL_CLK=0D - {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCH= PNL_MISO=0D - {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCH= PNL_MOSI=0D - {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLA= SH_STROBE=0D - {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0= _SDA=0D - {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0= _SCL=0D - {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1= _SDA=0D - {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1= _SCL=0D - {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNo= ne}},//HOME_BTN=0D - {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNo= ne}},//SCREEN_LOCK_PCH=0D - {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNo= ne}},//VOL_UP_PCH=0D - {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNo= ne}},//VOL_DOWN_PCH=0D - {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART= 0_RXD_SML0B_DATA=0D - {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART= 0_TXD_SML0B_CLK=0D - {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART= 0_RTS_N=0D - {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART= 0_CTS_SML0B_ALERT_N=0D - {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK= _1=0D - {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DMIC_D= ATA_1=0D - {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK= _0=0D - {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DMIC_D= ATA_0=0D - {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCH= PNL_IO2=0D - {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCH= PNL_IO3=0D - {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK= =0D - {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv= , GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNo= ne}},//SPI_TPM_HDR_IRQ_N=0D - {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD= _PRSNT_N=0D - {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioT= ermNone}},//M.2_SSD_SATA2_PCIE3_DET_N=0D - {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_D= FU_N=0D - {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_= RESET=0D - {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PH= YSLP1_DIRECT_R=0D - // {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2= _PHYSLP2_M.2SSD_R, NOT OWNED BY BIOS=0D - {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA= _LED_N=0D - {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0= _WP1_OTG_N=0D - {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1= _WP4_N=0D - {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2= _WP2_WP3_WP5_R_N=0D - // {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn= , GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTer= mNone}},//PCH_NFC_IRQ, NOT OWNED BY BIOS=0D - {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD= _Q=0D - {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD= _Q=0D - {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv= , GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNon= e}},//SMC_EXTSMI_R_N=0D - {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv= , GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNo= ne}},//SMC_RUNTIME_SCI_R_N=0D - {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD= =0D - {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTR= L_CLK=0D - {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_C= TRL_DATA=0D - {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTR= L_CLK=0D - {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_C= TRL_DATA=0D - {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv= , GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermN= one}},//PCH_CODEC_IRQ=0D - {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PN= L_RST_N=0D - {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCL= K=0D - {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFR= M=0D - {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD= =0D - {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD= =0D - {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTer= mNone}},//SERIALIO_I2C2_SDA=0D - {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTer= mNone}},//SERIALIO_I2C2_SCL=0D - {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTer= mNone}},//SERIALIO_I2C3_SDA=0D - {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTer= mNone}},//SERIALIO_I2C3_SCL=0D - {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTer= mNone}},//SERIALIO_I2C4_SDA=0D - {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTer= mNone}},//SERIALIO_I2C4_SCL=0D - {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTer= mNone}},//SERIALIO_I2C5_ISH_12C2_SDA=0D - {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTer= mNone}},//SERIALIO_I2C5_ISH_12C2_SCL=0D - {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD= =0D - {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DAT= A0=0D - {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DAT= A1=0D - {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DAT= A2=0D - {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DAT= A3=0D - {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DAT= A4=0D - {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DAT= A5=0D - {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DAT= A6=0D - {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DAT= A7=0D - {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCL= K=0D - {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK= =0D - {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermN= one}},//PCH_M.2_WWAN_UIM_SIM_DET=0D - {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD=0D - {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0= =0D - {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1= =0D - {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2= =0D - {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3= =0D - {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB=0D - {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK=0D - {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP=0D - {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N= =0D - {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R=0D - {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},/= /LANWAKE_SMC_WAKE_SCI_N=0D - {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_= N=0D - {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N=0D - {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N=0D - {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N=0D - {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_IN= TRUDET_N=0D - {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK=0D - {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N= =0D - {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N=0D - {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENAB= LE=0D - {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of= Table=0D -};=0D =0D -UINT16 mGpioTableLpDdr3Rvp3Size =3D sizeof (mGpioTableLpDdr3Rvp3) / sizeof= (GPIO_INIT_CONFIG) - 1;=0D +/* TODO: Vendor configures many NC pads as _TERM_GPO. Why? */=0D +/* TODO: Clean-up=0D + * - On direction: Are some of these comments illusory? At least some pads= =0D + * are bidirectional on the other side of the GPIO.=0D + * - Then, finalise whitespace */=0D +/* NB: Do not reconfigure pads used by Optimus, their assertion state may = be lost */=0D =0D -GPIO_INIT_CONFIG mGpioTableKabyLakeYLpddr3Rvp3[] =3D=0D +GPIO_INIT_CONFIG mGpioTableAspireVn7Dash572G[] =3D=0D {=0D - { GPIO_SKL_LP_GPP_A12, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirNon= e, GpioOutDefault, GpioIntDis, GpioResumeReset, GpioTermNone } },//REALSENS= E_ISH_WAKE=0D - { GPIO_SKL_LP_GPP_A20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirNon= e, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone } },//IRIS_P= ROXI_INTR=0D - { GPIO_SKL_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut= , GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//M.2_WWAN_G= NSS_UART_RST_N=0D - { GPIO_SKL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,= GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNo= ne } },//SD_CARD_WAKE=0D - { GPIO_SKL_LP_GPP_D11, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirNon= e, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone } },//TYPEC_= P1_DCI_CLK=0D - { GPIO_SKL_LP_GPP_D12, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirNon= e, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone } },//TYPEC_= P1_DCI_DATA=0D -};=0D =0D -UINT16 mGpioTableKabyLakeYLpddr3Rvp3Size =3D sizeof (mGpioTableKabyLakeYLp= ddr3Rvp3) / sizeof (GPIO_INIT_CONFIG);=0D + /* ------- GPIO Community 0 ------- */=0D =0D -GPIO_INIT_CONFIG mGpioTableLpddr3Rvp3UcmcDevice[] =3D=0D -{=0D - { GPIO_SKL_LP_GPP_B0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone = } }, //GPP_B0=0D - { GPIO_SKL_LP_GPP_B1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone = } }, //GPP_B1=0D -};=0D + /* ------- GPIO Group GPP_A ------- */=0D + // RCIN# <=3D H_RCIN#=0D + { GPIO_SKL_LP_GPP_A0, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // LAD0 (ESPI_IO0) <=3D> LPC_AD_CPU_P0=0D + { GPIO_SKL_LP_GPP_A1, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNative } },=0D + // LAD1 (ESPI_IO1) <=3D> LPC_AD_CPU_P1=0D + { GPIO_SKL_LP_GPP_A2, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNative } },=0D + // LAD2 (ESPI_IO2) <=3D> LPC_AD_CPU_P2=0D + { GPIO_SKL_LP_GPP_A3, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNative } },=0D + // LAD3 (ESPI_IO3) <=3D> LPC_AD_CPU_P3=0D + { GPIO_SKL_LP_GPP_A4, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNative } },=0D + // LFRAME# (ESPI_CS#) =3D> LPC_FRAME#_CPU=0D + { GPIO_SKL_LP_GPP_A5, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // SERIRQ <=3D> INT_SERIRQ=0D + { GPIO_SKL_LP_GPP_A6, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // PIRQA# =3D PIRQA#=0D + { GPIO_SKL_LP_GPP_A7, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // CLKRUN# <=3D PM_CLKRUN#_EC=0D + { GPIO_SKL_LP_GPP_A8, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // CLKOUT_LPC0 (ESPI_CLK) <=3D LPC_CLK_CPU_P0=0D + { GPIO_SKL_LP_GPP_A9, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // CLKOUT_LPC1 <=3D LPC_CLK_CPU_P1=0D + { GPIO_SKL_LP_GPP_A10, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (PME#) // NC=0D + { GPIO_SKL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (SX_EXIT_HOLDOFF#/BM_BUSY#/ISH_GP6) <=3D GC6_FB_EN=0D + { GPIO_SKL_LP_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, Gp= ioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // SUSWARN#/SUSPWRDNACK =3D PM_SUSACK#=0D + { GPIO_SKL_LP_GPP_A13, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // SUS_STAT# (ESPI_RESET#) =3D> PM_SUS_STAT#=0D + { GPIO_SKL_LP_GPP_A14, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // SUS_ACK# =3D PM_SUSACK#=0D + { GPIO_SKL_LP_GPP_A15, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (SD_1P8_SEL) // NC=0D + { GPIO_SKL_LP_GPP_A16, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (SD_PWR_EN#/ISH_GP7) // NC=0D + { GPIO_SKL_LP_GPP_A17, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (ISH_GP0) =3D> GSENSOR_INT#=0D + { GPIO_SKL_LP_GPP_A18, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, Gp= ioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO (ISH_GP1) // NC=0D + { GPIO_SKL_LP_GPP_A19, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (ISH_GP3) // NC=0D + { GPIO_SKL_LP_GPP_A21, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (ISH_GP4) <=3D GPU_EVENT#=0D + { GPIO_SKL_LP_GPP_A22, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO (ISH_GP5) // NC=0D + { GPIO_SKL_LP_GPP_A23, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D =0D -UINT16 mGpioTableLpddr3Rvp3UcmcDeviceSize =3D sizeof (mGpioTableLpddr3Rvp3= UcmcDevice) / sizeof (GPIO_INIT_CONFIG);=0D + /* ------- GPIO Group GPP_B ------- */=0D + // CORE_VID0 // V0.85A_VID0=0D + { GPIO_SKL_LP_GPP_B0, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // CORE_VID1 // V0.85A_VID1=0D + { GPIO_SKL_LP_GPP_B1, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO (CPU_GP2) <=3D TP_IN#=0D + // TODO: APIC-routed pads don't have host owners?=0D + { GPIO_SKL_LP_GPP_B3, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, Gpi= oOutLow, GpioIntApic | GpioIntLevel, GpioHostDeepReset, GpioTermNone } },=0D + // SRCCLKREQ0# <=3D PEG_CLKREQ_CPU#=0D + { GPIO_SKL_LP_GPP_B5, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirNone= , GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // SRCCLKREQ1# <=3D LAN_CLKREQ_CPU#=0D + { GPIO_SKL_LP_GPP_B6, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirNone= , GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // SRCCLKREQ2# <=3D WLAN_CLKREQ_CPU#=0D + { GPIO_SKL_LP_GPP_B7, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirNone= , GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // SRCCLKREQ3# <=3D MSATA_CLKREQ_CPU#=0D + { GPIO_SKL_LP_GPP_B8, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirNone= , GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // SRCCLKREQ4# // SRCCLKREQ4# ("Remove TBT")=0D + { GPIO_SKL_LP_GPP_B9, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // SRCCLKREQ5# // SRCCLKREQ5#=0D + { GPIO_SKL_LP_GPP_B10, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO (EXT_PWR_GATE#) =3D EXT_PWR_GATE#=0D + { GPIO_SKL_LP_GPP_B11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (SLP_S0#) // NC=0D + { GPIO_SKL_LP_GPP_B12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // PLTRST# =3D> PLT_RST#=0D + { GPIO_SKL_LP_GPP_B13, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO (SPKR) =3D> HDA_SPKR (Strap - Top Swap Override)=0D + { GPIO_SKL_LP_GPP_B14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (GSPI0_CS#) =3D TOUCH_DET#=0D + { GPIO_SKL_LP_GPP_B15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO (GSPI0_CLK) // NC=0D + { GPIO_SKL_LP_GPP_B16, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO (GSPI0_MISO) // NC ("Remove TBT")=0D + { GPIO_SKL_LP_GPP_B17, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,= GpioOutLow, GpioIntSci | GpioIntEdge, GpioHostDeepReset, GpioTermWpd20K } = },=0D + // GPIO (GSPI0_MOSI) =3D> GPP_B18/GSPI0_MOSI (Strap - No reboot)=0D + { GPIO_SKL_LP_GPP_B18, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (GSPI1_CS#) =3D> RTC_DET#=0D + { GPIO_SKL_LP_GPP_B19, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, Gp= ioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO (GSPI1_CLK) <=3D PSW_CLR#=0D + { GPIO_SKL_LP_GPP_B20, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, Gp= ioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (GSPI1_MOSI) =3D> GPP_B22/GSPI1_MOSI (Strap - Boot BIOS strap)=0D + { GPIO_SKL_LP_GPP_B22, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (SML1ALERT#/PCHHOT#) =3D> GPP_B23 (Strap)=0D + { GPIO_SKL_LP_GPP_B23, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D =0D -GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3Touchpanel =3D=0D - {GPIO_SKL_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNo= ne}};=0D + /* ------- GPIO Community 1 ------- */=0D =0D -GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3SdhcSidebandCardDetect =3D=0D - {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntBothEdge, GpioHostDeepReset, GpioTermNone}}; //SD_C= DB D3=0D + /* ------- GPIO Group GPP_C ------- */=0D + // SMBCLK <=3D SMB_CLK=0D + { GPIO_SKL_LP_GPP_C0, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // SMBDATA =3D SMB_DATA=0D + { GPIO_SKL_LP_GPP_C1, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (SMBALERT#) =3D> GPP_C2 (Strap - TLS Confidentiality)=0D + { GPIO_SKL_LP_GPP_C2, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (SML0CLK) // NC=0D + { GPIO_SKL_LP_GPP_C3, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (SML0DATA) // NC=0D + { GPIO_SKL_LP_GPP_C4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (SML0ALERT#) // NC (Strap - eSPI or LPC)=0D + { GPIO_SKL_LP_GPP_C5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // RESERVED (SML1CLK) <=3D> SML1_CLK (KBC)=0D + // RESERVED (SML1DATA) <=3D> SML1_DATA (KBC)=0D + // GPIO (UART0_RXD) // NC=0D + { GPIO_SKL_LP_GPP_C8, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (UART0_TXD) // NC=0D + { GPIO_SKL_LP_GPP_C9, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (UART0_RTS#) // NC=0D + { GPIO_SKL_LP_GPP_C10, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (UART0_CTS#) // NC=0D + { GPIO_SKL_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (UART1_RXD/ISH_UART1_RXD) // NC=0D + { GPIO_SKL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (UART1_TXD/ISH_UART1_TXD) // NC=0D + { GPIO_SKL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (UART1_RTS#/ISH_UART1_RTS#) // NC=0D + { GPIO_SKL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (UART1_CTS#/ISH_UART1_CTS#) // NC=0D + { GPIO_SKL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // I2C0_SDA <=3D> I2C0_DATA_CPU (Touch Panel)=0D + { GPIO_SKL_LP_GPP_C16, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // I2C0_SCL <=3D> I2C0_CLK_CPU (Touch Panel)=0D + { GPIO_SKL_LP_GPP_C17, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // I2C1_SDA <=3D> I2C1_DATA_CPU (Touch Pad)=0D + { GPIO_SKL_LP_GPP_C18, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // I2C1_SCL <=3D> I2C1_CLK_CPU (Touch Pad)=0D + { GPIO_SKL_LP_GPP_C19, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // UART2_RXD =3D LPSS_UART2_RXD=0D + { GPIO_SKL_LP_GPP_C20, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // UART2_TXD =3D LPSS_UART2_TXD=0D + { GPIO_SKL_LP_GPP_C21, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // UART2_RTS# =3D LPSS_UART2_RTS#=0D + { GPIO_SKL_LP_GPP_C22, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // UART2_CTS# =3D LPSS_UART2_CTS#=0D + { GPIO_SKL_LP_GPP_C23, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D =0D -//IO Expander Table for SKL RVP7, RVP13 and RVP15=0D -IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[] =3D=0D -{=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_3.3_PWREN_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SNSR_HUB_DFU_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SATA_PWR_EN_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_RST_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WLAN_WAKE_CTRL_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //GFX_CRB_DET_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //MFG_MODE_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //FLIP_TO_TABLET_MODE_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_SLOT1_RST_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB3_CAM_PWREN_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD_TESTMODE_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //BIOS_REC_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //EINK_PWREN_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TBT_FORCE_PWR_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIFI_RST_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //DGPU_PRSNT_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB2_CAM_PWREN_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //IMAGING_DFU_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SW_GFX_PWERGD_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_WAKE_CTRL_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_RST_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TP_IOEXP1_P26=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TP_IOEXP1_P27=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_PWREN_IOEXP=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_DISABLE_IOEXP_N=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP4_PWREN_IOEXP=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_OTG_WP1_PWREN_IOEXP=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP2_WP3_WP5_PWREN_R_IOEXP=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_AUDIO_PWREN_IOEXP=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_GNSS_DISABLE_IOEXP_N=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED}/= /M.2_WIGIG_PWREN_IOEXP=0D -};=0D + /* ------- GPIO Group GPP_D ------- */=0D + // GPIO (SPI1_CS#) // NC=0D + { GPIO_SKL_LP_GPP_D0, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (SPI1_CLK) // NC=0D + { GPIO_SKL_LP_GPP_D1, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // SPI1_MISO // NC=0D + { GPIO_SKL_LP_GPP_D2, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // SPI1_MOSI // NC=0D + { GPIO_SKL_LP_GPP_D3, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO (FLASHTRIG) // NC=0D + { GPIO_SKL_LP_GPP_D4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (ISH_I2C0_SDA) // NC=0D + { GPIO_SKL_LP_GPP_D5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (ISH_I2C0_SCL) // NC=0D + { GPIO_SKL_LP_GPP_D6, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (ISH_I2C1_SDA) // NC=0D + { GPIO_SKL_LP_GPP_D7, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (ISH_I2C1_SCL) // NC=0D + { GPIO_SKL_LP_GPP_D8, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO // NC=0D + { GPIO_SKL_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, Gpi= oOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO =3D> TOUCH_S_RST#=0D + { GPIO_SKL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, Gp= ioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO // NC=0D + { GPIO_SKL_LP_GPP_D11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, Gp= ioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO // NC ("Remove TBT")=0D + { GPIO_SKL_LP_GPP_D12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, Gp= ioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO (ISH_UART0_RXD/SML0BDATA/I2C4B_SDA) // NC=0D + { GPIO_SKL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (ISH_UART0_TXD/SML0BCLK/I2C4B_SCL) // NC=0D + { GPIO_SKL_LP_GPP_D14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (ISH_UART0_RTS#) // NC=0D + { GPIO_SKL_LP_GPP_D15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (ISH_UART0_CTS#/SML0BALERT#) // NC=0D + { GPIO_SKL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (DMIC_CLK1) // NC=0D + { GPIO_SKL_LP_GPP_D17, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (DMIC_DATA1) // NC=0D + { GPIO_SKL_LP_GPP_D18, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // DMIC_CLK0 =3D> DMIC_CLK_CON_R=0D + { GPIO_SKL_LP_GPP_D19, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // DMIC_DATA0 =3D> DMIC_PCH_DATA=0D + { GPIO_SKL_LP_GPP_D20, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // SPI1_IO2 // NC=0D + { GPIO_SKL_LP_GPP_D21, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // SPI1_IO3 // NC=0D + { GPIO_SKL_LP_GPP_D22, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO (I2S_MCLK) // NC=0D + { GPIO_SKL_LP_GPP_D23, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D =0D -UINT16 mGpioTableIoExpanderSize =3D sizeof (mGpioTableIoExpander) / sizeof= (IO_EXPANDER_GPIO_CONFIG);=0D + /* ------- GPIO Group GPP_E ------- */=0D + // SATAXPCIE0 (SATAGP0) =3D SATAGP0=0D + { GPIO_SKL_LP_GPP_E0, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // SATAXPCIE1 (SATAGP1) // NC=0D + { GPIO_SKL_LP_GPP_E1, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // SATAXPCIE2 (SATAGP2) =3D SATAGP2=0D + { GPIO_SKL_LP_GPP_E2, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO (CPU_GP0) // NC=0D + { GPIO_SKL_LP_GPP_E3, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO (DEVSLP0) // NC ("Remove DEVSLP_PCH")=0D + { GPIO_SKL_LP_GPP_E4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (DEVSLP1) // NC=0D + { GPIO_SKL_LP_GPP_E5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (DEVSLP2) // NC=0D + { GPIO_SKL_LP_GPP_E6, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (CPU_GP1) <=3D TOUCH_INT#=0D + { GPIO_SKL_LP_GPP_E7, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, = GpioOutLow, GpioIntApic | GpioIntLevel, GpioHostDeepReset, GpioTermNone } }= ,=0D + // SATALED# =3D SATA_LED#=0D + { GPIO_SKL_LP_GPP_E8, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // USB2_OC0# =3D USB_OC#=0D + { GPIO_SKL_LP_GPP_E9, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // USB2_OC1# // USB_OC#=0D + { GPIO_SKL_LP_GPP_E10, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // USB2_OC2# // USB_OC#=0D + { GPIO_SKL_LP_GPP_E11, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // USB2_OC3# // USB_OC#=0D + { GPIO_SKL_LP_GPP_E12, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // DDPB_HPD0 <=3D DDI1_HDMI_HPD_CPU=0D + { GPIO_SKL_LP_GPP_E13, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // DDPC_HPD1 // NC ("Remove HPD")=0D + { GPIO_SKL_LP_GPP_E14, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO (DDPD_HPD2) <=3D EC_SMI#=0D + // FIXME: Vendor configures as _TERM_GPO. Why?=0D + { GPIO_SKL_LP_GPP_E15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,= GpioOutLow, GpioIntSmi | GpioIntLevel, GpioHostDeepReset, GpioTermNone } }= ,=0D + // GPIO (DDPE_HPD3) <=3D EC_SCI#=0D + { GPIO_SKL_LP_GPP_E16, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,= GpioOutLow, GpioIntSci | GpioIntLevel, GpioPlatformReset, GpioTermNone } }= ,=0D + // EDP_HPD <=3D eDP_HPD_CPU=0D + { GPIO_SKL_LP_GPP_E17, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // DDPB_CTRLCLK <=3D> DDI1_HDMI_CLK_CPU=0D + { GPIO_SKL_LP_GPP_E18, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // DDPB_CTRLDATA <=3D> DDI1_HDMI_DATA_CPU (Strap - Display Port B Detect= ed)=0D + { GPIO_SKL_LP_GPP_E19, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // DDPC_CTRLCLK // NC=0D + { GPIO_SKL_LP_GPP_E20, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // DDPC_CTRLDATA =3D> DDPC_CDA (Strap - Display Port C Detected)=0D + { GPIO_SKL_LP_GPP_E21, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO // NC=0D + // TODO: Vendor configures as _GPIO_BIDIRECT. Why?=0D + { GPIO_SKL_LP_GPP_E22, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO =3D> DDPD_CDA (Strap - Display Port D Detected)=0D + { GPIO_SKL_LP_GPP_E23, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D =0D -//IO Expander Table for KBL -Refresh=0D -IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeRDdr4[] =3D=0D -{=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_3.3_PWREN_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SNSR_HUB_DFU_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SATA_PWR_EN_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_RST_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WLAN_WAKE_CTRL_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //GFX_CRB_DET_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //MFG_MODE_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //FLIP_TO_TABLET_MODE_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_SLOT1_RST_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB3_CAM_PWREN_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD_TESTMODE_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //BIOS_REC_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //Unused pin=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TBT_FORCE_PWR_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIFI_RST_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RTD3_USB_PD1_PWR_EN=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB2_CAM_PWREN_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //IMAGING_DFU_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //HRESET_PD1_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_WAKE_CTRL_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_RST_IOEXP_N=0D - //{IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPAN= DER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED= },//M.2_WWAN_RST_CNTRL_R=0D - // We want the initial state to be high.=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_RST_CNTRL_R=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_WAKE_CTRL_R_N=0D - // Turn off WWAN power and will turn it on later.=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_PWREN_IOEXP=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_DISABLE_IOEXP_N=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP2_WP3_WP5_PWREN_R_IOEXP=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_AUDIO_PWREN_IOEXP=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_GNSS_DISABLE_IOEXP_N=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_PWREN_IOEXP=0D -};=0D -UINT16 mGpioTableIoExpanderSizeKabylakeRDdr4 =3D sizeof (mGpioTableIoExpan= derKabylakeRDdr4) / sizeof (IO_EXPANDER_GPIO_CONFIG);=0D + /* ------- GPIO Community 2 ------- */=0D =0D -//IO Expander Table for KBL -kc=0D -IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeKcDdr3[] =3D=0D -{=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_3.3_PWREN_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SNSR_HUB_DFU_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SATA_PWR_EN_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_RST_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WLAN_WAKE_CTRL_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //GFX_CRB_DET_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //MFG_MODE_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //FLIP_TO_TABLET_MODE_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_SLOT1_RST_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB3_CAM_PWREN_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD_TESTMODE_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //BIOS_REC_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //EINK_PWREN_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TBT_FORCE_PWR_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIFI_RST_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB2_CAM_PWREN_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //IMAGING_DFU_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_WAKE_CTRL_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_RST_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TP_IOEXP1_P26=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TP_IOEXP1_P27=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_PWREN_IOEXP=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_DISABLE_IOEXP_N=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP4_PWREN_IOEXP=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_OTG_WP1_PWREN_IOEXP=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP2_WP3_WP5_PWREN_R_IOEXP=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_AUDIO_PWREN_IOEXP=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_GNSS_DISABLE_IOEXP_N=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_PWREN_IOEXP=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //FPS_LOCK_N=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_FLEX_PWREN=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB_UART_SEL=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_DOCK_PWREN_IOEXP_R=0D + /* -------- GPIO Group GPD -------- */=0D + // GPIO (BATLOW#) =3D BATLOW=0D + { GPIO_SKL_LP_GPD0, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gpio= OutHigh, GpioIntDis, GpioDswReset, GpioTermWpd20K } },=0D + // ACPRESENT <=3D AC_PRESENT=0D + { GPIO_SKL_LP_GPD1, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut,= GpioOutLow, GpioIntDis, GpioDswReset, GpioTermNone } },=0D + // GPIO (LAN_WAKE#) =3D GPD2/LAN_WAKE#=0D + { GPIO_SKL_LP_GPD2, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gpio= OutHigh, GpioIntDis, GpioDswReset, GpioTermWpd20K } },=0D + // PWRBTN# <=3D PM_PWRBTN#=0D + { GPIO_SKL_LP_GPD3, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut,= GpioOutLow, GpioIntDis, GpioDswReset, GpioTermWpu20K } },=0D + // SLP_S3# =3D> PM_SLP_S3#=0D + { GPIO_SKL_LP_GPD4, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut,= GpioOutLow, GpioIntDis, GpioDswReset, GpioTermNone } },=0D + // SLP_S4# =3D> PM_SLP_S4#=0D + { GPIO_SKL_LP_GPD5, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut,= GpioOutLow, GpioIntDis, GpioDswReset, GpioTermNone } },=0D + // SLP_A# // NC=0D + { GPIO_SKL_LP_GPD6, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut,= GpioOutLow, GpioIntDis, GpioDswReset, GpioTermWpd20K } },=0D + // GPIO (RSVD#AT15) // NC=0D + { GPIO_SKL_LP_GPD7, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gpio= OutHigh, GpioIntDis, GpioDswReset, GpioTermWpd20K } },=0D + // SUSCLK =3D> SUS_CLK_CPU=0D + { GPIO_SKL_LP_GPD8, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut,= GpioOutLow, GpioIntDis, GpioDswReset, GpioTermNone } },=0D + // SLP_WLAN# // NC=0D + { GPIO_SKL_LP_GPD9, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut,= GpioOutLow, GpioIntDis, GpioDswReset, GpioTermWpd20K } },=0D + // SLP_S5# // NC=0D + { GPIO_SKL_LP_GPD10, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut= , GpioOutLow, GpioIntDis, GpioDswReset, GpioTermWpd20K } },=0D + // GPIO (LANPHYPC) // NC=0D + { GPIO_SKL_LP_GPD11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gpi= oOutHigh, GpioIntDis, GpioDswReset, GpioTermWpd20K } },=0D +=0D + /* ------- GPIO Community 3 ------- */=0D +=0D + /* ------- GPIO Group GPP_F ------- */=0D + // GPIO (I2S2_SCLK) // NC=0D + { GPIO_SKL_LP_GPP_F0, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (I2S2_SFRM) // NC=0D + { GPIO_SKL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (I2S2_TXD) // NC=0D + { GPIO_SKL_LP_GPP_F2, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (I2S2_RXD) // NC=0D + { GPIO_SKL_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (I2C2_SDA) // NC=0D + { GPIO_SKL_LP_GPP_F4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (I2C2_SCL) // NC=0D + { GPIO_SKL_LP_GPP_F5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (I2C3_SDA) // NC=0D + { GPIO_SKL_LP_GPP_F6, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (I2C3_SCL) // NC=0D + { GPIO_SKL_LP_GPP_F7, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (I2C4_SDA) // NC=0D + { GPIO_SKL_LP_GPP_F8, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (I2C4_SCL) // NC=0D + { GPIO_SKL_LP_GPP_F9, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (I2C5_SDA/ISH_I2C2_SDA) // NC=0D + { GPIO_SKL_LP_GPP_F10, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (I2C5_SCL/ISH_I2C2_SCL) // NC=0D + { GPIO_SKL_LP_GPP_F11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (EMMC_CMD) // NC=0D + { GPIO_SKL_LP_GPP_F12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (EMMC_DATA0) // NC=0D + { GPIO_SKL_LP_GPP_F13, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (EMMC_DATA1) // NC=0D + { GPIO_SKL_LP_GPP_F14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (EMMC_DATA2) // NC=0D + { GPIO_SKL_LP_GPP_F15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (EMMC_DATA3) // NC=0D + { GPIO_SKL_LP_GPP_F16, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (EMMC_DATA4) // NC=0D + { GPIO_SKL_LP_GPP_F17, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (EMMC_DATA5) // NC=0D + { GPIO_SKL_LP_GPP_F18, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (EMMC_DATA6) // NC=0D + { GPIO_SKL_LP_GPP_F19, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (EMMC_DATA7) // NC=0D + { GPIO_SKL_LP_GPP_F20, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (EMMC_RCLK) // NC=0D + { GPIO_SKL_LP_GPP_F21, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (EMMC_CLK) // NC=0D + { GPIO_SKL_LP_GPP_F22, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, = GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO // NC=0D + { GPIO_SKL_LP_GPP_F23, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, Gp= ioOutLow, GpioIntApic | GpioIntLevel, GpioHostDeepReset, GpioTermNone } },= =0D +=0D + /* ------- GPIO Group GPP_G ------- */=0D + // GPIO (SD_CMD) // NC=0D + { GPIO_SKL_LP_GPP_G0, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (SD_DATA0) // NC=0D + { GPIO_SKL_LP_GPP_G1, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (SD_DATA1) // NC=0D + { GPIO_SKL_LP_GPP_G2, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (SD_DATA2) // NC=0D + { GPIO_SKL_LP_GPP_G3, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (SD_DATA3) // NC=0D + // TODO: Vendor configures as _GPO. Why?=0D + { GPIO_SKL_LP_GPP_G4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO (SD_CD#) // NC=0D + { GPIO_SKL_LP_GPP_G5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (SD_CLK) // NC=0D + { GPIO_SKL_LP_GPP_G6, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + // GPIO (SD_WP) // NC=0D + { GPIO_SKL_LP_GPP_G7, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirNone, G= pioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + //Marking End of Table=0D + { END_OF_GPIO_TABLE, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, Gp= ioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone} },=0D };=0D -UINT16 mGpioTableIoExpanderSizeKabylakeKcDdr3 =3D sizeof (mGpioTableIoExpa= nderKabylakeKcDdr3) / sizeof (IO_EXPANDER_GPIO_CONFIG);=0D -//IO Expander Table Full table for KBL RVP3=0D -IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeRvp3[] =3D=0D +=0D +UINT16 mGpioTableAspireVn7Dash572GSize =3D sizeof (mGpioTableAspireVn7Dash= 572G) / sizeof (GPIO_INIT_CONFIG) - 1;=0D +=0D +GPIO_INIT_CONFIG mGpioTableAspireVn7Dash572G_early[] =3D=0D {=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_3.3_PWREN_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SNSR_HUB_DFU_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SATA_PWR_EN_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_RST_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WLAN_WAKE_CTRL_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //GFX_CRB_DET_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //MFG_MODE_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //FLIP_TO_TABLET_MODE_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_SLOT1_RST_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB3_CAM_PWREN_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD_TESTMODE_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //BIOS_REC_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //EINK_PWREN_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TBT_FORCE_PWR_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIFI_RST_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //DGPU_PRSNT_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED }= ,//SW_GFX_DGPU_SEL (KBL_RVP3_BOARD)=0D -//{IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB2_CAM_PWREN_IOEXP (SKL_RVP3_BOARD)=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //IMAGING_DFU_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SW_GFX_PWERGD_IOEXP=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_WAKE_CTRL_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_RST_IOEXP_N=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TP_IOEXP1_P26=0D - {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TP_IOEXP1_P27=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_PWREN_IOEXP=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_DISABLE_IOEXP_N=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP4_PWREN_IOEXP=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED }= ,//Not Connected (KBK_RVP3_BOARD)=0D -//{IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_OTG_WP1_PWREN_IOEXP (SKL_RVP3_BOARD)=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP2_WP3_WP5_PWREN_R_IOEXP=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_AUDIO_PWREN_IOEXP=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_GNSS_DISABLE_IOEXP_N=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_PWREN_IOEXP=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB2_CAM_PWREN (KBL_RVP3_BOARD)=0D - {IO_EXPANDER_1, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //FPS_LOCK_N (KBL_RVP3_BOARD)=0D + // GPIO (ISH_GP2) =3D DGPU_PRESENT=0D + { GPIO_SKL_LP_GPP_A20, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, Gp= ioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO (VRALERT#) <=3D DGPU_PWROK=0D + { GPIO_SKL_LP_GPP_B2, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, Gpi= oOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO (CPU_GP3) =3D> DGPU_HOLD_RST#=0D + { GPIO_SKL_LP_GPP_B4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone } },=0D + // GPIO (GSPI1_MISO) =3D> DGPU_PWR_EN#=0D + { GPIO_SKL_LP_GPP_B21, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K } },=0D + //Marking End of Table=0D + { END_OF_GPIO_TABLE, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, Gp= ioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone} },=0D };=0D =0D -UINT16 mGpioTableIoExpanderKabylakeRvp3Size =3D sizeof (mGpioTableIoExpand= erKabylakeRvp3) / sizeof (IO_EXPANDER_GPIO_CONFIG);=0D +UINT16 mGpioTableAspireVn7Dash572G_earlySize =3D sizeof (mGpioTableAspireV= n7Dash572G_early) / sizeof (GPIO_INIT_CONFIG) - 1;=0D =0D -#endif // _KABYLAKE_RVP3_GPIO_TABLE_H_=0D +#endif // _ASPIRE_VN7_572G_GPIO_TABLE_H_=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/AspireVn7Dash572GHdaVerbTables.c b/Platform/Intel/KabylakeOpen= BoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GHdaVerbTab= les.c index 92afcbab0653..d13a8af09107 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/AspireVn7Dash572GHdaVerbTables.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/AspireVn7Dash572GHdaVerbTables.c @@ -1,232 +1,203 @@ /** @file=0D - HDA Verb table for KabylakeRvp3=0D + HDA Verb table for Acer Aspire VN7-572G=0D =0D Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D =0D -#ifndef _KABYLAKE_RVP3_HDA_VERB_TABLES_H_=0D -#define _KABYLAKE_RVP3_HDA_VERB_TABLES_H_=0D +#ifndef _ASPIRE_VN7_572G_HDA_VERB_TABLES_H_=0D +#define _ASPIRE_VN7_572G_HDA_VERB_TABLES_H_=0D =0D #include =0D =0D -HDAUDIO_VERB_TABLE HdaVerbTableAlc286Rvp3 =3D HDAUDIO_VERB_TABLE_INIT (=0D +HDAUDIO_VERB_TABLE HdaVerbTableAlc255AspireVn7Dash572G =3D HDAUDIO_VERB_TA= BLE_INIT (=0D //=0D - // VerbTable: (Realtek ALC286) for RVP3=0D + // VerbTable: (Realtek ALC255) for Aspire VN7-572G=0D // Revision ID =3D 0xff=0D // Codec Verb Table for SKL PCH boards=0D // Codec Address: CAd value (0/1/2)=0D - // Codec Vendor: 0x10EC0286=0D + // Codec Vendor: 0x10EC0255=0D //=0D - 0x10EC, 0x0286,=0D + 0x10EC, 0x0255,=0D 0xFF, 0xFF,=0D - //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=0D - //=0D - // Realtek Semiconductor Corp.=0D - //=0D - //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=0D =0D - //Realtek High Definition Audio Configuration - Version : 5.0.2.9=0D - //Realtek HD Audio Codec : ALC286=0D - //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086=0D - //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0286&SUBSYS_10EC108E=0D - //The number of verb command block : 16=0D -=0D - // NID 0x12 : 0x411111F0=0D - // NID 0x13 : 0x40000000=0D - // NID 0x14 : 0x9017011F=0D - // NID 0x17 : 0x90170110=0D - // NID 0x18 : 0x03A11040=0D + // The number of verb command block : 20=0D + // NID 0x12 : 0x411111C0=0D + // NID 0x14 : 0x90172120=0D + // NID 0x17 : 0x40000000=0D + // NID 0x18 : 0x411111F0=0D // NID 0x19 : 0x411111F0=0D // NID 0x1A : 0x411111F0=0D - // NID 0x1D : 0x4066A22D=0D + // NID 0x1B : 0x411111F0=0D + // NID 0x1D : 0x40700001=0D // NID 0x1E : 0x411111F0=0D - // NID 0x21 : 0x03211020=0D + // NID 0x21 : 0x02211030=0D =0D =0D + // Codec Address: Bits 31:28=0D + // Node ID: Bits 27:20=0D + // Verb ID: Bits 19:8 / Bits 19:16=0D + // Payload: Bits 7:0 / Bits 15:0=0D +=0D + //Widget node 0x01 : Reset Codec=0D + 0x0017FF00,=0D + 0x0017FF00,=0D + 0x0017FF00,=0D + 0x0017FF00,=0D +=0D //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D=0D - //HDA Codec Subsystem ID : 0x10EC108E=0D - 0x0017208E,=0D + //HDA Codec Subsystem ID : 0x10251037=0D + 0x00172037,=0D 0x00172110,=0D - 0x001722EC,=0D + 0x00172225,=0D 0x00172310,=0D =0D //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D=0D - //Widget node 0x01 :=0D - 0x0017FF00,=0D - 0x0017FF00,=0D - 0x0017FF00,=0D - 0x0017FF00,=0D - //Pin widget 0x12 - DMIC=0D - 0x01271CF0,=0D + //Pin widget 0x12=0D + 0x01271CC0,=0D 0x01271D11,=0D 0x01271E11,=0D 0x01271F41,=0D - //Pin widget 0x13 - DMIC=0D - 0x01371C00,=0D - 0x01371D00,=0D - 0x01371E00,=0D - 0x01371F40,=0D - //Pin widget 0x14 - SPEAKER-OUT (Port-D)=0D - 0x01771C1F,=0D - 0x01771D01,=0D - 0x01771E17,=0D - 0x01771F90,=0D - //Pin widget 0x17 - I2S-OUT=0D - 0x01771C10,=0D - 0x01771D01,=0D - 0x01771E17,=0D - 0x01771F90,=0D - //Pin widget 0x18 - MIC1 (Port-B)=0D - 0x01871C40,=0D - 0x01871D10,=0D - 0x01871EA1,=0D - 0x01871F03,=0D - //Pin widget 0x19 - I2S-IN=0D + //Pin widget 0x14 - Speaker=0D + 0x01471C20,=0D + 0x01471D21,=0D + 0x01471E17,=0D + 0x01471F90,=0D + //Pin widget 0x17=0D + 0x01771C00,=0D + 0x01771D00,=0D + 0x01771E00,=0D + 0x01771F40,=0D + //Pin widget 0x18 - NC=0D + 0x01871CF0,=0D + 0x01871D11,=0D + 0x01871E11,=0D + 0x01871F41,=0D + //Pin widget 0x19 - NC=0D 0x01971CF0,=0D 0x01971D11,=0D 0x01971E11,=0D 0x01971F41,=0D - //Pin widget 0x1A - LINE1 (Port-C)=0D + //Pin widget 0x1A - NC=0D 0x01A71CF0,=0D 0x01A71D11,=0D 0x01A71E11,=0D 0x01A71F41,=0D - //Pin widget 0x1D - PC-BEEP=0D - 0x01D71C2D,=0D - 0x01D71DA2,=0D - 0x01D71E66,=0D + //Pin widget 0x1B - NC=0D + 0x01B71CF0,=0D + 0x01B71D11,=0D + 0x01B71E11,=0D + 0x01B71F41,=0D + //Pin widget 0x1D=0D + 0x01D71C01,=0D + 0x01D71D00,=0D + 0x01D71E70,=0D 0x01D71F40,=0D - //Pin widget 0x1E - S/PDIF-OUT=0D + //Pin widget 0x1E - NC=0D 0x01E71CF0,=0D 0x01E71D11,=0D 0x01E71E11,=0D 0x01E71F41,=0D - //Pin widget 0x21 - HP-OUT (Port-A)=0D - 0x02171C20,=0D + //Pin widget 0x21 - Headphone=0D + 0x02171C30,=0D 0x02171D10,=0D 0x02171E21,=0D - 0x02171F03,=0D - //Widget node 0x20 :=0D - 0x02050071,=0D - 0x02040014,=0D - 0x02050010,=0D - 0x02040C22,=0D - //Widget node 0x20 - 1 :=0D - 0x0205004F,=0D - 0x02045029,=0D - 0x0205004F,=0D - 0x02045029,=0D - //Widget node 0x20 - 2 :=0D - 0x0205002B,=0D - 0x02040DD0,=0D - 0x0205002D,=0D - 0x02047020,=0D - //Widget node 0x20 - 3 :=0D - 0x0205000E,=0D - 0x02046C80,=0D - 0x01771F90,=0D - 0x01771F90,=0D - //TI AMP settings :=0D - 0x02050022,=0D - 0x0204004C,=0D - 0x02050023,=0D - 0x02040000,=0D - 0x02050025,=0D - 0x02040000,=0D - 0x02050026,=0D - 0x0204B010,=0D + 0x02171F02,=0D =0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D + /* See data blob in "InstallPchHdaVerbTablePei" of vendor firmware=0D + * (some appear in https://github.com/torvalds/linux/blob/master/sound/p= ci/hda/patch_realtek.c).=0D + * - Largely coefficient programming (undocumented): Select coeff; write= data=0D + * - Also programs speaker amplifier gain=0D + * - Sets speaker output=0D + * Note: NID 0x20 holds the "Realtek Defined Hidden registers" */=0D + 0x02050038, /* Set coeff idx: 0x38 */=0D + 0x02048981, /* Set processing coeff: 0x8981 */=0D + 0x02050045, /* Set coeff idx: 0x45 */=0D + 0x0204c489, /* Set processing coeff: 0xc489 */=0D =0D - 0x02050022,=0D - 0x0204004C,=0D - 0x02050023,=0D - 0x02040002,=0D - 0x02050025,=0D - 0x02040011,=0D - 0x02050026,=0D - 0x0204B010,=0D + 0x02050037, /* Set coeff idx: 0x37 */=0D + 0x02044a05, /* Set processing coeff: 0x4a05 */=0D + 0x05750003, /* Set coeff idx on NID 0x57?: 0x3 */=0D + 0x057486a6, /* Set processing coeff on NID 0x57?: 0x86a6 */=0D =0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D + 0x02050046, /* Set coeff idx: 0x46 */=0D + 0x02040004, /* Set processing coeff: 0x4 */=0D + 0x0205001b, /* Set coeff idx: 0x1b */=0D + 0x02040a0b, /* Set processing coeff: 0xa0b */=0D =0D - 0x02050022,=0D - 0x0204004C,=0D - 0x02050023,=0D - 0x0204000D,=0D - 0x02050025,=0D - 0x02040010,=0D - 0x02050026,=0D - 0x0204B010,=0D + 0x02050008, /* Set coeff idx: 0x8 */=0D + 0x02046a0c, /* Set processing coeff: 0x6a0c */=0D + 0x02050009, /* Set coeff idx: 0x9 */=0D + 0x0204e003, /* Set processing coeff: 0xe003 */=0D =0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D + 0x0205000a, /* Set coeff idx: 0xa */=0D + 0x02047770, /* Set processing coeff: 0x7770 */=0D + 0x02050040, /* Set coeff idx: 0x40 */=0D + 0x02049800, /* Set processing coeff: 0x9800 */=0D =0D - 0x02050022,=0D - 0x0204004C,=0D - 0x02050023,=0D - 0x02040025,=0D - 0x02050025,=0D - 0x02040008,=0D - 0x02050026,=0D - 0x0204B010,=0D + 0x02050010, /* Set coeff idx: 0x10 */=0D + 0x02040e20, /* Set processing coeff: 0xe20 */=0D + 0x0205000d, /* Set coeff idx: 0xd */=0D + 0x02042801, /* Set processing coeff: 0x2801 */=0D =0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D + 0x0143b000, /* Set amplifier gain on speaker: Set output, L+R amp; Unmu= ted; No gain */=0D + 0x0143b000, /* Repeated for units? */=0D + 0x01470740, /* Set widget control on speaker: Out enabled; VrefEn: Hi-Z= (disabled) */=0D + 0x01470740, /* Repeated for units? */=0D =0D - 0x02050022,=0D - 0x0204004C,=0D - 0x02050023,=0D - 0x02040002,=0D - 0x02050025,=0D - 0x02040000,=0D - 0x02050026,=0D - 0x0204B010,=0D + 0x01470740, /* Repeated for units? */=0D + 0x01470740, /* Repeated for units? */=0D + 0x02050010, /* Set coeff idx: 0x10 */=0D + 0x02040f20 /* Set processing coeff: 0xf20 */=0D +);=0D +=0D +HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio =3D HDAUDIO_VERB_TABLE_INIT (= =0D + //=0D + // VerbTable: Intel Skylake HDMI=0D + // Revision ID =3D 0xFF=0D + // Codec Vendor: 0x80862809=0D + // Subsystem ID: 0x80860101=0D + //=0D + 0x8086, 0x2809,=0D + 0xFF, 0xFF,=0D +=0D + // Codec Address: Bits 31:28=0D + // Node ID: Bits 27:20=0D + // Verb ID: Bits 19:8 / Bits 19:16=0D + // Payload: Bits 7:0 / Bits 15:0=0D =0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D - 0x000F0000,=0D + // Note: Corrected the table in vendor FW, codec address 0x2, not 0x0=0D =0D - 0x02050022,=0D - 0x0204004C,=0D - 0x02050023,=0D - 0x02040003,=0D - 0x02050025,=0D - 0x02040000,=0D - 0x02050026,=0D - 0x0204B010=0D + //=0D + // Display Audio Verb Table=0D + //=0D + // For GEN9, the Vendor Node ID is 08h=0D + // Enable the third converter and pin first=0D + 0x20878101,=0D + 0x20878101,=0D + 0x20878101,=0D + 0x20878101,=0D + // Pin Widget 5 - PORT B - Configuration Default: 0x18560010=0D + 0x20571C10,=0D + 0x20571D00,=0D + 0x20571E56,=0D + 0x20571F18,=0D + // Pin Widget 6 - PORT C - Configuration Default: 0x18560020=0D + 0x20671C20,=0D + 0x20671D00,=0D + 0x20671E56,=0D + 0x20671F18,=0D + // Pin Widget 7 - PORT D - Configuration Default: 0x18560030=0D + 0x20771C30,=0D + 0x20771D00,=0D + 0x20771E56,=0D + 0x20771F18,=0D + // Disable the third converter and third pin=0D + 0x20878100,=0D + 0x20878100,=0D + 0x20878100,=0D + 0x20878100=0D );=0D =0D -#endif // _KABYLAKE_RVP3_HDA_VERB_TABLES_H_=0D +#endif // _ASPIRE_VN7_572G_HDA_VERB_TABLES_H_=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/AspireVn7Dash572GHsioPtssTables.c b/Platform/Intel/KabylakeOpe= nBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GHsioPtssT= ables.c index 8a9048fa4c88..fb3ca713260b 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/AspireVn7Dash572GHsioPtssTables.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/AspireVn7Dash572GHsioPtssTables.c @@ -1,13 +1,13 @@ /** @file=0D - KabylakeRvp3 HSIO PTSS H File=0D + Aspire VN7-572G HSIO PTSS H File=0D =0D Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D =0D -#ifndef KABYLAKE_RVP3_HSIO_PTSS_H_=0D -#define KABYLAKE_RVP3_HSIO_PTSS_H_=0D +#ifndef ASPIRE_VN7_572G_HSIO_PTSS_H_=0D +#define ASPIRE_VN7_572G_HSIO_PTSS_H_=0D =0D #include =0D =0D @@ -15,91 +15,19 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define HSIO_PTSS_TABLE_SIZE(A) A##_Size =3D sizeof (A) / sizeof (HSIO_PTS= S_TABLES)=0D #endif=0D =0D -//BoardId KabylakeRvp3=0D -HSIO_PTSS_TABLES PchLpHsioPtss_Cx_KabylakeRvp3[] =3D {=0D - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoM2},=0D - {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0= 000}, PchPcieTopoM2},=0D - {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D - {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4},=0D - {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) ~0x3F0000= 00}, PchSataTopoDirectConnect},=0D - {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0= 000}, PchPcieTopoM2},=0D - {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D - {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4},=0D - {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D - {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4},=0D - {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D - {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D - {{12, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D - {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D - {{13, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D - {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D - {{14, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D - {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D - {{15, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D - {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4},=0D - {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopoM2},=0D - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopox1},=0D - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00322900, (UINT32) ~0x3F3F00}= , PchSataTopoM2},=0D - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00382C00, (UINT32) ~0x3F3F00}= , PchSataTopoDirectConnect},=0D - {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopoM2},=0D - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopox1},=0D - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D - {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D - {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D - {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown}=0D +//BoardId AspireVn7Dash572G=0D +HSIO_PTSS_TABLES PchLpHsioPtss_Cx_AspireVn7Dash572G[] =3D {=0D + /* PchSataHsioRxGen3EqBoostMag[1] =3D "1" */=0D + {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x01000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown}=0D };=0D =0D -UINT16 PchLpHsioPtss_Cx_KabylakeRvp3_Size =3D sizeof(PchLpHsioPtss_Cx_Kaby= lakeRvp3) / sizeof(HSIO_PTSS_TABLES);=0D +UINT16 PchLpHsioPtss_Cx_AspireVn7Dash572G_Size =3D sizeof(PchLpHsioPtss_Cx= _AspireVn7Dash572G) / sizeof(HSIO_PTSS_TABLES);=0D =0D -HSIO_PTSS_TABLES PchLpHsioPtss_Bx_KabylakeRvp3[] =3D {=0D - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchPcieTopoUnknown},=0D - {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D - {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D - {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4},=0D - {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) ~0x3F0000= 00}, PchSataTopoDirectConnect},=0D - {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D - {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D - {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4},=0D - {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D - {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4},=0D - {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D - {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D - {{12, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D - {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D - {{13, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D - {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D - {{14, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D - {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D - {{15, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D - {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4},=0D - {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopox1},=0D - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00322900, (UINT32) ~0x3F3F00}= , PchPcieTopoUnknown},=0D - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00382C00, (UINT32) ~0x3F3F00}= , PchSataTopoDirectConnect},=0D - {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopox1},=0D - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D - {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D - {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D - {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D +HSIO_PTSS_TABLES PchLpHsioPtss_Bx_AspireVn7Dash572G[] =3D {=0D + /* PchSataHsioRxGen3EqBoostMag[1] =3D "1" */=0D + {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x01000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown}=0D };=0D =0D -UINT16 PchLpHsioPtss_Bx_KabylakeRvp3_Size =3D sizeof(PchLpHsioPtss_Bx_Kaby= lakeRvp3) / sizeof(HSIO_PTSS_TABLES);=0D +UINT16 PchLpHsioPtss_Bx_AspireVn7Dash572G_Size =3D sizeof(PchLpHsioPtss_Bx= _AspireVn7Dash572G) / sizeof(HSIO_PTSS_TABLES);=0D =0D -#endif // KABYLAKE_RVP3_HSIO_PTSS_H_=0D +#endif // ASPIRE_VN7_572G_HSIO_PTSS_H_=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/AspireVn7Dash572GSpdTable.c b/Platform/Intel/KabylakeOpenBoard= Pkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GSpdTable.c deleted file mode 100644 index e4ad785bda20..000000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/AspireVn7Dash572GSpdTable.c +++ /dev/null @@ -1,541 +0,0 @@ -/** @file=0D - GPIO definition table for KabylakeRvp3=0D -=0D -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D -SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#ifndef _KABYLAKE_RVP3_SPD_TABLE_H_=0D -#define _KABYLAKE_RVP3_SPD_TABLE_H_=0D -=0D -//=0D -// DQByteMap[0] - ClkDQByteMap:=0D -// If clock is per rank, program to [0xFF, 0xFF]=0D -// If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]=0D -// If clock is shared by 2 ranks but does not go to all bytes,=0D -// Entry[i] defines which DQ bytes Group i services=0D -// DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is CmdN= /CAB=0D -// DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is CmdS= /CAB=0D -// DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE = /CAB=0D -// For DDR, DQByteMap[3:1] =3D [0xFF, 0]=0D -// DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we have= 1 CTL / rank=0D -// Variable only exists to make the code eas= ier to use=0D -// DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we have= 1 CA Vref=0D -// Variable only exists to make the code eas= ier to use=0D -//=0D -//=0D -// DQ byte mapping to CMD/CTL/CLK, from the CPU side - for SKL RVP3, SKL S= DS - used by SKL/KBL MRC=0D -//=0D -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqByteMapSklRvp3[2][6][2] =3D {= =0D - // Channel 0:=0D - {=0D - { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to p= ackage 1 - Bytes[7:4]=0D - { 0x00, 0xF0 }, // CmdN does not have CAA, CAB goes to Bytes[7:4]=0D - { 0x0F, 0xF0 }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[= 7:4]=0D - { 0x0F, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB=0D - { 0xFF, 0x00 }, // CTL (CS) goes to all bytes=0D - { 0xFF, 0x00 } // CA Vref is one for all bytes=0D - },=0D - // Channel 1:=0D - {=0D - { 0x33, 0xCC }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to p= ackage 1 - Bytes[7:4]=0D - { 0x00, 0xCC }, // CmdN does not have CAA, CAB goes to Bytes[7:4]=0D - { 0x33, 0xCC }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[= 7:4]=0D - { 0x33, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB=0D - { 0xFF, 0x00 }, // CTL (CS) goes to all bytes=0D - { 0xFF, 0x00 } // CA Vref is one for all bytes=0D - }=0D -};=0D -=0D -//=0D -// DQS byte swizzling between CPU and DRAM - for SKL DOE RVP=0D -//=0D -=0D -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqsMapCpu2DramSklRvp3[2][8] =3D= {=0D - { 0, 1, 3, 2, 4, 5, 6, 7 }, // Channel 0=0D - { 1, 0, 4, 5, 2, 3, 6, 7 } // Channel 1=0D -};=0D -=0D -// Samsung K4E6E304ED-EGCF 178b QDP LPDDR3, 4Gb die (256Mx16), x16=0D -// or Hynix H9CCNNNBLTALAR-NUD=0D -// or similar=0D -// 1867, 14-17-17-40=0D -// 2 ranks per channel, 2 SDRAMs per rank, 8x4Gb =3D 4GB total per channel= =0D -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp16Spd[] =3D {=0D - 0x24, ///< 0 Number of Serial PD Bytes= Written / SPD Device Size=0D - 0x20, ///< 1 SPD Revision=0D - 0x0F, ///< 2 DRAM Device Type=0D - 0x0E, ///< 3 Module Type=0D - 0x14, ///< 4 SDRAM Density and Banks: = 8 Banks, 4 Gb SDRAM density=0D - 0x12, ///< 5 SDRAM Addressing: 14 Rows= , 11 Columns=0D - 0xB5, ///< 6 SDRAM Package Type: QDP, = 1 Channel per die, Signal Loading Matrix 1=0D - 0x00, ///< 7 SDRAM Optional Features=0D - 0x00, ///< 8 SDRAM Thermal and Refresh= Options=0D - 0x00, ///< 9 Other SDRAM Optional Feat= ures=0D - 0x00, ///< 10 Reserved - must be coded = as 0x00=0D - 0x03, ///< 11 Module Nominal Voltage, V= DD=0D - 0x0A, ///< 12 Module Organization, SDRA= M width: 16 bits, 2 Ranks=0D - 0x23, ///< 13 Module Memory Bus Width: = 2 channels, 64 bit channel bus width=0D - 0x00, ///< 14 Module Thermal Sensor=0D - 0x00, ///< 15 Extended Module Type=0D - 0x00, ///< 16 Reserved - must be coded = as 0x00=0D - 0x00, ///< 17 Timebases=0D - 0x09, ///< 18 SDRAM Minimum Cycle Time = (tCKmin): tCKmin =3D 1.071ns (LPDDR3-1867)=0D - 0xFF, ///< 19 SDRAM Minimum Cycle Time = (tCKmax)=0D - 0xD4, ///< 20 CAS Latencies Supported, = First Byte (tCK): 14, 12, 10, 8=0D - 0x00, ///< 21 CAS Latencies Supported, = Second Byte=0D - 0x00, ///< 22 CAS Latencies Supported, = Third Byte=0D - 0x00, ///< 23 CAS Latencies Supported, = Fourth Byte=0D - 0x78, ///< 24 Minimum CAS Latency Time = (tAAmin) =3D 14.994 ns=0D - 0x00, ///< 25 Read and Write Latency Se= t Options=0D - 0x90, ///< 26 Minimum RAS# to CAS# Dela= y Time (tRCDmin)=0D - 0xA8, ///< 27 Minimum Row Precharge Del= ay Time for all banks (tRPab)=0D - 0x90, ///< 28 Minimum Row Precharge Del= ay Time per bank (tRPpb)=0D - 0x10, ///< 29 Minimum Refresh Recovery = Delay Time for all banks (tRFCab), Least Significant Byte=0D - 0x04, ///< 30 Minimum Refresh Recovery = Delay Time for all banks (tRFCab), Most Significant Byte=0D - 0xE0, ///< 31 Minimum Refresh Recovery = Delay Time for per bank (tRFCpb), Least Significant Byte=0D - 0x01, ///< 32 Minimum Refresh Recovery = Delay Time for per bank (tRFCpb), Most Significant Byte=0D - 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bi= t Mapping=0D - 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bi= t Mapping=0D - 0, 0, ///< 78 - 79=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119=0D - 0x00, ///< 120 Fine Offset for Minimum R= ow Precharge Delay Time per bank (tRPpb)=0D - 0x00, ///< 121 Fine Offset for Minimum R= ow Precharge Delay Time for all banks (tRPab)=0D - 0x00, ///< 122 Fine Offset for Minimum R= AS# to CAS# Delay Time (tRCDmin)=0D - 0xFA, ///< 123 Fine Offset for Minimum C= AS Latency Time (tAAmin): 14.994 ns (LPDDR3-1867)=0D - 0x7F, ///< 124 Fine Offset for SDRAM Min= imum Cycle Time (tCKmax): 32.002 ns=0D - 0xCA, ///< 125 Fine Offset for SDRAM Min= imum Cycle Time (tCKmin): 1.071 ns (LPDDR-1867)=0D - 0x00, ///< 126 CRC A=0D - 0x00, ///< 127 CRC B=0D - 0, 0, ///< 128 - 129=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319=0D - 0x00, ///< 320 Module Manufacturer ID Co= de, Least Significant Byte=0D - 0x00, ///< 321 Module Manufacturer ID Co= de, Most Significant Byte=0D - 0x00, ///< 322 Module Manufacturing Loca= tion=0D - 0x00, ///< 323 Module Manufacturing Date= Year=0D - 0x00, ///< 324 Module Manufacturing Date= Week=0D - 0x55, ///< 325 Module Serial Number A=0D - 0x00, ///< 326 Module Serial Number B=0D - 0x00, ///< 327 Module Serial Number C=0D - 0x00, ///< 328 Module Serial Number D=0D - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number:= Unused bytes coded as ASCII Blanks (0x20)=0D - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number= =0D - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number= =0D - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number= =0D - 0x00, ///< 349 Module Revision Code=0D - 0x00, ///< 350 DRAM Manufacturer ID Code= , Least Significant Byte=0D - 0x00, ///< 351 DRAM Manufacturer ID Code= , Most Significant Byte=0D - 0x00, ///< 352 DRAM Stepping=0D - 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509=0D - 0, 0 ///< 510 - 511=0D -};=0D -=0D -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp16SpdSize =3D sizeof= (mSkylakeRvp16Spd);=0D -=0D -//Hynix H9CCNNNBJTMLAR-NUD, DDP, LPDDR3, 8Gb die=0D -//1867=0D -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp3Spd110[] =3D {=0D - 0x91, ///< 0 Number of Serial PD Byt= es Written / SPD Device Size / CRC Coverage 1, 2=0D - 0x20, ///< 1 SPD Revision=0D - 0xF1, ///< 2 DRAM Device Type=0D - 0x03, ///< 3 Module Type=0D - 0x05, ///< 4 SDRAM Density and Banks= , 8Gb=0D - 0x19, ///< 5 SDRAM Addressing: 15 Ro= ws, 10 Columns=0D - 0x05, ///< 6 Module Nominal Voltage= =0D - 0x0B, ///< 7 Module Organization: 32= bits, 2 Ranks=0D - 0x03, ///< 8 Module Memory Bus Width= =0D - 0x11, ///< 9 Fine Timebase (FTB) Div= idend / Divisor=0D - 0x01, ///< 10 Medium Timebase (MTB) D= ividend=0D - 0x08, ///< 11 Medium Timebase (MTB) D= ivisor=0D - 0x09, ///< 12 SDRAM Minimum Cycle Tim= e (tCKmin): tCKmin =3D 1.071 ns (LPDDR3-1867)=0D - 0x00, ///< 13 Reserved0=0D - 0x50, ///< 14 CAS Latencies supported= (tCK): 14, 12, 10, 8 (LSB)=0D - 0x05, ///< 15 CAS Latencies supported= (tCK): 14, 12, 10, 8 (LSB)=0D - 0x78, ///< 16 Minimum CAS Latency (tA= Amin) =3D 14.994 ns=0D - 0x78, ///< 17 Minimum Write Recovery = Time (tWRmin)=0D - 0x90, ///< 18 Minimum RAS# to CAS# De= lay Time (tRCDmin)=0D - 0x50, ///< 19 Minimum Row Active to R= ow Active Delay Time (tRRDmin)=0D - 0x90, ///< 20 Minimum Row Precharge D= elay Time (tRPmin)=0D - 0x11, ///< 21 Upper Nibbles for tRAS = and tRC=0D - 0x50, ///< 22 Minimum Active to Prech= arge Delay Time (tRASmin), Least Significant Byte=0D - 0xE0, ///< 23 Minimum Active to Activ= e/Refresh Delay Time (tRCmin), Least Significant Byte=0D - 0x90, ///< 24 Minimum Refresh Recover= y Delay Time (tRFCmin), Least Significant Byte=0D - 0x06, ///< 25 Minimum Refresh Recover= y Delay Time (tRFCmin), Most Significant Byte=0D - 0x3C, ///< 26 Minimum Internal Write = to Read Command Delay Time (tWTRmin)=0D - 0x3C, ///< 27 Minimum Internal Read t= o Precharge Command Delay Time (tRTPmin)=0D - 0x01, ///< 28 Upper Nibble for tFAW=0D - 0x90, ///< 29 Minimum Four Activate W= indow Delay Time (tFAWmin)=0D - 0x00, ///< 30 SDRAM Optional Features= =0D - 0x00, ///< 31 SDRAMThermalAndRefreshO= ptions=0D - 0x00, ///< 32 ModuleThermalSensor=0D - 0x00, ///< 33 SDRAM Device Type=0D - 0xCA, ///< 34 Fine Offset for SDRAM M= inimum Cycle Time (tCKmin): 1.071 ns (LPDDR3-1867)=0D - 0xFA, ///< 35 Fine Offset for Minimum= CAS Latency Time (tAAmin): 14.994 ns (LPDDR3-1867)=0D - 0x00, ///< 36 Fine Offset for Minimum= RAS# to CAS# Delay Time (tRCDmin)=0D - 0x00, ///< 37 Fine Offset for Minimum= Row Precharge Delay Time (tRPmin)=0D - 0x00, ///< 38 Fine Offset for Minimum= Active to Active/Refresh Delay Time (tRCmin)=0D - 0xA8, ///< 39 Row precharge time for = all banks (tRPab)=0D - 0x00, ///< 40 FTB for Row precharge t= ime for all banks (tRPab)=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 41 - 49=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59=0D - 0, 0, ///< 60 - 61=0D - 0x00, ///< 62 Reference Raw Card Used= =0D - 0x00, ///< 63 Address Mapping from Ed= ge Connector to DRAM=0D - 0x00, ///< 64 ThermalHeatSpreaderSolu= tion=0D - 0, 0, 0, 0, 0, ///< 65 - 69=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109=0D - 0, 0, 0, 0, 0, 0, 0, ///< 110 - 116=0D - 0x00, ///< 117 Module Manufacturer ID = Code, Least Significant Byte=0D - 0x00, ///< 118 Module Manufacturer ID = Code, Most Significant Byte=0D - 0x00, ///< 119 Module Manufacturing Lo= cation=0D - 0x00, ///< 120 Module Manufacturing Da= te Year=0D - 0x00, ///< 121 Module Manufacturing Da= te creation work week=0D - 0x55, ///< 122 Module Serial Number A= =0D - 0x00, ///< 123 Module Serial Number B= =0D - 0x00, ///< 124 Module Serial Number C= =0D - 0x00, ///< 125 Module Serial Number D= =0D - 0x00, ///< 126 CRC A=0D - 0x00 ///< 127 CRC B=0D -};=0D -=0D -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp3Spd110Size =3D size= of (mSkylakeRvp3Spd110);=0D -=0D -//=0D -// Micron MT52L512M32D2PF 78b DDP LPDDR3, 8Gb die (256Mx32), x32=0D -//=0D -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mKblRSpdLpddr32133[] =3D {=0D - 0x91, ///< 0 128 SPD bytes used, 256= total, CRC covers 0..116=0D - 0x20, ///< 1 SPD Revision 2.0=0D - 0xF1, ///< 2 DRAM Type: LPDDR3 SDRAM= =0D - 0x03, ///< 3 Module Type: SO-DIMM=0D - 0x05, ///< 4 8 Banks, 8 Gb SDRAM den= sity=0D - 0x19, ///< 5 SDRAM Addressing: 15 Ro= ws, 10 Columns=0D - 0x05, ///< 6 Module Nominal Voltage = VDD: 1.2v=0D - 0x0B, ///< 7 SDRAM width: 32 bits, 2= Ranks=0D - 0x03, ///< 8 SDRAM bus width: 64 bit= s, no ECC=0D - 0x11, ///< 9 Fine Timebase (FTB) gra= nularity: 1 ps=0D - 0x01, ///< 10 Medium Timebase (MTB) := 0.125 ns=0D - 0x08, ///< 11 Medium Timebase Divisor= =0D - 0x08, ///< 12 tCKmin =3D 0.938 ns (LP= DDR3-2133)=0D - 0x00, ///< 13 Reserved=0D - 0x50, ///< 14 CAS Latencies supported= (tCK): 16, 14, 12, 10, 8 (LSB)=0D - 0x15, ///< 15 CAS Latencies supported= (tCK): 16, 14, 12, 10, 8 (MSB)=0D - 0x78, ///< 16 Minimum CAS Latency (tA= Amin) =3D 15.008 ns=0D - 0x78, ///< 17 tWR =3D 15 ns=0D - 0x90, ///< 18 Minimum RAS-to-CAS dela= y (tRCDmin) =3D 18 ns=0D - 0x50, ///< 19 tRRD =3D 10 ns=0D - 0x90, ///< 20 Minimum row precharge t= ime (tRPmin) =3D 18 ns=0D - 0x11, ///< 21 Upper nibbles for tRAS = and tRC=0D - 0x50, ///< 22 tRASmin =3D 42 ns=0D - 0xE0, ///< 23 tRCmin =3D (tRASmin + = tRPmin) =3D 60 ns=0D - 0x90, ///< 24 tRFCmin =3D (tRFCab) = =3D 210 ns (8Gb)=0D - 0x06, ///< 25 tRFCmin MSB=0D - 0x3C, ///< 26 tWTRmin =3D 7.5 ns=0D - 0x3C, ///< 27 tRTPmin =3D 7.5 ns=0D - 0x01, ///< 28 tFAWmin upper nibble=0D - 0x90, ///< 29 tFAWmin =3D 50 ns=0D - 0x00, ///< 30 SDRAM Optional Features= - none=0D - 0x00, ///< 31 SDRAM Thermal / Refresh= options - none=0D - 0x00, ///< 32 ModuleThermalSensor=0D - 0x00, ///< 33 SDRAM Device Type=0D - 0xC2, ///< 34 FTB for tCKmin =3D 0.93= 8 ns (LPDDR3-2133)=0D - 0x08, ///< 35 FTB for tAAmin =3D 15.0= 08 ns (LPDDR3-2133)=0D - 0x00, ///< 36 Fine Offset for Minimum= RAS# to CAS# Delay Time (tRCDmin)=0D - 0x00, ///< 37 Fine Offset for Minimum= Row Precharge Delay Time (tRPmin)=0D - 0x00, ///< 38 Fine Offset for Minimum= Active to Active/Refresh Delay Time (tRCmin)=0D - 0xA8, ///< 39 Row precharge time for = all banks (tRPab)=3D 21 ns=0D - 0x00, ///< 40 FTB for Row precharge t= ime for all banks (tRPab) =3D 0=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 41 - 49=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59=0D - 0, 0, ///< 60 - 61=0D - 0x00, ///< 62 Reference Raw Card Used= =0D - 0x00, ///< 63 Rank1 Mapping: Standard= =0D - 0x00, ///< 64 ThermalHeatSpreaderSolu= tion=0D - 0, 0, 0, 0, 0, ///< 65 - 69=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109=0D - 0, 0, 0, 0, 0, 0, 0, ///< 110 - 116=0D - 0x00, ///< 117 Module Manufacturer ID = Code, Least Significant Byte=0D - 0x00, ///< 118 Module Manufacturer ID = Code, Most Significant Byte=0D - 0x00, ///< 119 Module Manufacturing Lo= cation=0D - 0x00, ///< 120 Module Manufacturing Da= te Year=0D - 0x00, ///< 121 Module Manufacturing Da= te creation work week=0D - 0x55, ///< 122 Module ID: Module Seria= l Number=0D - 0x00, ///< 123 Module Serial Number B= =0D - 0x00, ///< 124 Module Serial Number C= =0D - 0x00, ///< 125 Module Serial Number D= =0D - 0x00, ///< 126 CRC A=0D - 0x00 ///< 127 CRC B=0D -};=0D -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mKblRSpdLpddr32133Size =3D size= of (mKblRSpdLpddr32133);=0D -=0D -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSpdLpddr32133[] =3D {=0D - 0x24, ///< 0 Number of Serial PD Bytes= Written / SPD Device Size=0D - 0x01, ///< 1 SPD Revision=0D - 0x0F, ///< 2 DRAM Device Type=0D - 0x0E, ///< 3 Module Type=0D - 0x15, ///< 4 SDRAM Density and Banks: = 8 Banks, 8 Gb SDRAM density=0D - 0x19, ///< 5 SDRAM Addressing: 15 Rows= , 10 Columns=0D - 0x90, ///< 6 SDRAM Package Type: QDP, = 1 Channel per die, Signal Loading Matrix 1=0D - 0x00, ///< 7 SDRAM Optional Features=0D - 0x00, ///< 8 SDRAM Thermal and Refresh= Options=0D - 0x00, ///< 9 Other SDRAM Optional Feat= ures=0D - 0x00, ///< 10 Reserved - must be coded = as 0x00=0D - 0x0B, ///< 11 Module Nominal Voltage, V= DD=0D - 0x0B, ///< 12 Module Organization, SDRA= M width: 32 bits, 2 Ranks=0D - 0x03, ///< 13 Module Memory Bus Width: = 2 channels, 64 bit channel bus width=0D - 0x00, ///< 14 Module Thermal Sensor=0D - 0x00, ///< 15 Extended Module Type=0D - 0x00, ///< 16 Reserved - must be coded = as 0x00=0D - 0x00, ///< 17 Timebases=0D - 0x08, ///< 18 SDRAM Minimum Cycle Time = (tCKmin)=0D - 0xFF, ///< 19 SDRAM Minimum Cycle Time = (tCKmax)=0D - 0xD4, ///< 20 CAS Latencies Supported, = First Byte=0D - 0x01, ///< 21 CAS Latencies Supported, = Second Byte=0D - 0x00, ///< 22 CAS Latencies Supported, = Third Byte=0D - 0x00, ///< 23 CAS Latencies Supported, = Fourth Byte=0D - 0x78, ///< 24 Minimum CAS Latency Time = (tAAmin)=0D - 0x00, ///< 25 Read and Write Latency Se= t Options=0D - 0x90, ///< 26 Minimum RAS# to CAS# Dela= y Time (tRCDmin)=0D - 0xA8, ///< 27 Minimum Row Precharge Del= ay Time for all banks (tRPab)=0D - 0x90, ///< 28 Minimum Row Precharge Del= ay Time per bank (tRPpb)=0D - 0x90, ///< 29 Minimum Refresh Recovery = Delay Time for all banks (tRFCab), Least Significant Byte=0D - 0x06, ///< 30 Minimum Refresh Recovery = Delay Time for all banks (tRFCab), Most Significant Byte=0D - 0xD0, ///< 31 Minimum Refresh Recovery = Delay Time for per bank (tRFCpb), Least Significant Byte=0D - 0x02, ///< 32 Minimum Refresh Recovery = Delay Time for per bank (tRFCpb), Most Significant Byte=0D - 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bi= t Mapping=0D - 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bi= t Mapping=0D - 0, 0, ///< 78 - 79=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119=0D - 0x00, ///< 120 Fine Offset for Minimum R= ow Precharge Delay Time per bank (tRPpb)=0D - 0x00, ///< 121 Fine Offset for Minimum R= ow Precharge Delay Time for all banks (tRPab)=0D - 0x00, ///< 122 Fine Offset for Minimum R= AS# to CAS# Delay Time (tRCDmin)=0D - 0x08, ///< 123 Fine Offset for Minimum C= AS Latency Time (tAAmin)=0D - 0x7F, ///< 124 Fine Offset for SDRAM Min= imum Cycle Time (tCKmax)=0D - 0xC2, ///< 125 Fine Offset for SDRAM Min= imum Cycle Time (tCKmin)=0D - 0x00, ///< 126 CRC A=0D - 0x00, ///< 127 CRC B=0D - 0, 0, ///< 128 - 129=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319=0D - 0x00, ///< 320 Module Manufacturer ID Co= de, Least Significant Byte=0D - 0x00, ///< 321 Module Manufacturer ID Co= de, Most Significant Byte=0D - 0x00, ///< 322 Module Manufacturing Loca= tion=0D - 0x00, ///< 323 Module Manufacturing Date= Year=0D - 0x00, ///< 324 Module Manufacturing Date= Week=0D - 0x55, ///< 325 Module Serial Number A=0D - 0x00, ///< 326 Module Serial Number B=0D - 0x00, ///< 327 Module Serial Number C=0D - 0x00, ///< 328 Module Serial Number D=0D - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number:= Unused bytes coded as ASCII Blanks (0x20)=0D - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number= =0D - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number= =0D - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number= =0D - 0x00, ///< 349 Module Revision Code=0D - 0x00, ///< 350 DRAM Manufacturer ID Code= , Least Significant Byte=0D - 0x00, ///< 351 DRAM Manufacturer ID Code= , Most Significant Byte=0D - 0x00, ///< 352 DRAM Stepping=0D - 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509=0D - 0, 0 ///< 510 - 511=0D -};=0D -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSpdLpddr32133Size =3D sizeof (= mSpdLpddr32133);=0D -=0D -/**=0D - Hynix H9CCNNN8JTMLAR-NTM_178b_DDP LPDDR3, 4Gb die (128Mx32), x32=0D - or Elpida EDF8132A1MC-GD-F=0D - or Samsung K4E8E304EB-EGCE=0D - 1600, 12-15-15-34=0D - 2 rank per channel, 2 SDRAMs per rank, 4x4Gb =3D 2GB total per channel=0D -**/=0D -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp3Spd[] =3D {=0D - 0x24, ///< 0 Number of Serial PD Bytes= Written / SPD Device Size=0D - 0x20, ///< 1 SPD Revision=0D - 0x0F, ///< 2 DRAM Device Type=0D - 0x0E, ///< 3 Module Type=0D - 0x14, ///< 4 SDRAM Density and Banks: = 8 Banks, 4 Gb SDRAM density=0D - 0x11, ///< 5 SDRAM Addressing: 14 Rows= , 10 Columns=0D - 0x95, ///< 6 SDRAM Package Type: DDP, = 1 Channel per die, Signal Loading Matrix 1=0D - 0x00, ///< 7 SDRAM Optional Features=0D - 0x00, ///< 8 SDRAM Thermal and Refresh= Options=0D - 0x00, ///< 9 Other SDRAM Optional Feat= ures=0D - 0x00, ///< 10 Reserved - must be coded = as 0x00=0D - 0x03, ///< 11 Module Nominal Voltage, V= DD=0D - 0x0B, ///< 12 Module Organization, SDRA= M width: 32 bits, 2 Ranks=0D - 0x23, ///< 13 Module Memory Bus Width: = 2 channels, 64 bit channel bus width=0D - 0x00, ///< 14 Module Thermal Sensor=0D - 0x00, ///< 15 Extended Module Type=0D - 0x00, ///< 16 Reserved - must be coded = as 0x00=0D - 0x00, ///< 17 Timebases=0D - 0x0A, ///< 18 SDRAM Minimum Cycle Time = (tCKmin)=0D - 0xFF, ///< 19 SDRAM Minimum Cycle Time = (tCKmax)=0D - 0x54, ///< 20 CAS Latencies Supported, = First Byte (tCk): 12 10 8=0D - 0x00, ///< 21 CAS Latencies Supported, = Second Byte=0D - 0x00, ///< 22 CAS Latencies Supported, = Third Byte=0D - 0x00, ///< 23 CAS Latencies Supported, = Fourth Byte=0D - 0x78, ///< 24 Minimum CAS Latency Time = (tAAmin)=0D - 0x00, ///< 25 Read and Write Latency Se= t Options=0D - 0x90, ///< 26 Minimum RAS# to CAS# Dela= y Time (tRCDmin)=0D - 0xA8, ///< 27 Minimum Row Precharge Del= ay Time for all banks (tRPab)=0D - 0x90, ///< 28 Minimum Row Precharge Del= ay Time per bank (tRPpb)=0D - 0x10, ///< 29 Minimum Refresh Recovery = Delay Time for all banks (tRFCab), Least Significant Byte=0D - 0x04, ///< 30 Minimum Refresh Recovery = Delay Time for all banks (tRFCab), Most Significant Byte=0D - 0xE0, ///< 31 Minimum Refresh Recovery = Delay Time for per bank (tRFCpb), Least Significant Byte=0D - 0x01, ///< 32 Minimum Refresh Recovery = Delay Time for per bank (tRFCpb), Most Significant Byte=0D - 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bi= t Mapping=0D - 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bi= t Mapping=0D - 0, 0, ///< 78 - 79=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119=0D - 0x00, ///< 120 Fine Offset for Minimum R= ow Precharge Delay Time per bank (tRPpb)=0D - 0x00, ///< 121 Fine Offset for Minimum R= ow Precharge Delay Time for all banks (tRPab)=0D - 0x00, ///< 122 Fine Offset for Minimum R= AS# to CAS# Delay Time (tRCDmin)=0D - 0x00, ///< 123 Fine Offset for Minimum C= AS Latency Time (tAAmin)=0D - 0x7F, ///< 124 Fine Offset for SDRAM Min= imum Cycle Time (tCKmax)=0D - 0x00, ///< 125 Fine Offset for SDRAM Min= imum Cycle Time (tCKmin)=0D - 0x00, ///< 126 CRC A=0D - 0x00, ///< 127 CRC B=0D - 0, 0, ///< 128 - 129=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319=0D - 0x00, ///< 320 Module Manufacturer ID Co= de, Least Significant Byte=0D - 0x00, ///< 321 Module Manufacturer ID Co= de, Most Significant Byte=0D - 0x00, ///< 322 Module Manufacturing Loca= tion=0D - 0x00, ///< 323 Module Manufacturing Date= Year=0D - 0x00, ///< 324 Module Manufacturing Date= Week=0D - 0x55, ///< 325 Module Serial Number A=0D - 0x00, ///< 326 Module Serial Number B=0D - 0x00, ///< 327 Module Serial Number C=0D - 0x00, ///< 328 Module Serial Number D=0D - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number:= Unused bytes coded as ASCII Blanks (0x20)=0D - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number= =0D - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number= =0D - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number= =0D - 0x00, ///< 349 Module Revision Code=0D - 0x00, ///< 350 DRAM Manufacturer ID Code= , Least Significant Byte=0D - 0x00, ///< 351 DRAM Manufacturer ID Code= , Most Significant Byte=0D - 0x00, ///< 352 DRAM Stepping=0D - 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499=0D - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509=0D - 0, 0 ///< 510 - 511=0D -};=0D -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp3SpdSize =3D sizeof = (mSkylakeRvp3Spd);=0D -#endif // _KABYLAKE_RVP3_SPD_TABLE_H_=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiAspireVn7Dash572GDetect.c b/Platform/Intel/KabylakeOpenBoar= dPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GDetect.c index 429f4316dd64..14c1fbddf95a 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiAspireVn7Dash572GDetect.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiAspireVn7Dash572GDetect.c @@ -6,64 +6,21 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/=0D =0D #include =0D -#include =0D +#include "PeiAspireVn7Dash572GInitLib.h"=0D +#include =0D #include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -=0D -#include "PeiKabylakeRvp3InitLib.h"=0D -=0D -#include =0D -#include =0D -#include =0D -#include =0D -=0D -#define BOARD_ID_MASK_8BIT 0xff=0D -=0D -/**=0D - Get board fab ID.=0D -=0D - @param[out] DataBuffer=0D -=0D - @retval EFI_SUCCESS Command success=0D - @retval EFI_DEVICE_ERROR Command error=0D -**/=0D -EFI_STATUS=0D -GetBoardFabId (=0D - OUT UINT8 *DataBuffer=0D - )=0D -{=0D - UINT8 DataSize;=0D -=0D - //=0D - // For 'EC_C_FAB_ID' command NumberOfSendData =3D 0, NumberOfReceiveData= =3D2.=0D - //=0D - DataSize =3D 2;=0D - return (LpcEcInterface (EC_C_FAB_ID, &DataSize, DataBuffer));=0D -}=0D +#define ADC_3V_10BIT_GRANULARITY_MAX (3005/1023)=0D +#define PCB_VER_AD 1=0D +#define MODEL_ID_AD 3=0D =0D /**=0D - Get RVP3 board ID.=0D - There are 2 different RVP3 boards having different ID.=0D + Get Aspire V Nitro (Skylake) board ID.=0D + There are 2 different boards having different ID.=0D This function will return board ID to caller.=0D + TODO: Newgate board is not supported. PCH differs,=0D + user should not attempt to flash such a board=0D + at this time.=0D =0D @param[out] DataBuffer=0D =0D @@ -71,35 +28,39 @@ GetBoardFabId ( @retval EFI_DEVICE_ERROR Command error=0D **/=0D EFI_STATUS=0D -GetRvp3BoardId (=0D - UINT8 *BoardId=0D +GetAspireVn7Dash572GBoardId (=0D + OUT UINT8 *BoardId=0D )=0D {=0D EFI_STATUS Status;=0D - UINT16 EcBoardInfo;=0D - UINT8 DataBuffer[2];=0D + UINT16 DataBuffer;=0D =0D - Status =3D GetBoardFabId (DataBuffer);=0D + Status =3D ReadEcAdcConverter (MODEL_ID_AD, &DataBuffer);=0D if (Status =3D=3D EFI_SUCCESS) {=0D - EcBoardInfo =3D DataBuffer[0];=0D - EcBoardInfo =3D (EcBoardInfo << 8) | DataBuffer[1];=0D - //=0D - // Get the following data:=0D - // [7:0] - BOARD_IDx=0D - // [8] - GEN_ID=0D - // [11:9] - REV_FAB_IDx=0D - // [12] - TP_SPD_PRSNT=0D - // [15:13] - BOM_IDx=0D - //=0D - *BoardId =3D (UINT8) (EcBoardInfo & BOARD_ID_MASK_8BIT);=0D - DEBUG ((DEBUG_INFO, "BoardId =3D %X\n", *BoardId));=0D + DEBUG ((DEBUG_INFO, "BoardId (raw) =3D 0x%X\n", DataBuffer));=0D + // Board by max voltage range (of 10-bit, 3.005 V ADC)=0D + if (DataBuffer <=3D (1374/ADC_3V_10BIT_GRANULARITY_MAX)) {=0D + DEBUG ((DEBUG_ERROR, "BoardId is reserved?\n"));=0D + } else if (DataBuffer <=3D (2017/ADC_3V_10BIT_GRANULARITY_MAX)) {=0D + *BoardId =3D BoardIdNewgateSLx_dGPU;=0D + } else {=0D + *BoardId =3D BoardIdRayleighSLx_dGPU;=0D + }=0D + DEBUG ((DEBUG_INFO, "BoardId =3D 0x%X\n", *BoardId));=0D + } else {=0D + DEBUG ((DEBUG_ERROR, "Unable to detect BoardId!\n"));=0D + }=0D +=0D + Status =3D ReadEcAdcConverter (PCB_VER_AD, &DataBuffer);=0D + if (Status =3D=3D EFI_SUCCESS) {=0D + DEBUG ((DEBUG_INFO, "PCB version (raw) =3D 0x%X\n", DataBuffer));=0D }=0D return Status;=0D }=0D =0D EFI_STATUS=0D EFIAPI=0D -KabylakeRvp3BoardDetect (=0D +AspireVn7Dash572GBoardDetect (=0D VOID=0D )=0D {=0D @@ -109,14 +70,16 @@ KabylakeRvp3BoardDetect ( return EFI_SUCCESS;=0D }=0D =0D - DEBUG ((DEBUG_INFO, "KabylakeRvp3DetectionCallback\n"));=0D - if (GetRvp3BoardId (&BoardId) =3D=3D EFI_SUCCESS) {=0D - if (BoardId =3D=3D BoardIdKabyLakeYLpddr3Rvp3) {=0D - LibPcdSetSku (BoardIdKabyLakeYLpddr3Rvp3);=0D - ASSERT (LibPcdGetSku() =3D=3D BoardIdKabyLakeYLpddr3Rvp3);=0D - } else if (BoardId =3D=3D BoardIdSkylakeRvp3) {=0D - LibPcdSetSku (BoardIdSkylakeRvp3);=0D - ASSERT (LibPcdGetSku() =3D=3D BoardIdSkylakeRvp3);=0D + DEBUG ((DEBUG_INFO, "AspireVn7Dash572GDetectionCallback\n"));=0D + if (GetAspireVn7Dash572GBoardId (&BoardId) =3D=3D EFI_SUCCESS) {=0D + if (BoardId =3D=3D BoardIdRayleighSLx_dGPU) {=0D + LibPcdSetSku (BoardIdRayleighSLx_dGPU);=0D + ASSERT (LibPcdGetSku() =3D=3D BoardIdRayleighSLx_dGPU);=0D + } else if (BoardId =3D=3D BoardIdNewgateSLx_dGPU) {=0D + // TODO: Newgate is the "Black Edition" (VN7-792G). It uses PCH-H,=0D + // should we forcibly halt execution here?=0D + LibPcdSetSku (BoardIdNewgateSLx_dGPU);=0D + ASSERT (LibPcdGetSku() =3D=3D BoardIdNewgateSLx_dGPU);=0D }=0D DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));=0D }=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiAspireVn7Dash572GInitLib.h b/Platform/Intel/KabylakeOpenBoa= rdPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitLib.h index 5b2ccf6b0dea..100572870690 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiAspireVn7Dash572GInitLib.h +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiAspireVn7Dash572GInitLib.h @@ -5,8 +5,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =0D **/=0D =0D -#ifndef _PEI_KABYLAKE_RVP3_BOARD_INIT_LIB_H_=0D -#define _PEI_KABYLAKE_RVP3_BOARD_INIT_LIB_H_=0D +#ifndef _PEI_ASPIRE_VN7_572G_BOARD_INIT_LIB_H_=0D +#define _PEI_ASPIRE_VN7_572G_BOARD_INIT_LIB_H_=0D =0D #include =0D #include =0D @@ -16,29 +16,20 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =0D #include =0D #include =0D -#include =0D =0D #include =0D =0D -extern const UINT8 mDqByteMapSklRvp3[2][6][2];=0D -extern const UINT8 mDqsMapCpu2DramSklRvp3[2][8];=0D -extern const UINT8 mSkylakeRvp3Spd110[];=0D -extern const UINT16 mSkylakeRvp3Spd110Size;=0D -extern const UINT8 mSkylakeRvp3Spd[];=0D -extern const UINT16 mSkylakeRvp3SpdSize;=0D -extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_KabylakeRvp3[];=0D -extern UINT16 PchLpHsioPtss_Bx_KabylakeRvp3_Size;=0D -extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_KabylakeRvp3[];=0D -extern UINT16 PchLpHsioPtss_Cx_KabylakeRvp3_Size;=0D +extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_AspireVn7Dash572G[];=0D +extern UINT16 PchLpHsioPtss_Bx_AspireVn7Dash572G_Size;=0D +extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_AspireVn7Dash572G[];=0D +extern UINT16 PchLpHsioPtss_Cx_AspireVn7Dash572G_Size;=0D =0D -extern HDAUDIO_VERB_TABLE HdaVerbTableAlc286Rvp3;=0D -extern GPIO_INIT_CONFIG mGpioTableLpddr3Rvp3UcmcDevice[];=0D -extern UINT16 mGpioTableLpddr3Rvp3UcmcDeviceSize;=0D +extern HDAUDIO_VERB_TABLE HdaVerbTableAlc255AspireVn7Dash572G;=0D +extern HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio;=0D =0D -extern IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[];=0D -extern UINT16 mGpioTableIoExpanderSize;=0D -extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3Touchpanel;=0D -extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[];=0D -extern UINT16 mGpioTableLpDdr3Rvp3Size;=0D +extern GPIO_INIT_CONFIG mGpioTableAspireVn7Dash572G[];=0D +extern UINT16 mGpioTableAspireVn7Dash572GSize;=0D +extern GPIO_INIT_CONFIG mGpioTableAspireVn7Dash572G_early[];=0D +extern UINT16 mGpioTableAspireVn7Dash572G_earlySize;=0D =0D -#endif // _PEI_KABYLAKE_RVP3_BOARD_INIT_LIB_H_=0D +#endif // _PEI_ASPIRE_VN7_572G_BOARD_INIT_LIB_H_=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiAspireVn7Dash572GInitPostMemLib.c b/Platform/Intel/Kabylake= OpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GIni= tPostMemLib.c index 5d398ab6654e..44a108d9b7f2 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiAspireVn7Dash572GInitPostMemLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiAspireVn7Dash572GInitPostMemLib.c @@ -6,32 +6,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/=0D =0D #include =0D -#include =0D #include =0D -#include =0D -#include =0D -#include =0D +#include =0D #include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D #include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D #include =0D +#include =0D =0D -#include "PeiKabylakeRvp3InitLib.h"=0D +#include "PeiAspireVn7Dash572GInitLib.h"=0D =0D /**=0D - SkylaeA0Rvp3 board configuration init function for PEI post memory phase= .=0D + Aspire VN7-572G board configuration init function for PEI post memory ph= ase.=0D =0D PEI_BOARD_CONFIG_PCD_INIT=0D =0D @@ -42,23 +27,16 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/=0D EFI_STATUS=0D EFIAPI=0D -KabylakeRvp3Init (=0D +AspireVn7Dash572GInit (=0D VOID=0D )=0D {=0D - PcdSet32S (PcdHdaVerbTable, (UINTN) &HdaVerbTableAlc286Rvp3);=0D -=0D - //=0D - // Assign the GPIO table with pin configs to be used for UCMC=0D - //=0D - PcdSet32S (PcdBoardUcmcGpioTable, (UINTN)mGpioTableLpddr3Rvp3UcmcDevice)= ;=0D - PcdSet16S (PcdBoardUcmcGpioTableSize, mGpioTableLpddr3Rvp3UcmcDeviceSize= );=0D + PcdSet32S (PcdHdaVerbTable, (UINTN) &HdaVerbTableAlc255AspireVn7Dash572G= );=0D + PcdSet32S (PcdDisplayAudioHdaVerbTable, (UINTN) &HdaVerbTableDisplayAudi= o);=0D =0D return EFI_SUCCESS;=0D }=0D =0D -#define EXPANDERS 2 // = defines expander's quantity=0D -=0D /**=0D Configures GPIO=0D =0D @@ -81,105 +59,62 @@ ConfigureGpio ( DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));=0D }=0D =0D -VOID=0D -SetBit (=0D - IN OUT UINT32 *Value,=0D - IN UINT32 BitNumber,=0D - IN BOOLEAN NewBitValue=0D - )=0D -{=0D - if (NewBitValue) {=0D - *Value |=3D 1 << BitNumber;=0D - } else {=0D - *Value &=3D ~(1 << BitNumber);=0D - }=0D -}=0D -=0D -/**=0D - Configures IO Expander GPIO device=0D -=0D - @param[in] IOExpGpioDefinition Point to IO Expander Gpio table=0D - @param[in] IOExpGpioTableCount Number of Gpio table entries=0D -=0D -**/=0D -void=0D -ConfigureIoExpanderGpio (=0D - IN IO_EXPANDER_GPIO_CONFIG *IoExpGpioDefinition,=0D - IN UINT16 IoExpGpioTableCount=0D - )=0D -{=0D - UINT8 Index;=0D - UINT32 Direction[EXPANDERS] =3D {0x00FFFFFF, 0x00FFFFFF};=0D - UINT32 Level[EXPANDERS] =3D {0};=0D - UINT32 Polarity[EXPANDERS] =3D {0};=0D -=0D - // IoExpander {TCA6424A}=0D - DEBUG ((DEBUG_INFO, "IO Expander Configuration Start\n"));=0D - for (Index =3D 0; Index < IoExpGpioTableCount; Index++) { //Program IO= Expander as per the table defined in PeiPlatformHooklib.c=0D - SetBit(&Direction[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpG= pioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].Gpi= oDirection);=0D - SetBit(&Level[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGpioD= efinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].GpioLev= el);=0D - SetBit(&Polarity[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGp= ioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].Gpio= Inversion);=0D - }=0D - for (Index =3D 0; Index < EXPANDERS; Index++) {=0D - GpioExpBulkConfig(Index, Direction[Index], Polarity[Index], Level[Inde= x]);=0D - }=0D - DEBUG ((DEBUG_INFO, "IO Expander Configuration End\n"));=0D - return;=0D -}=0D -=0D -/**=0D - Configure GPIO behind IoExpander.=0D -=0D - @param[in] PeiServices General purpose services available to ever= y PEIM.=0D - @param[in] NotifyDescriptor=0D - @param[in] Interface=0D -=0D - @retval EFI_SUCCESS Operation success.=0D -**/=0D -VOID=0D -ExpanderGpioInit (=0D - VOID=0D - )=0D -{=0D - ConfigureIoExpanderGpio(mGpioTableIoExpander, mGpioTableIoExpanderSize);= =0D -}=0D -=0D -/**=0D - Configure single GPIO pad for touchpanel interrupt=0D -=0D -**/=0D -VOID=0D -TouchpanelGpioInit (=0D - VOID=0D - )=0D -{=0D - GPIO_INIT_CONFIG* TouchpanelPad;=0D - GPIO_PAD_OWN PadOwnVal;=0D -=0D - PadOwnVal =3D 0;=0D - TouchpanelPad =3D &mGpioTableLpDdr3Rvp3Touchpanel;=0D -=0D - GpioGetPadOwnership (TouchpanelPad->GpioPad, &PadOwnVal);=0D - if (PadOwnVal =3D=3D GpioPadOwnHost) {=0D - GpioConfigurePads (1, TouchpanelPad);=0D - }=0D -}=0D -=0D =0D /**=0D Configure GPIO=0D =0D **/=0D VOID=0D -GpioInit (=0D +GpioInitPostMem (=0D VOID=0D )=0D {=0D - ConfigureGpio (mGpioTableLpDdr3Rvp3, mGpioTableLpDdr3Rvp3Size);=0D + ConfigureGpio (mGpioTableAspireVn7Dash572G, mGpioTableAspireVn7Dash572GS= ize);=0D +}=0D =0D - TouchpanelGpioInit();=0D +VOID=0D +ec_fills_time (=0D + VOID=0D + )=0D +{=0D +#if 0=0D + struct rtc_time time;=0D + rtc_get(&time);=0D +=0D + u8 ec_time_byte;=0D + int ec_time =3D ((time.year << 26) + (time.mon << 22) + (time.mday << 17= )=0D + + (time.hour << 12) + (time.min << 6) + (time.sec)=0D + /* 16 years */=0D + - 0x40000000);=0D +=0D + printk(BIOS_DEBUG, "EC: reporting present time 0x%x\n", ec_time);=0D + send_ec_command(0xE0);=0D + for (int i =3D 0; i < 4; i++) {=0D + ec_time_byte =3D ec_time >> (i*sizeof(ec_time_byte));=0D + printk(BIOS_DEBUG, "EC: Sending 0x%x (iteration %d)\n", ec_time_byte, = i);=0D + send_ec_data(ec_time_byte);=0D + }=0D =0D - return;=0D + printk(BIOS_DEBUG, "EC: response 0x%x\n", recv_ec_data());=0D +#endif=0D +}=0D +=0D +/**=0D + Configure EC=0D + FIXME: Move to DXE phase library (RTC protocol available).=0D + Only use new module if required hook is unavailable.=0D +=0D +**/=0D +VOID=0D +EcInit (=0D + VOID=0D + )=0D +{=0D + UINT8 Dat;=0D + /* UEFI modules "notify" this protocol in RtKbcDriver */=0D + EcCmd90Read(0x79, &Dat);=0D + if (Dat & 1)=0D + ec_fills_time();=0D }=0D =0D =0D @@ -190,14 +125,14 @@ GpioInit ( **/=0D EFI_STATUS=0D EFIAPI=0D -KabylakeRvp3BoardInitBeforeSiliconInit (=0D +AspireVn7Dash572GBoardInitBeforeSiliconInit (=0D VOID=0D )=0D {=0D - KabylakeRvp3Init ();=0D + AspireVn7Dash572GInit ();=0D =0D - GpioInit ();=0D - ExpanderGpioInit ();=0D + GpioInitPostMem ();=0D + EcInit ();=0D =0D ///=0D /// Do Late PCH init=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c b/Platform/Intel/KabylakeO= penBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInit= PreMemLib.c index 8f2e03635687..ec9267b2fd43 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiAspireVn7Dash572GInitPreMemLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiAspireVn7Dash572GInitPreMemLib.c @@ -1,127 +1,53 @@ /** @file=0D =0D -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D =0D #include =0D -#include =0D +#include =0D #include =0D -#include =0D +#include =0D #include =0D -#include =0D #include =0D #include =0D -#include =0D -#include =0D -#include =0D +#include =0D +#include =0D +#include =0D +#include =0D =0D -#include =0D -#include =0D -#include =0D -#include =0D #include =0D #include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D +#include =0D +#include =0D =0D -#include "PeiKabylakeRvp3InitLib.h"=0D +#include "PeiAspireVn7Dash572GInitLib.h"=0D =0D #include =0D #include =0D =0D +#ifndef STALL_ONE_MILLI_SECOND=0D +#define STALL_ONE_MILLI_SECOND 1000=0D +#endif=0D +=0D //=0D -// Reference RCOMP resistors on motherboard - for SKL RVP1=0D +// Reference RCOMP resistors on motherboard - for Aspire VN7-572G=0D //=0D -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp1[SA_MRC_MAX= _RCOMP] =3D { 200, 81, 162 };=0D +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorAspireVn7Dash572G[= SA_MRC_MAX_RCOMP] =3D { 121, 80, 100 };=0D //=0D -// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for SK= L RVP1=0D +// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for As= pire VN7-572G=0D //=0D -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp1[SA_MRC_MAX_R= COMP_TARGETS] =3D { 100, 40, 40, 23, 40 };=0D -=0D -/**=0D - SkylaeA0Rvp3 board configuration init function for PEI pre-memory phase.= =0D -=0D - PEI_BOARD_CONFIG_PCD_INIT=0D -=0D - @param Content pointer to the buffer contain init information for boar= d init.=0D -=0D - @retval EFI_SUCCESS The function completed successfully.=0D - @retval EFI_INVALID_PARAMETER The parameter is NULL.=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -KabylakeRvp3InitPreMem (=0D - VOID=0D - )=0D -{=0D - PcdSet32S (PcdPcie0WakeGpioNo, 0);=0D - PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);=0D - PcdSet32S (PcdPcie0HoldRstGpioNo, 8);=0D - PcdSetBoolS (PcdPcie0HoldRstActive, TRUE);=0D - PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);=0D - PcdSet32S (PcdPcie0PwrEnableGpioNo, 16);=0D - PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);=0D -=0D - //=0D - // HSIO PTSS Table=0D - //=0D - PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_Bx_Kab= ylakeRvp3);=0D - PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_Kab= ylakeRvp3_Size);=0D - PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_Cx_Kab= ylakeRvp3);=0D - PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_Kab= ylakeRvp3_Size);=0D -=0D - //=0D - // DRAM related definition=0D - //=0D - PcdSet8S (PcdSaMiscUserBd, 5);=0D -=0D - PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapSklRvp3);=0D - PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapSklRvp3));=0D - PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramSklRvp3);=0D - PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramSklRvp3));=0D - PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorSklRvp1);=0D - PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetSklRvp1);=0D - //=0D - // Example policy for DIMM slots implementation boards:=0D - // 1. Assign Smbus address of DIMMs and SpdData will be updated later=0D - // by reading from DIMM SPD.=0D - // 2. No need to apply hardcoded SpdData buffers here for such board.=0D - // Example:=0D - // PcdMrcSpdAddressTable0 =3D 0xA0=0D - // PcdMrcSpdAddressTable1 =3D 0xA2=0D - // PcdMrcSpdAddressTable2 =3D 0xA4=0D - // PcdMrcSpdAddressTable3 =3D 0xA6=0D - // PcdMrcSpdData =3D 0=0D - // PcdMrcSpdDataSize =3D 0=0D - //=0D - // Kabylake RVP3 has 8GB Memory down implementation withouit SPD,=0D - // So assign all SpdAddress to 0 and apply static SpdData buffers:=0D - // PcdMrcSpdAddressTable0 =3D 0=0D - // PcdMrcSpdAddressTable1 =3D 0=0D - // PcdMrcSpdAddressTable2 =3D 0=0D - // PcdMrcSpdAddressTable3 =3D 0=0D - // PcdMrcSpdData =3D static data buffer=0D - // PcdMrcSpdDataSize =3D sizeof (static data buffer)=0D - //=0D - PcdSet8S (PcdMrcSpdAddressTable0, 0);=0D - PcdSet8S (PcdMrcSpdAddressTable1, 0);=0D - PcdSet8S (PcdMrcSpdAddressTable2, 0);=0D - PcdSet8S (PcdMrcSpdAddressTable3, 0);=0D - PcdSet32S (PcdMrcSpdData, (UINTN) mSkylakeRvp3Spd110);=0D - PcdSet16S (PcdMrcSpdDataSize, mSkylakeRvp3Spd110Size);=0D +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetAspireVn7Dash572G[SA= _MRC_MAX_RCOMP_TARGETS] =3D { 100, 40, 40, 23, 40 };=0D =0D - PcdSetBoolS (PcdIoExpanderPresent, TRUE);=0D -=0D - return EFI_SUCCESS;=0D -}=0D +//=0D +// dGPU power GPIO definitions=0D +#define DGPU_PRESENT GPIO_SKL_LP_GPP_A20 /* Active low */=0D +#define DGPU_HOLD_RST GPIO_SKL_LP_GPP_B4 /* Active low */=0D +#define DGPU_PWR_EN GPIO_SKL_LP_GPP_B21 /* Active low */=0D =0D /**=0D - SkylaeA0Rvp3 board configuration init function for PEI pre-memory phase.= =0D + Aspire VN7-572G board configuration init function for PEI pre-memory pha= se.=0D =0D PEI_BOARD_CONFIG_PCD_INIT=0D =0D @@ -132,37 +58,29 @@ KabylakeRvp3InitPreMem ( **/=0D EFI_STATUS=0D EFIAPI=0D -SkylakeRvp3InitPreMem (=0D +AspireVn7Dash572GInitPreMem (=0D VOID=0D )=0D {=0D - PcdSet32S (PcdPcie0WakeGpioNo, 0);=0D - PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);=0D - PcdSet32S (PcdPcie0HoldRstGpioNo, 8);=0D - PcdSetBoolS (PcdPcie0HoldRstActive, TRUE);=0D - PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);=0D - PcdSet32S (PcdPcie0PwrEnableGpioNo, 16);=0D - PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);=0D -=0D //=0D // HSIO PTSS Table=0D //=0D - PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_Bx_Kab= ylakeRvp3);=0D - PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_Kab= ylakeRvp3_Size);=0D - PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_Cx_Kab= ylakeRvp3);=0D - PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_Kab= ylakeRvp3_Size);=0D + PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_Bx_Asp= ireVn7Dash572G);=0D + PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_Asp= ireVn7Dash572G_Size);=0D + PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_Cx_Asp= ireVn7Dash572G);=0D + PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_Asp= ireVn7Dash572G_Size);=0D =0D //=0D // DRAM related definition=0D //=0D - PcdSet8S (PcdSaMiscUserBd, 5);=0D -=0D - PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapSklRvp3);=0D - PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapSklRvp3));=0D - PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramSklRvp3);=0D - PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramSklRvp3));=0D - PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorSklRvp1);=0D - PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetSklRvp1);=0D + PcdSet8S (PcdSaMiscUserBd, 5); // ULT/ULX/Mobile Halo=0D + PcdSet8S (PcdMrcCaVrefConfig, 2); // "VREF_CA to CH_A and VREF_DQ_B to = CH_B" - for DDR4 boards=0D + PcdSetBoolS (PcdMrcDqPinsInterleaved, TRUE);=0D +=0D + PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorAspireVn7Dash572G);= =0D + PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetAspireVn7Dash572G);=0D + // TODO: Sample policy will populate Dq/Dqs, we should override (but "0"= will cause=0D + // `if (Buffer)` to fail...)=0D //=0D // Example policy for DIMM slots implementation boards:=0D // 1. Assign Smbus address of DIMMs and SpdData will be updated later=0D @@ -176,29 +94,16 @@ SkylakeRvp3InitPreMem ( // PcdMrcSpdData =3D 0=0D // PcdMrcSpdDataSize =3D 0=0D //=0D - // Skylake RVP3 has 4GB Memory down implementation withouit SPD,=0D - // So assign all SpdAddress to 0 and apply static SpdData buffers:=0D - // PcdMrcSpdAddressTable0 =3D 0=0D - // PcdMrcSpdAddressTable1 =3D 0=0D - // PcdMrcSpdAddressTable2 =3D 0=0D - // PcdMrcSpdAddressTable3 =3D 0=0D - // PcdMrcSpdData =3D static data buffer=0D - // PcdMrcSpdDataSize =3D sizeof (static data buffer)=0D - //=0D - PcdSet8S (PcdMrcSpdAddressTable0, 0);=0D + PcdSet8S (PcdMrcSpdAddressTable0, 0xA0);=0D PcdSet8S (PcdMrcSpdAddressTable1, 0);=0D - PcdSet8S (PcdMrcSpdAddressTable2, 0);=0D + PcdSet8S (PcdMrcSpdAddressTable2, 0xA4);=0D PcdSet8S (PcdMrcSpdAddressTable3, 0);=0D - PcdSet32S (PcdMrcSpdData, (UINTN) mSkylakeRvp3Spd);=0D - PcdSet16S (PcdMrcSpdDataSize, mSkylakeRvp3SpdSize);=0D -=0D - PcdSetBoolS (PcdIoExpanderPresent, TRUE);=0D + PcdSet32S (PcdMrcSpdData, 0);=0D + PcdSet16S (PcdMrcSpdDataSize, 0);=0D =0D return EFI_SUCCESS;=0D }=0D =0D -#define SIO_RUNTIME_REG_BASE_ADDRESS 0x0680=0D -=0D /**=0D Configures GPIO.=0D =0D @@ -230,45 +135,100 @@ GpioInitPreMem ( VOID=0D )=0D {=0D - // ConfigureGpio ();=0D + ConfigureGpio (mGpioTableAspireVn7Dash572G_early, mGpioTableAspireVn7Das= h572G_earlySize);=0D }=0D =0D /**=0D - Configure Super IO.=0D + Init based on PeiOemModule. KbcPeim does not appear to be used.=0D + It implements commands also found in RtKbcDriver and SmmKbcDriver.=0D =0D **/=0D VOID=0D -SioInit (=0D +EcInit (=0D VOID=0D )=0D {=0D - //=0D - // Program and Enable Default Super IO Configuration Port Addresses and = range=0D - //=0D - PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x1= 0);=0D + EFI_BOOT_MODE BootMode;=0D + UINT8 PowerState;=0D + UINT8 OutData;=0D + UINT32 GpeSts;=0D =0D - //=0D - // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF;=0D - //=0D - PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F), 0x10);=0D + /* This is called via a "$FNC" in a PeiOemModule pointer table */=0D + IoWrite8(0x6C, 0x5A); // 6Ch is the EC sideband port=0D + PeiServicesGetBootMode(&BootMode);=0D + if (BootMode =3D=3D BOOT_ON_S3_RESUME) {=0D + /* "MLID" in LGMR-based memory map is equivalent to "ELID" in EC-based= =0D + * memory map. Vendor firmware accesses through LGMR; remapped */=0D + EcRead(0x70, &PowerState);=0D + if (!(PowerState & 2)) { // Lid is closed=0D + EcCmd90Read(0x0A, &OutData); // Code executed, do not remap=0D + if (!(OutData & 2))=0D + EcCmd91Write(0x0A, OutData | 2); // Code executed, do not remap=0D +=0D + /* TODO: Clear events and go back to sleep */=0D + // pmc_clear_pm1_status();=0D + /* Clear GPE0_STS[127:96] */=0D +// GpeSts =3D inl(ACPI_BASE_ADDRESS + GPE0_STS(3));=0D +// outl(GpeSts, ACPI_BASE_ADDRESS + GPE0_STS(3));=0D + /* TODO: Clear xHCI PM_CS[PME_Status] - 74h[15]? */=0D =0D - return;=0D +// pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S3 << SLP_TYP_SHIFT));=0D +// halt();=0D + }=0D + }=0D }=0D =0D /**=0D - Configues the IC2 Controller on which GPIO Expander Communicates.=0D - This Function is to enable the I2CGPIOExapanderLib to programm the Gpios= =0D - Complete intilization will be done in later Stage=0D + Initialises the dGPU.=0D =0D **/=0D VOID=0D -EFIAPI=0D -I2CGpioExpanderInitPreMem(=0D +DgpuPowerOn (=0D VOID=0D )=0D {=0D - ConfigureSerialIoController (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden= );=0D - SerialIoI2cGpioInit (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden, PchSer= ialIoIs33V);=0D + UINT32 OutputVal;=0D +=0D + GpioGetOutputValue(DGPU_PRESENT, &OutputVal);=0D + if (!OutputVal) {=0D + GpioSetOutputValue(DGPU_HOLD_RST, 0); // Assert dGPU_HOLD_RST#=0D + MicroSecondDelay(2 * STALL_ONE_MILLI_SECOND);=0D + GpioSetOutputValue(DGPU_PWR_EN, 0); // Assert dGPU_PWR_EN#=0D + MicroSecondDelay(7 * STALL_ONE_MILLI_SECOND);=0D + GpioSetOutputValue(DGPU_HOLD_RST, 1); // Deassert dGPU_HOLD_RST#=0D + MicroSecondDelay(30 * STALL_ONE_MILLI_SECOND);=0D + } else {=0D + GpioSetOutputValue(DGPU_HOLD_RST, 0); // Assert dGPU_HOLD_RST#=0D + GpioSetOutputValue(DGPU_PWR_EN, 1); // Deassert dGPU_PWR_EN#=0D + }=0D +}=0D +=0D +/**=0D + Configure LPC.=0D + TODO: Execute even earlier, so that EC (index) is available=0D + for the ADC reads in board detection (it seems to work)?=0D +=0D +**/=0D +VOID=0D +LpcInit (=0D + VOID=0D + )=0D +{=0D + //=0D + // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2E= h/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h.=0D + //=0D + PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));=0D + PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));=0D +=0D + //=0D + // Program and Enable EC (sideband) Port Addresses and range=0D + //=0D + PchLpcGenIoRangeSet (0x68, 0x08);=0D +=0D + //=0D + // Program and Enable EC (index) Port Addresses and range=0D + //=0D + PchLpcGenIoRangeSet (0x1200, 0x10);=0D }=0D =0D /**=0D @@ -278,37 +238,57 @@ I2CGpioExpanderInitPreMem( **/=0D EFI_STATUS=0D EFIAPI=0D -KabylakeRvp3BoardInitBeforeMemoryInit (=0D +AspireVn7Dash572GBoardInitBeforeMemoryInit (=0D VOID=0D )=0D {=0D - if (LibPcdGetSku () =3D=3D BoardIdKabyLakeYLpddr3Rvp3) {=0D - KabylakeRvp3InitPreMem ();=0D - } else if (LibPcdGetSku () =3D=3D BoardIdSkylakeRvp3) {=0D - SkylakeRvp3InitPreMem ();=0D - }=0D -=0D - //=0D - // Configures the I2CGpioExpander=0D - //=0D - if (PcdGetBool (PcdIoExpanderPresent)) {=0D - I2CGpioExpanderInitPreMem();=0D - }=0D + EFI_STATUS Status;=0D =0D + EcInit ();=0D GpioInitPreMem ();=0D - SioInit ();=0D - =0D + DgpuPowerOn ();=0D + AspireVn7Dash572GInitPreMem ();=0D +=0D + LpcInit ();=0D +=0D ///=0D /// Do basic PCH init=0D ///=0D SiliconInit ();=0D =0D + //=0D + // Install PCH RESET PPI and EFI RESET2 PeiService=0D + //=0D + Status =3D PchInitializeReset ();=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Configure GPIO and SIO before memory ready.=0D +=0D + @retval EFI_SUCCESS Operation success.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +AspireVn7Dash572GBoardInitAfterMemoryInit (=0D + VOID=0D + )=0D +{=0D + // BUGBUG: Workaround for a misbehaving system firmware not setting goId= le=0D + // - Based on prior investigation for coreboot, I suspect FSP=0D + if ((MmioRead32(0xFED40044) & PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE) =3D= =3D 0) {=0D + MmioWrite32(0xFED40040, PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE);=0D + }=0D +=0D + // TODO: Set-up LGMR=0D return EFI_SUCCESS;=0D }=0D =0D EFI_STATUS=0D EFIAPI=0D -KabylakeRvp3BoardDebugInit (=0D +AspireVn7Dash572GBoardDebugInit (=0D VOID=0D )=0D {=0D @@ -321,10 +301,29 @@ KabylakeRvp3BoardDebugInit ( =0D EFI_BOOT_MODE=0D EFIAPI=0D -KabylakeRvp3BoardBootModeDetect (=0D +AspireVn7Dash572GBoardBootModeDetect (=0D VOID=0D )=0D {=0D - return BOOT_WITH_FULL_CONFIGURATION;=0D + UINT16 ABase;=0D + UINT32 SleepType;=0D +=0D + PchAcpiBaseGet (&ABase);=0D + SleepType =3D IoRead32 (ABase + R_PCH_ACPI_PM1_CNT) & B_PCH_ACPI_PM1_CNT= _SLP_TYP;=0D +=0D + // TODO: Perform advanced detection (capsule/recovery)=0D + // - Also compare BOOT_WITH_FULL_CONFIGURATION, BOOT_WITH_MINIMAL_CONFIG= URATION,=0D + // BOOT_ASSUMING_NO_CONFIGURATION_CHANGES and BOOT_WITH_DEFAULT_SETTIN= GS=0D + // - If "IsFirstBoot" =3D 0, BOOT_ASSUMING_NO_CONFIGURATION_CHANGES?=0D + switch (SleepType) {=0D + case V_PCH_ACPI_PM1_CNT_S3:=0D + return BOOT_ON_S3_RESUME;=0D + case V_PCH_ACPI_PM1_CNT_S4:=0D + return BOOT_ON_S4_RESUME;=0D + case V_PCH_ACPI_PM1_CNT_S5:=0D + return BOOT_ON_S5_RESUME;=0D + default:=0D + return BOOT_WITH_FULL_CONFIGURATION;=0D + }=0D }=0D =0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiBoardInitPostMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg= /AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.c index 2e079a0387a5..86350e1ba8ac 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiBoardInitPostMemLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiBoardInitPostMemLib.c @@ -1,5 +1,5 @@ /** @file=0D - Kaby Lake RVP 3 Board Initialization Post-Memory library=0D + Aspire VN7-572G Board Initialization Post-Memory library=0D =0D Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D @@ -7,15 +7,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/=0D =0D #include =0D -#include =0D -#include =0D #include =0D -#include =0D -#include =0D =0D EFI_STATUS=0D EFIAPI=0D -KabylakeRvp3BoardInitBeforeSiliconInit (=0D +AspireVn7Dash572GBoardInitBeforeSiliconInit (=0D VOID=0D );=0D =0D @@ -25,8 +21,7 @@ BoardInitBeforeSiliconInit ( VOID=0D )=0D {=0D - KabylakeRvp3BoardInitBeforeSiliconInit ();=0D - return EFI_SUCCESS;=0D + return AspireVn7Dash572GBoardInitBeforeSiliconInit ();=0D }=0D =0D EFI_STATUS=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/KabylakeOpenBoardP= kg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.inf index bdf481b9805c..9d98c2277754 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiBoardInitPostMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiBoardInitPostMemLib.inf @@ -1,5 +1,5 @@ ## @file=0D -# Component information file for KabylakeRvp3InitLib in PEI post memory ph= ase.=0D +# Component information file for AspireVn7Dash572GInitLib in PEI post memo= ry phase.=0D #=0D # Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
=0D #=0D @@ -20,9 +20,10 @@ DebugLib=0D BaseMemoryLib=0D MemoryAllocationLib=0D - GpioExpanderLib=0D PcdLib=0D + GpioLib=0D SiliconInitLib=0D + BoardEcLib=0D =0D [Packages]=0D MinPlatformPkg/MinPlatformPkg.dec=0D @@ -33,9 +34,9 @@ IntelSiliconPkg/IntelSiliconPkg.dec=0D =0D [Sources]=0D - PeiKabylakeRvp3InitPostMemLib.c=0D - KabylakeRvp3GpioTable.c=0D - KabylakeRvp3HdaVerbTables.c=0D + PeiAspireVn7Dash572GInitPostMemLib.c=0D + AspireVn7Dash572GGpioTable.c=0D + AspireVn7Dash572GHdaVerbTables.c=0D PeiBoardInitPostMemLib.c=0D =0D [FixedPcd]=0D @@ -43,12 +44,6 @@ [Pcd]=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel=0D -=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize=0D =0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable=0D -=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDisplayAudioHdaVerbTable=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiBoardInitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/= AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.c index f5c695ecff86..495a150af587 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiBoardInitPreMemLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiBoardInitPreMemLib.c @@ -1,5 +1,5 @@ /** @file=0D - Kaby Lake RVP 3 Board Initialization Pre-Memory library=0D + Aspire VN7-572G Board Initialization Pre-Memory library=0D =0D Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D @@ -7,34 +7,35 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/=0D =0D #include =0D -#include =0D -#include =0D #include =0D -#include =0D -#include =0D -#include =0D =0D EFI_STATUS=0D EFIAPI=0D -KabylakeRvp3BoardDetect (=0D +AspireVn7Dash572GBoardDetect (=0D VOID=0D );=0D =0D EFI_BOOT_MODE=0D EFIAPI=0D -KabylakeRvp3BoardBootModeDetect (=0D +AspireVn7Dash572GBoardBootModeDetect (=0D VOID=0D );=0D =0D EFI_STATUS=0D EFIAPI=0D -KabylakeRvp3BoardDebugInit (=0D +AspireVn7Dash572GBoardDebugInit (=0D VOID=0D );=0D =0D EFI_STATUS=0D EFIAPI=0D -KabylakeRvp3BoardInitBeforeMemoryInit (=0D +AspireVn7Dash572GBoardInitBeforeMemoryInit (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +AspireVn7Dash572GBoardInitAfterMemoryInit (=0D VOID=0D );=0D =0D @@ -44,8 +45,7 @@ BoardDetect ( VOID=0D )=0D {=0D - KabylakeRvp3BoardDetect ();=0D - return EFI_SUCCESS;=0D + return AspireVn7Dash572GBoardDetect ();=0D }=0D =0D EFI_STATUS=0D @@ -54,8 +54,7 @@ BoardDebugInit ( VOID=0D )=0D {=0D - KabylakeRvp3BoardDebugInit ();=0D - return EFI_SUCCESS;=0D + return AspireVn7Dash572GBoardDebugInit ();=0D }=0D =0D EFI_BOOT_MODE=0D @@ -64,7 +63,7 @@ BoardBootModeDetect ( VOID=0D )=0D {=0D - return KabylakeRvp3BoardBootModeDetect ();=0D + return AspireVn7Dash572GBoardBootModeDetect ();=0D }=0D =0D EFI_STATUS=0D @@ -73,10 +72,7 @@ BoardInitBeforeMemoryInit ( VOID=0D )=0D {=0D - if ((LibPcdGetSku () =3D=3D BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSku= () =3D=3D BoardIdSkylakeRvp3)) {=0D - KabylakeRvp3BoardInitBeforeMemoryInit ();=0D - }=0D - return EFI_SUCCESS;=0D + return AspireVn7Dash572GBoardInitBeforeMemoryInit ();=0D }=0D =0D EFI_STATUS=0D @@ -85,7 +81,7 @@ BoardInitAfterMemoryInit ( VOID=0D )=0D {=0D - return EFI_SUCCESS;=0D + return AspireVn7Dash572GBoardInitAfterMemoryInit ();=0D }=0D =0D EFI_STATUS=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPk= g/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf index d0cdba666fa2..1b9892b52acc 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiBoardInitPreMemLib.inf @@ -1,7 +1,7 @@ ## @file=0D -# Component information file for PEI KabylakeRvp3 Board Init Pre-Mem Libra= ry=0D +# Component information file for PEI AspireVn7Dash572G Board Init Pre-Mem = Library=0D #=0D -# Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2017 - 2021 Intel Corporation. All rights reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -23,6 +23,13 @@ PcdLib=0D SiliconInitLib=0D EcLib=0D + BoardEcLib=0D + TimerLib=0D + PeiServicesLib=0D + PchCycleDecodingLib=0D + PchResetLib=0D + IoLib=0D + GpioLib=0D =0D [Packages]=0D MinPlatformPkg/MinPlatformPkg.dec=0D @@ -33,14 +40,15 @@ IntelSiliconPkg/IntelSiliconPkg.dec=0D =0D [Sources]=0D - PeiKabylakeRvp3Detect.c=0D - PeiKabylakeRvp3InitPreMemLib.c=0D - KabylakeRvp3HsioPtssTables.c=0D - KabylakeRvp3SpdTable.c=0D + PeiAspireVn7Dash572GDetect.c=0D + PeiAspireVn7Dash572GInitPreMemLib.c=0D + AspireVn7Dash572GGpioTable.c=0D + AspireVn7Dash572GHsioPtssTables.c=0D PeiBoardInitPreMemLib.c=0D =0D [Pcd]=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding=0D =0D # PCH-LP HSIO PTSS Table=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1=0D @@ -58,23 +66,10 @@ gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize=0D =0D - # PEG Reset By GPIO=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive=0D -=0D -=0D # SPD Address Table=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1=0D @@ -82,6 +77,7 @@ gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3=0D =0D # CA Vref Configuration=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig=0D =0D # Root Port Clock Info=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort0ClkInfo=0D @@ -128,7 +124,4 @@ gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5=0D =0D - # Misc=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent=0D -=0D =0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiMultiBoardInitPostMemLib.c b/Platform/Intel/KabylakeOpenBoa= rdPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c deleted file mode 100644 index 70e93e94da11..000000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiMultiBoardInitPostMemLib.c +++ /dev/null @@ -1,40 +0,0 @@ -/** @file=0D - Kaby Lake RVP 3 Multi-Board Initialization Post-Memory library=0D -=0D -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D -SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -=0D -#include =0D -=0D -EFI_STATUS=0D -EFIAPI=0D -KabylakeRvp3BoardInitBeforeSiliconInit (=0D - VOID=0D - );=0D -=0D -BOARD_POST_MEM_INIT_FUNC mKabylakeRvp3BoardInitFunc =3D {=0D - KabylakeRvp3BoardInitBeforeSiliconInit,=0D - NULL, // BoardInitAfterSiliconInit=0D -};=0D -=0D -EFI_STATUS=0D -EFIAPI=0D -PeiKabylakeRvp3MultiBoardInitLibConstructor (=0D - VOID=0D - )=0D -{=0D - if ((LibPcdGetSku () =3D=3D BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSku= () =3D=3D BoardIdSkylakeRvp3)) {=0D - return RegisterBoardPostMemInit (&mKabylakeRvp3BoardInitFunc);=0D - }=0D - return EFI_SUCCESS;=0D -}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/KabylakeOpenB= oardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.= inf deleted file mode 100644 index f955dd4ea966..000000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiMultiBoardInitPostMemLib.inf +++ /dev/null @@ -1,56 +0,0 @@ -## @file=0D -# Component information file for KabylakeRvp3InitLib in PEI post memory ph= ase.=0D -#=0D -# Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
=0D -#=0D -# SPDX-License-Identifier: BSD-2-Clause-Patent=0D -#=0D -##=0D -=0D -[Defines]=0D - INF_VERSION =3D 0x00010005=0D - BASE_NAME =3D PeiKabylakeRvp3MultiBoardInitLib=0D - FILE_GUID =3D C7D39F17-E5BA-41D9-8DFE-FF9017499280= =0D - MODULE_TYPE =3D BASE=0D - VERSION_STRING =3D 1.0=0D - LIBRARY_CLASS =3D NULL=0D - CONSTRUCTOR =3D PeiKabylakeRvp3MultiBoardInitLibConst= ructor=0D -=0D -[LibraryClasses]=0D - BaseLib=0D - DebugLib=0D - BaseMemoryLib=0D - MemoryAllocationLib=0D - GpioExpanderLib=0D - PcdLib=0D - SiliconInitLib=0D - MultiBoardInitSupportLib=0D -=0D -[Packages]=0D - MinPlatformPkg/MinPlatformPkg.dec=0D - KabylakeOpenBoardPkg/OpenBoardPkg.dec=0D - MdePkg/MdePkg.dec=0D - MdeModulePkg/MdeModulePkg.dec=0D - KabylakeSiliconPkg/SiPkg.dec=0D - IntelSiliconPkg/IntelSiliconPkg.dec=0D -=0D -[Sources]=0D - PeiKabylakeRvp3InitPostMemLib.c=0D - KabylakeRvp3GpioTable.c=0D - KabylakeRvp3HdaVerbTables.c=0D - PeiMultiBoardInitPostMemLib.c=0D -=0D -[FixedPcd]=0D -=0D -[Pcd]=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel=0D -=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize=0D -=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable=0D -=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiMultiBoardInitPreMemLib.c b/Platform/Intel/KabylakeOpenBoar= dPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c deleted file mode 100644 index 59b3177201db..000000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiMultiBoardInitPreMemLib.c +++ /dev/null @@ -1,82 +0,0 @@ -/** @file=0D - Kaby Lake RVP 3 Multi-Board Initialization Pre-Memory library=0D -=0D -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D -SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -=0D -#include =0D -=0D -EFI_STATUS=0D -EFIAPI=0D -KabylakeRvp3BoardDetect (=0D - VOID=0D - );=0D -=0D -EFI_STATUS=0D -EFIAPI=0D -KabylakeRvp3MultiBoardDetect (=0D - VOID=0D - );=0D -=0D -EFI_BOOT_MODE=0D -EFIAPI=0D -KabylakeRvp3BoardBootModeDetect (=0D - VOID=0D - );=0D -=0D -EFI_STATUS=0D -EFIAPI=0D -KabylakeRvp3BoardDebugInit (=0D - VOID=0D - );=0D -=0D -EFI_STATUS=0D -EFIAPI=0D -KabylakeRvp3BoardInitBeforeMemoryInit (=0D - VOID=0D - );=0D -=0D -BOARD_DETECT_FUNC mKabylakeRvp3BoardDetectFunc =3D {=0D - KabylakeRvp3MultiBoardDetect=0D -};=0D -=0D -BOARD_PRE_MEM_INIT_FUNC mKabylakeRvp3BoardPreMemInitFunc =3D {=0D - KabylakeRvp3BoardDebugInit,=0D - KabylakeRvp3BoardBootModeDetect,=0D - KabylakeRvp3BoardInitBeforeMemoryInit,=0D - NULL, // BoardInitAfterMemoryInit=0D - NULL, // BoardInitBeforeTempRamExit=0D - NULL, // BoardInitAfterTempRamExit=0D -};=0D -=0D -EFI_STATUS=0D -EFIAPI=0D -KabylakeRvp3MultiBoardDetect (=0D - VOID=0D - )=0D -{=0D - KabylakeRvp3BoardDetect ();=0D - if ((LibPcdGetSku () =3D=3D BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSku= () =3D=3D BoardIdSkylakeRvp3)) {=0D - RegisterBoardPreMemInit (&mKabylakeRvp3BoardPreMemInitFunc);=0D - }=0D - return EFI_SUCCESS;=0D -}=0D -=0D -EFI_STATUS=0D -EFIAPI=0D -PeiKabylakeRvp3MultiBoardInitPreMemLibConstructor (=0D - VOID=0D - )=0D -{=0D - return RegisterBoardDetect (&mKabylakeRvp3BoardDetectFunc);=0D -} \ No newline at end of file diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBo= ardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf deleted file mode 100644 index a51712ac347d..000000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiMultiBoardInitPreMemLib.inf +++ /dev/null @@ -1,136 +0,0 @@ -## @file=0D -# Component information file for PEI KabylakeRvp3 Board Init Pre-Mem Libra= ry=0D -#=0D -# Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
=0D -#=0D -# SPDX-License-Identifier: BSD-2-Clause-Patent=0D -#=0D -##=0D -=0D -[Defines]=0D - INF_VERSION =3D 0x00010005=0D - BASE_NAME =3D PeiKabylakeRvp3MultiBoardInitPreMemLi= b=0D - FILE_GUID =3D EA05BD43-136F-45EE-BBBA-27D75817574F= =0D - MODULE_TYPE =3D BASE=0D - VERSION_STRING =3D 1.0=0D - LIBRARY_CLASS =3D NULL=0D - CONSTRUCTOR =3D PeiKabylakeRvp3MultiBoardInitPreMemLi= bConstructor=0D -=0D -[LibraryClasses]=0D - BaseLib=0D - DebugLib=0D - BaseMemoryLib=0D - MemoryAllocationLib=0D - PcdLib=0D - SiliconInitLib=0D - MultiBoardInitSupportLib=0D - EcLib=0D -=0D -[Packages]=0D - MinPlatformPkg/MinPlatformPkg.dec=0D - KabylakeOpenBoardPkg/OpenBoardPkg.dec=0D - MdePkg/MdePkg.dec=0D - MdeModulePkg/MdeModulePkg.dec=0D - KabylakeSiliconPkg/SiPkg.dec=0D - IntelSiliconPkg/IntelSiliconPkg.dec=0D -=0D -[Sources]=0D - PeiKabylakeRvp3InitPreMemLib.c=0D - KabylakeRvp3HsioPtssTables.c=0D - KabylakeRvp3SpdTable.c=0D - PeiMultiBoardInitPreMemLib.c=0D - PeiKabylakeRvp3Detect.c=0D -=0D -[Pcd]=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort=0D -=0D - # PCH-LP HSIO PTSS Table=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size=0D -=0D - # PCH-H HSIO PTSS Table=0D - #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1=0D - #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2=0D - #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size=0D - #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size=0D -=0D - # SA Misc Config=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize=0D -=0D - # PEG Reset By GPIO=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive=0D -=0D -=0D - # SPD Address Table=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3=0D -=0D - # CA Vref Configuration=0D -=0D - # Root Port Clock Info=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort0ClkInfo=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort4ClkInfo=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort5ClkInfo=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort7ClkInfo=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort8ClkInfo=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort9ClkInfo=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortLanClkInfo=0D -=0D - # USB 2.0 Port AFE=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe=0D -=0D - # USB 2.0 Port Over Current Pin=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13=0D -=0D - # USB 3.0 Port Over Current Pin=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5=0D -=0D - # Misc=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent=0D -=0D -=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoar= dPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP= kg.dsc index 8523ab3f4fc1..6f7334db457e 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc @@ -1,5 +1,5 @@ ## @file=0D -# The main build description file for the KabylakeRvp3 board.=0D +# The main build description file for the Aspire VN7-572G board.=0D #=0D # Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
=0D #=0D @@ -11,7 +11,7 @@ DEFINE PLATFORM_SI_PACKAGE =3D KabylakeSiliconPkg=0D DEFINE PLATFORM_SI_BIN_PACKAGE =3D KabylakeSiliconBinPkg=0D DEFINE PLATFORM_BOARD_PACKAGE =3D KabylakeOpenBoardPkg=0D - DEFINE BOARD =3D KabylakeRvp3=0D + DEFINE BOARD =3D AspireVn7Dash572G=0D DEFINE PROJECT =3D $(PLATFORM_BOARD_PACKAGE= )/$(BOARD)=0D DEFINE PEI_ARCH =3D IA32=0D DEFINE DXE_ARCH =3D X64=0D @@ -20,10 +20,18 @@ #=0D # Default value for OpenBoardPkg.fdf use=0D #=0D - DEFINE BIOS_SIZE_OPTION =3D SIZE_70=0D + DEFINE BIOS_SIZE_OPTION =3D SIZE_60=0D +=0D + #=0D + # Debug logging=0D + #=0D + DEFINE USE_PEI_SPI_LOGGING =3D TRUE=0D + DEFINE USE_MEMORY_LOGGING =3D TRUE=0D + DEFINE RELEASE_LOGGING =3D ($(USE_PEI_SPI_LOGGING) || $(USE_MEMORY_= LOGGING))=0D + DEFINE TESTING =3D TRUE=0D =0D PLATFORM_NAME =3D $(PLATFORM_PACKAGE)=0D - PLATFORM_GUID =3D 8470676C-18E8-467F-B126-= 28DB1941AA5A=0D + PLATFORM_GUID =3D AEEEF17C-36B6-4B68-949A-= 1E54CB33492F=0D PLATFORM_VERSION =3D 0.1=0D DSC_SPECIFICATION =3D 0x00010005=0D OUTPUT_DIRECTORY =3D Build/$(PROJECT)=0D @@ -79,8 +87,9 @@ ##########################################################################= ######=0D [SkuIds]=0D 0x00|DEFAULT # 0|DEFAULT is reserved and always required.= =0D - 0x04|KabylakeRvp3=0D - 0x60|KabyLakeYLpddr3Rvp3=0D + # For further details on specific SKUs (which dGPU installed), see EC pa= ge of schematics=0D + 0x41|RayleighSLx_dGPU # Detect the UMA board by GPIO=0D + 0x42|NewgateSLx_dGPU=0D =0D ##########################################################################= ######=0D #=0D @@ -126,12 +135,15 @@ #=0D ##########################################################################= ######=0D =0D +# TODO: Harden and tune platform by libraries=0D [LibraryClasses.common]=0D #######################################=0D # Edk2 Packages=0D #######################################=0D FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFs= pWrapperApiLib.inf=0D FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib= /PeiFspWrapperApiTestLib.inf=0D + # This board will set debugging library instances; FIXME: UART2 not used= =0D + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull= .inf=0D =0D #######################################=0D # Silicon Initialization Package=0D @@ -168,6 +180,7 @@ # Board Package=0D #######################################=0D EcLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseEcLib/BaseEcLib.inf=0D + BoardEcLib|$(PROJECT)/Library/BoardEcLib/BoardEcLib.inf=0D GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/Ba= seGpioExpanderLib.inf=0D I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAcc= essLib.inf=0D PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatf= ormSecLib/SecFspWrapperPlatformSecLib.inf=0D @@ -181,7 +194,7 @@ #######################################=0D # Board-specific=0D #######################################=0D - PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookL= ib.inf=0D + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatfor= mHookLibNull.inf=0D !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1=0D #=0D # FSP API mode=0D @@ -194,14 +207,38 @@ SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/PeiSiliconPolicyUpdateL= ib/PeiSiliconPolicyUpdateLib.inf=0D !endif=0D =0D -[LibraryClasses.IA32.SEC]=0D +# NB: MinPlatform sets a NULL DebugLib and only overrides it for DEBUG bui= lds=0D +# TODO: Now that all debug logging is routed through RSC, correct the defi= nes=0D +[LibraryClasses.common.SEC]=0D + #######################################=0D + # Edk2 Packages=0D + #######################################=0D + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +=0D #######################################=0D # Platform Package=0D #######################################=0D TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Sec= TestPointCheckLib.inf=0D SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLib= Null/SecBoardInitLibNull.inf=0D =0D +[LibraryClasses.common.PEI_CORE]=0D + #######################################=0D + # Edk2 Packages=0D + #######################################=0D +# SPI logging requires local patch: InitializeMemoryServices() before Proc= essLibraryConstructorList()=0D +# In-memory logging may require too many services for early core debug out= put=0D +!if $(RELEASE_LOGGING) =3D=3D TRUE=0D + DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebug= LibReportStatusCode.inf=0D +!endif=0D +=0D [LibraryClasses.common.PEIM]=0D + #######################################=0D + # Edk2 Packages=0D + #######################################=0D +!if $(RELEASE_LOGGING) =3D=3D TRUE=0D + DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebug= LibReportStatusCode.inf=0D +!endif=0D +=0D #######################################=0D # Silicon Package=0D #######################################=0D @@ -214,7 +251,7 @@ FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf=0D MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/PeiMultiBoardInitSupportLib.inf=0D TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointL= ib.inf=0D -!if $(TARGET) =3D=3D DEBUG=0D +!if ($(TARGET) =3D=3D DEBUG || $(TESTING) =3D=3D TRUE)=0D TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pei= TestPointCheckLib.inf=0D !endif=0D SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrr= LibNull.inf=0D @@ -228,7 +265,22 @@ PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPol= icyLib/PeiTbtPolicyLib.inf=0D !endif=0D =0D +[LibraryClasses.common.DXE_CORE]=0D + #######################################=0D + # Edk2 Packages=0D + #######################################=0D +!if $(USE_MEMORY_LOGGING) =3D=3D TRUE=0D + DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebug= LibReportStatusCode.inf=0D +!endif=0D +=0D [LibraryClasses.common.DXE_DRIVER]=0D + #######################################=0D + # Edk2 Packages=0D + #######################################=0D +!if $(USE_MEMORY_LOGGING) =3D=3D TRUE=0D + DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebug= LibReportStatusCode.inf=0D +!endif=0D +=0D #######################################=0D # Silicon Initialization Package=0D #######################################=0D @@ -244,7 +296,7 @@ MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/DxeMultiBoardInitSupportLib.inf=0D TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointL= ib.inf=0D =0D -!if $(TARGET) =3D=3D DEBUG=0D +!if ($(TARGET) =3D=3D DEBUG || $(TESTING) =3D=3D TRUE)=0D TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Dxe= TestPointCheckLib.inf=0D !endif=0D #######################################=0D @@ -258,13 +310,35 @@ #######################################=0D SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/DxeSiliconPolicyUpdateL= ib/DxeSiliconPolicyUpdateLib.inf=0D =0D -[LibraryClasses.X64.DXE_RUNTIME_DRIVER]=0D +[LibraryClasses.common.DXE_RUNTIME_DRIVER]=0D + #######################################=0D + # Edk2 Packages=0D + #######################################=0D +!if $(USE_MEMORY_LOGGING) =3D=3D TRUE=0D + DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebug= LibReportStatusCode.inf=0D +!endif=0D +=0D #######################################=0D # Silicon Initialization Package=0D #######################################=0D ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemL= ib/DxeRuntimeResetSystemLib.inf=0D =0D -[LibraryClasses.X64.DXE_SMM_DRIVER]=0D +[LibraryClasses.common.SMM_CORE]=0D + #######################################=0D + # Edk2 Packages=0D + #######################################=0D +!if $(USE_MEMORY_LOGGING) =3D=3D TRUE=0D + DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebug= LibReportStatusCode.inf=0D +!endif=0D +=0D +[LibraryClasses.common.DXE_SMM_DRIVER]=0D + #######################################=0D + # Edk2 Packages=0D + #######################################=0D +!if $(USE_MEMORY_LOGGING) =3D=3D TRUE=0D + DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebug= LibReportStatusCode.inf=0D +!endif=0D +=0D #######################################=0D # Silicon Initialization Package=0D #######################################=0D @@ -276,10 +350,13 @@ BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSuppor= tLib/SmmMultiBoardAcpiSupportLib.inf=0D MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpi= SupportLib/SmmMultiBoardAcpiSupportLib.inf=0D TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointL= ib.inf=0D -!if $(TARGET) =3D=3D DEBUG=0D +!if ($(TARGET) =3D=3D DEBUG || $(TESTING) =3D=3D TRUE)=0D TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Smm= TestPointCheckLib.inf=0D !endif=0D =0D +# TODO: DebugLib override for UEFI_DRIVER and UEFI_APPLICATION?=0D +=0D +# TODO: Add and improve feature support=0D #######################################=0D # PEI Components=0D #######################################=0D @@ -294,6 +371,19 @@ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf=0D }=0D =0D + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf {= =0D + =0D + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +!if $(USE_PEI_SPI_LOGGING) =3D=3D TRUE=0D + SerialPortLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiSerialPortLibSpiF= lash/PeiSerialPortLibSpiFlash.inf=0D +!else if $(USE_MEMORY_LOGGING) =3D=3D TRUE=0D + SerialPortLib|MdeModulePkg/Library/PeiDxeSerialPortLibMem/PeiSerialP= ortLibMem.inf=0D +!endif=0D + =0D + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|$(RELEASE_LOGG= ING)=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|63=0D + }=0D +=0D !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1=0D #=0D # In FSP API mode the policy has to be installed before FSP Wrapper upda= ting UPD.=0D @@ -326,6 +416,15 @@ }=0D !endif=0D =0D +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE=0D + SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf {=0D + =0D + NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf=0D + NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf= =0D + NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256= .inf=0D + }=0D +!endif=0D +=0D #######################################=0D # Silicon Initialization Package=0D #######################################=0D @@ -398,16 +497,44 @@ # @todo: Change below line to [Components.$(DXE_ARCH)] after https://bugzi= lla.tianocore.org/show_bug.cgi?id=3D2308=0D # is completed=0D [Components.X64]=0D +# Compiled .efi but not in FV (PcdBootStage =3D=3D 4-6, with performance b= uild):=0D +# - dpDynamicCommand, TestPointDumpApp=0D +# Other apps; perhaps useful:=0D +# - MdeModulePkg/{DumpDynPcd,*ProfileInfo,VariableInfo}, UefiCpuPkg/Cpuid= =0D +# - Also, ShellPkg/*DynamicCommand=0D +=0D #######################################=0D # Edk2 Packages=0D #######################################=0D + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRun= timeDxe.inf {=0D + =0D + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +!if $(USE_MEMORY_LOGGING) =3D=3D TRUE=0D + SerialPortLib|MdeModulePkg/Library/PeiDxeSerialPortLibMem/DxeSerialP= ortLibMem.inf=0D +!endif=0D + =0D + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|$(USE_MEMORY_L= OGGING)=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1024=0D + }=0D + # TODO: Still requires a little more thought=0D + MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf {= =0D + =0D + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D +!if $(USE_MEMORY_LOGGING) =3D=3D TRUE=0D + SerialPortLib|MdeModulePkg/Library/PeiDxeSerialPortLibMem/SmmSerialP= ortLibMem.inf=0D +!endif=0D + =0D + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|$(USE_MEMORY_L= OGGING)=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1024=0D + }=0D MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf=0D MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf=0D MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf=0D MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf=0D MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf=0D MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf=0D - MdeModulePkg/Universal/BdsDxe/BdsDxe.inf{=0D + MdeModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf=0D + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf {=0D =0D NULL|BoardModulePkg/Library/BdsPs2KbcLib/BdsPs2KbcLib.inf=0D }=0D @@ -424,14 +551,15 @@ =0D gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE=0D =0D - NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comma= ndsLib.inf=0D NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comma= ndsLib.inf=0D + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comma= ndsLib.inf=0D NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comma= ndsLib.inf=0D NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Com= mandsLib.inf=0D NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1C= ommandsLib.inf=0D NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comma= ndsLib.inf=0D NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1C= ommandsLib.inf=0D NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2C= ommandsLib.inf=0D + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCo= mmandLib.inf=0D ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommand= Lib.inf=0D HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePars= ingLib.inf=0D BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfg= CommandLib.inf=0D @@ -450,6 +578,16 @@ }=0D !endif=0D =0D +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE=0D + SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf {=0D + =0D + Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibR= outerDxe.inf=0D + NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf=0D + NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf= =0D + NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256= .inf=0D + }=0D +!endif=0D +=0D #######################################=0D # Silicon Initialization Package=0D #######################################=0D @@ -514,6 +652,7 @@ NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.i= nf=0D !endif=0D }=0D + $(PROJECT)/Acpi/BoardAcpiTables.inf=0D !endif=0D BoardModulePkg/LegacySioDxe/LegacySioDxe.inf=0D BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoar= dPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP= kg.fdf index 6cdf4e2f9f1f..53cfb23be964 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.fdf @@ -23,7 +23,7 @@ # existing system flash.=0D #=0D ##########################################################################= ######=0D -[FD.KabylakeRvp3]=0D +[FD.AspireVn7Dash572G]=0D #=0D # FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks, c= annot be=0D # assigned with PCD values. Instead, it uses the definitions for its varie= ty, which=0D @@ -131,6 +131,10 @@ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpar= eOffset|gEfiMdeModulePkgTo gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize=0D #NV_FTW_SPARE=0D =0D +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageOffset|gKabylake= OpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageSize=0D +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageBase|gKabylakeOp= enBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageSize=0D +#DEBUG_MESSAGE_AREA=0D +=0D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvAdvancedSize=0D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvAdvancedSize=0D FV =3D FvAdvanced=0D @@ -276,7 +280,7 @@ INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/S= iliconPolicyPeiPostMem.in =0D !if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable =3D=3D TRUE=0D FILE FREEFORM =3D 4ad46122-ffeb-4a52-bfb0-518cfca02db0 {=0D - SECTION RAW =3D $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin=0D + SECTION RAW =3D AspireVn7Dash572G/Vbt.bin=0D SECTION UI =3D "Vbt"=0D }=0D FILE FREEFORM =3D 7BB28B99-61BB-11D5-9A5D-0090273FC14D {=0D @@ -330,6 +334,13 @@ READ_LOCK_CAP =3D TRUE READ_LOCK_STATUS =3D TRUE=0D FvNameGuid =3D A881D567-6CB0-4eee-8435-2E72D33E45B5=0D =0D +# NOTE: UefiDriverEntryPoint imports a dependency on the architectural pro= tocols.=0D +APRIORI DXE {=0D + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf=0D + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStat= usCodeRouterRuntimeDxe.inf=0D + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandl= erRuntimeDxe.inf=0D +}=0D +=0D !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf=0D =0D INF UefiCpuPkg/CpuDxe/CpuDxe.inf=0D @@ -341,6 +352,7 @@ INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPass= Thru.inf INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.in= f=0D INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf=0D INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf=0D +INF MdeModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf=0D INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf=0D =0D INF ShellPkg/Application/Shell/Shell.inf=0D @@ -401,6 +413,12 @@ READ_LOCK_CAP =3D TRUE READ_LOCK_STATUS =3D TRUE=0D FvNameGuid =3D A0F04529-B715-44C6-BCA4-2DEBDD01EEEC=0D =0D +# NOTE: UefiDriverEntryPoint imports a dependency on the architectural pro= tocols.=0D +APRIORI DXE {=0D + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeR= outerSmm.inf=0D + INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.i= nf=0D +}=0D +=0D !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf=0D =0D INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf=0D @@ -414,6 +432,7 @@ INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.i= nf INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf=0D =0D INF RuleOverride =3D DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/Boar= dAcpiDxe/BoardAcpiDxe.inf=0D +INF RuleOverride =3D ACPITABLE $(PROJECT)/Acpi/BoardAcpiTables.inf=0D =0D INF $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf= =0D =0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoar= dPkgBuildOption.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G= /OpenBoardPkgBuildOption.dsc index 8e885cc6a4b8..5687915f1ebc 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgBui= ldOption.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgBui= ldOption.dsc @@ -144,7 +144,7 @@ MSFT: *_*_X64_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_= BUILD_OPTIONS) MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096=0D GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000=0D =0D -# Force PE/COFF sections to be aligned at 4KB boundaries to support NX pro= tection=0D +# TODO: Force PE/COFF sections to be aligned at 4KB boundaries to support = NX protection=0D [BuildOptions.common.EDKII.DXE_DRIVER, BuildOptions.common.EDKII.DXE_CORE,= BuildOptions.common.EDKII.UEFI_DRIVER, BuildOptions.common.EDKII.UEFI_APPL= ICATION]=0D #MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096=0D #GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoar= dPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoa= rdPkgPcd.dsc index 725596cbf71e..1d139120045e 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd= .dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd= .dsc @@ -1,5 +1,5 @@ ## @file=0D -# PCD configuration build description file for the KabylakeRvp3 board.=0D +# PCD configuration build description file for the Aspire VN7-572G board.= =0D #=0D # Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
=0D #=0D @@ -13,6 +13,9 @@ #=0D ##########################################################################= ######=0D =0D +# NB: Many "*Size" UPDs may not be hooked up!=0D +# TODO: Harden and tune platform by PCDs=0D +=0D [PcdsFixedAtBuild.common]=0D ######################################=0D # Key Boot Stage and FSP configuration=0D @@ -26,7 +29,7 @@ # Stage 5 - boot to OS with security boot enabled=0D # Stage 6 - boot with advanced features enabled=0D #=0D - gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4=0D + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|6=0D =0D #=0D # 0: FSP Wrapper is running in Dispatch mode.=0D @@ -68,27 +71,27 @@ =0D gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000=0D gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000=0D - gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000=0D + gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 # Now corrected, bu= t unused=0D gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000=0D - gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000=0D + gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000 # Now hooked up; TODO: Size= =0D =0D !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1=0D #=0D # FSP API mode does not share stack with the boot loader,=0D # so FSP needs more temporary memory for FSP heap + stack size.=0D #=0D - gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000=0D + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x28000 # Now update= d to not deprive FSP of stack=0D #=0D # FSP API mode does not need to enlarge the boot loader stack size=0D # since the stacks are separate.=0D #=0D - gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000=0D + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 # Not hooked u= p, not used (functionally equivalent and equal to UefiCpuPkg)=0D !else=0D #=0D # In FSP Dispatch mode boot loader stack size must be large=0D # enough for executing both boot loader and FSP.=0D #=0D - gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x40000=0D + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x40000 # Not hooked up= , not used (functionally equivalent but NOT equal to UefiCpuPkg)=0D !endif=0D =0D !if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode =3D=3D FALSE) || = (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1)=0D @@ -110,6 +113,28 @@ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE=0D gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE=0D gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE=0D +# TODO: Prune this list to relevant features only=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 6=0D + # FIXME: SMM path also PatchAndLoadAcpiTable()=0D + gAcpiDebugFeaturePkgTokenSpaceGuid.PcdAcpiDebugFeatureEnable = |FALSE=0D + # PcdIpmiFeatureEnable will not be enabled (no BMC)=0D + # TODO: Can be build-time (user) choice=0D + gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable = |FALSE=0D + # TODO: Continue developing support. May be broken at present.=0D + # - PeiSmmAccessLib in IntelSiliconPkg seems like a stub=0D + # - Only require a PeiSmmControlLib if SMM communicate is required=0D + gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable = |TRUE=0D + # TODO: Definitions (now added SmbiosDxe)=0D + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable = |FALSE=0D + # Requires actual hook-up=0D + gUsb3DebugFeaturePkgTokenSpaceGuid.PcdUsb3DebugFeatureEnable = |FALSE=0D + # FIXME: (Similar) DXE module is duplicate?=0D + gUserAuthFeaturePkgTokenSpaceGuid.PcdUserAuthenticationFeatureEnable = |FALSE=0D + # TODO: BGRT must be BMP, but this duplicates FSP logo. Can GetSectionFr= omAnyFv()?=0D + # - Also, broken? How?=0D + gLogoFeaturePkgTokenSpaceGuid.PcdLogoFeatureEnable = |FALSE=0D + gLogoFeaturePkgTokenSpaceGuid.PcdJpgEnable = |FALSE=0D +!endif=0D =0D ######################################=0D # Silicon Configuration=0D @@ -151,8 +176,8 @@ gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE=0D gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE=0D gSiPkgTokenSpaceGuid.PcdSerialGpioEnable|TRUE=0D - gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE=0D - gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE=0D + gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|$(RELEASE_LOGGING)=0D + gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE # TODO: Create libraries, inc= lude modules and hook-up someday=0D gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE=0D gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE=0D gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable|TRUE=0D @@ -165,10 +190,10 @@ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE=0D gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE=0D gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE=0D - gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE=0D + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE # FIXME: Defin= e by PERFORMANCE_BUILD?=0D gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE=0D gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE=0D - gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable|FALSE=0D + gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable|FALSE # FIXME: De= fine in build-system?=0D =0D !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1=0D gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE=0D @@ -193,7 +218,8 @@ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE=0D !endif=0D =0D -!if $(TARGET) =3D=3D DEBUG=0D +# TODO: Build profiler?=0D +!if ($(TARGET) =3D=3D DEBUG || $(TESTING) =3D=3D TRUE)=0D gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE=0D !else=0D gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE=0D @@ -202,7 +228,7 @@ ######################################=0D # Board Configuration=0D ######################################=0D - gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport|TRUE=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport|FALSE=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable|FALSE=0D =0D [PcdsFixedAtBuild.common]=0D @@ -213,7 +239,15 @@ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0=0D gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3=0D !else=0D - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F=0D + # FIXME: More than just compiler optimisation is hooked to DEBUG builds.= =0D + # Make asserts non-fatal for my early debugging=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0F=0D + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07=0D +!endif=0D + # Overrides: Cater to limited debugging system=0D +!if $(RELEASE_LOGGING) =3D=3D TRUE=0D + # TODO: DEBUG_CODE macros might not be production-ready=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x07=0D gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07=0D !endif=0D gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000=0D @@ -287,7 +321,7 @@ ######################################=0D =0D # Refer to HstiFeatureBit.h for bit definitions=0D - gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2=0D + gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 # FIXME: Boot Guard and BI= OS Guard not present, measured boot enforcement checking code not present=0D gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07=0D =0D ######################################=0D @@ -309,13 +343,24 @@ #=0D gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07=0D =0D -!if $(TARGET) =3D=3D RELEASE=0D - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402=0D -!else=0D - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B=0D -!endif=0D + ## This PCD is to control which device is the potential trusted console = input device.

=0D + # For example:
=0D + # PS/2 keyboard: PciRoot(0x0)/Pci(0x1F,0x0)/Acpi(PNP0303,0x0)
=0D + # //Header HID UID
=0D + # {0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00= , 0x00,
=0D + # //Header Func Dev
=0D + # 0x01, 0x01, 0x06, 0x00, 0x00, 0x1F,
=0D + # //Header HID UID
=0D + # 0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x03, 0x00, 0x00, 0x00= , 0x00,
=0D + # //Header
=0D + # 0x7F, 0xFF, 0x04, 0x00}
=0D + gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{0x02, 0x= 01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01= , 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x03,= 0x00, 0x00, 0x00, 0x00, 0x7F, 0xFF, 0x04, 0x00}=0D =0D - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b=0D +!if $(TARGET) =3D=3D DEBUG=0D + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B #= TODO=0D +!endif=0D + # TODO: Consider using reserved space instead for debug log=0D + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x200=0D !if $(TARGET) =3D=3D RELEASE=0D gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70=0D !else=0D @@ -335,15 +380,15 @@ !endif=0D =0D !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 4=0D - gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07= , 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00}=0D + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07= , 0x03, 0x05, 0x3F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00}=0D !endif=0D =0D !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 5=0D - gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F= , 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00}=0D + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F= , 0x07, 0x1F, 0x3F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00}=0D !endif=0D =0D !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 6=0D - gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F= , 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00}=0D + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F= , 0x07, 0x1F, 0x3F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00}=0D !endif=0D =0D =0D @@ -353,7 +398,7 @@ gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable|1=0D gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x00, 0x00, = 0x1F, 0x00}=0D =0D -[PcdsFixedAtBuild.IA32]=0D +[PcdsFixedAtBuild.IA32] # TODO?=0D ######################################=0D # Edk2 Configuration=0D ######################################=0D @@ -379,7 +424,7 @@ # Edk2 Configuration=0D ######################################=0D gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208=0D - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 # Consider = louder - 0x806800C7 - then reducing noise=0D =0D ######################################=0D # Silicon Configuration=0D @@ -421,8 +466,10 @@ ######################################=0D # Board Configuration=0D ######################################=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle|1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative|1=0D =0D - # Thunderbolt Configuration=0D + # Thunderbolt Configuration (FIXME: Remove if not supporting Newgate)=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcpiGpeSignature|0=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting|0=0D @@ -462,3 +509,7 @@ !else=0D gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|5 # Variable: L"Timeout"=0D !endif=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE=0D + gEfiSecurityPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|L"TCG2_= VERSION"|gTcg2ConfigFormSetGuid|0x0|"1.3"|NV,BS=0D + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableRev|L"TCG2_VERSION"|gTcg2C= onfigFormSetGuid|0x8|3|NV,BS=0D +!endif=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c b/Platform/Intel/Kabyla= keOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/D= xeGopPolicyInit.c index 7744af6b3cfc..eff8ea0c1345 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c @@ -6,8 +6,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =0D **/=0D =0D -#include "DxeGopPolicyInit.h"=0D +#include =0D #include =0D +#include "DxeGopPolicyInit.h"=0D =0D GLOBAL_REMOVE_IF_UNREFERENCED GOP_POLICY_PROTOCOL mGOPPolicy;=0D GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mVbtSize =3D 0;=0D @@ -30,7 +31,18 @@ GetPlatformLidStatus ( OUT LID_STATUS *CurrentLidStatus=0D )=0D {=0D - return EFI_UNSUPPORTED;=0D + EFI_STATUS Status;=0D + UINT8 PowerRegister;=0D +=0D + Status =3D EcRead(0x70, &PowerRegister);=0D + if (EFI_ERROR(Status)) {=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + // "ELID"=0D + *CurrentLidStatus =3D (PowerRegister & BIT1) ? LidOpen : LidClosed;=0D + =0D + return EFI_SUCCESS;=0D }=0D /**=0D =0D @@ -45,7 +57,8 @@ GetPlatformDockStatus ( OUT DOCK_STATUS CurrentDockStatus=0D )=0D {=0D - return EFI_UNSUPPORTED;=0D + // TODO: UnDocked or no dock=0D + return EFI_UNSUPPORTED;=0D }=0D =0D =0D @@ -154,7 +167,7 @@ GopPolicyInitDxe ( //=0D // Initialize the EFI Driver Library=0D //=0D - SetMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL), 0);=0D + ZeroMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL));=0D =0D mGOPPolicy.Revision =3D GOP_POLICY_PROTOCOL_REVISION_03;= =0D mGOPPolicy.GetPlatformLidStatus =3D GetPlatformLidStatus;=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c b/Platform/Intel/Kabyl= akeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/= DxeSaPolicyUpdate.c index fcd248fdf5cf..311fcd7ab487 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c @@ -29,21 +29,19 @@ UpdateRmrrUsbAddress ( Status =3D GetConfigBlock ((VOID *)SaPolicy, &gMiscDxeConfigGuid, (VOID = *)&MiscDxeConfig);=0D ASSERT_EFI_ERROR (Status);=0D =0D - if (1) {=0D - mSize =3D EFI_SIZE_TO_PAGES(SA_VTD_RMRR_USB_LENGTH);=0D - mAddress =3D SIZE_4GB;=0D + mSize =3D EFI_SIZE_TO_PAGES(SA_VTD_RMRR_USB_LENGTH);=0D + mAddress =3D SIZE_4GB;=0D =0D - Status =3D (gBS->AllocatePages) (=0D - AllocateMaxAddress,=0D - EfiReservedMemoryType,=0D - mSize,=0D - &mAddress=0D - );=0D - ASSERT_EFI_ERROR (Status);=0D + Status =3D (gBS->AllocatePages) (=0D + AllocateMaxAddress,=0D + EfiReservedMemoryType,=0D + mSize,=0D + &mAddress=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D =0D - MiscDxeConfig->RmrrUsbBaseAddress[0] =3D mAddress;=0D - MiscDxeConfig->RmrrUsbBaseAddress[1] =3D mAddress + SA_VTD_RMRR_USB_LE= NGTH - 1;=0D - }=0D + MiscDxeConfig->RmrrUsbBaseAddress[0] =3D mAddress;=0D + MiscDxeConfig->RmrrUsbBaseAddress[1] =3D mAddress + SA_VTD_RMRR_USB_LENG= TH - 1;=0D }=0D =0D /**=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c b/Platform/Int= el/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUp= dateLib/DxeSiliconPolicyUpdateLib.c index d4dbb414a26f..213b8e53ebca 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c @@ -5,9 +5,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =0D **/=0D =0D +#include =0D #include =0D #include =0D #include =0D +#include =0D +#include =0D =0D #include "DxeSaPolicyInit.h"=0D #include "DxeGopPolicyInit.h"=0D @@ -33,21 +36,42 @@ SiliconPolicyUpdateLate ( IN VOID *Policy=0D )=0D {=0D - SA_POLICY_PROTOCOL *SaPolicy;=0D + SA_POLICY_PROTOCOL *SaPolicy =3D Policy;=0D EFI_STATUS Status;=0D + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;=0D + GOP_POLICY_PROTOCOL *GopPolicy;=0D + EFI_PHYSICAL_ADDRESS VbtAddress;=0D + UINT32 VbtSize;=0D +=0D + Status =3D GetConfigBlock ((VOID *)SaPolicy, &gGraphicsDxeConfigGuid, (V= OID *) &GraphicsDxeConfig);=0D + ASSERT_EFI_ERROR (Status);=0D =0D - SaPolicy =3D Policy;=0D UpdateDxeSaPolicy (SaPolicy);=0D =0D - if (PcdGetBool(PcdIntelGopEnable)) {=0D + if (PcdGetBool (PcdIntelGopEnable)) {=0D //=0D // GOP Dxe Policy Initialization=0D //=0D Status =3D GopPolicyInitDxe(gImageHandle);=0D - DEBUG((DEBUG_INFO, "GOP Dxe Policy Initialization done\n"));=0D + DEBUG ((DEBUG_INFO, "GOP Dxe Policy Initialization done\n"));=0D ASSERT_EFI_ERROR(Status);=0D }=0D =0D + // Copy VBT address to Policy=0D + Status =3D gBS->LocateProtocol (&gGopPolicyProtocolGuid, NULL, (VOID **)= &GopPolicy);=0D + if (!EFI_ERROR(Status)) {=0D + Status =3D GopPolicy->GetVbtData (&VbtAddress, &VbtSize);=0D + if (!EFI_ERROR(Status) && GraphicsDxeConfig !=3D NULL) {=0D + GraphicsDxeConfig->VbtAddress =3D VbtAddress;=0D + GraphicsDxeConfig->Size =3D VbtSize;=0D + DEBUG ((DEBUG_INFO, "Located VBT at 0x%x with size 0x%x\n", VbtAddre= ss, VbtSize));=0D + } else {=0D + DEBUG ((DEBUG_ERROR, "No VBT found, or Policy =3D=3D NULL; Status - = %r\n", Status));=0D + }=0D + }=0D +=0D + // FIXME: DspEnable is set, per PeiPchPolicyLib, however it is disabled = in the HOB produced by FSP=0D +=0D return Policy;=0D }=0D =0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf b/Platform/I= ntel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicy= UpdateLib/DxeSiliconPolicyUpdateLib.inf index 2abf1aef805a..ca769728cdb8 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf @@ -20,6 +20,7 @@ PcdLib=0D DebugLib=0D ConfigBlockLib=0D + EcLib=0D =0D [Packages]=0D MdePkg/MdePkg.dec=0D @@ -44,6 +45,7 @@ gGopPolicyProtocolGuid ## PRODUCES=0D =0D [Guids]=0D + gGraphicsDxeConfigGuid=0D gMiscDxeConfigGuid=0D =0D [Depex]=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c b/Platform/Intel/Ka= bylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateL= ib/PeiBoardPolicyUpdate.c new file mode 100644 index 000000000000..ecd6f9ec292c --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c @@ -0,0 +1,328 @@ +/** @file=0D + This file configures Aspire VN7-572G board-specific policies.=0D +=0D +Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/* TODO: Some disabled devices are likely fuse-disabled. Remove such entri= es */=0D +/* TODO/NB: The configs commented here but not in FspWrapper must be found= ! */=0D +/*=0D + IgdDvmt50PreAlloc =3D ?=0D +*/=0D +=0D +#define SA_VR 0=0D +#define IA_VR 1=0D +#define GT_UNSLICED_VR 2=0D +#define GT_SLICED_VR 3=0D +=0D +/**=0D + Performs the remainder of board-specific FSP Policy initialization.=0D +=0D + @param[in] Policy Policy PPI pointer.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspBoardPolicyUpdatePreMem (=0D + IN VOID *Policy=0D + )=0D +{=0D + EFI_STATUS Status;=0D + MEMORY_CONFIGURATION *MemConfig;=0D + PCH_HPET_PREMEM_CONFIG *HpetPreMemConfig;=0D +=0D + // Retrieve the config blocks we depend on=0D + Status =3D GetConfigBlock (Policy, &gMemoryConfigGuid, (VOID *) &MemConf= ig);=0D + ASSERT_EFI_ERROR(Status);=0D + if (MemConfig =3D=3D NULL) {=0D + return EFI_NOT_FOUND;=0D + }=0D + Status =3D GetConfigBlock (Policy, &gHpetPreMemConfigGuid, (VOID *) &Hpe= tPreMemConfig);=0D + ASSERT_EFI_ERROR(Status);=0D + if (HpetPreMemConfig =3D=3D NULL) {=0D + return EFI_NOT_FOUND;=0D + }=0D +=0D + /* System Agent config */=0D +//FIXME FspmUpd->FspmConfig.UserBd =3D PcdGet8(PcdSaMiscUserBd);=0D + MemConfig->DqPinsInterleaved =3D (UINT8)PcdGetBool(PcdMrcDqPinsInterleav= ed);=0D + MemConfig->CaVrefConfig =3D PcdGet8(PcdMrcCaVrefConfig);=0D + MemConfig->SaGv =3D 3; // Enabled=0D +=0D + // TODO: Why should this be here?=0D +//FIXME FspmUpd->FspmConfig.TsegSize =3D PcdGet32(PcdTsegSize);=0D + // TODO: Isn't IED nochoice and nocare?=0D + // FSP should program it's default BDF value (but where is bus 0xF0?)=0D + HpetPreMemConfig->BdfValid =3D 1;=0D +=0D + /* iGFX config */=0D +//FIXME FspmUpd->FspmConfig.PrimaryDisplay =3D 4; // Switchable Graphics= =0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Performs the remainder of board-specific FSP Policy initialization.=0D +=0D + @param[in] Policy Policy PPI pointer.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspBoardPolicyUpdate (=0D + IN VOID *Policy=0D + )=0D +{=0D + EFI_STATUS Status;=0D + PCH_LOCK_DOWN_CONFIG *LockDownConfig;=0D + PCH_GENERAL_CONFIG *PchGeneralConfig;=0D + CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig;=0D + CPU_POWER_MGMT_VR_CONFIG *CpuPowerMgmtVrConfig;=0D + PCH_USB_CONFIG *UsbConfig;=0D + PCH_SATA_CONFIG *SataConfig;=0D + PCH_PCIE_CONFIG *PchPcieConfig;=0D + PCH_PM_CONFIG *PmConfig;=0D + PCH_LPC_SIRQ_CONFIG *SerialIrqConfig;=0D + PCH_HDAUDIO_CONFIG *HdAudioConfig;=0D + PCH_IOAPIC_CONFIG *IoApicConfig;=0D +=0D + // Retrieve the config blocks we depend on (all are expected to be insta= lled)=0D + Status =3D GetConfigBlock (Policy, &gLockDownConfigGuid, (VOID *) &LockD= ownConfig);=0D + ASSERT_EFI_ERROR(Status);=0D + if (LockDownConfig =3D=3D NULL) {=0D + return EFI_NOT_FOUND;=0D + }=0D + Status =3D GetConfigBlock (Policy, &gPchGeneralConfigGuid, (VOID *) &Pch= GeneralConfig);=0D + ASSERT_EFI_ERROR(Status);=0D + if (PchGeneralConfig =3D=3D NULL) {=0D + return EFI_NOT_FOUND;=0D + }=0D + Status =3D GetConfigBlock (Policy, &gCpuPowerMgmtBasicConfigGuid, (VOID = *) &CpuPowerMgmtBasicConfig);=0D + ASSERT_EFI_ERROR(Status);=0D + if (CpuPowerMgmtBasicConfig =3D=3D NULL) {=0D + return EFI_NOT_FOUND;=0D + }=0D + Status =3D GetConfigBlock (Policy, &gCpuPowerMgmtVrConfigGuid, (VOID *) = &CpuPowerMgmtVrConfig);=0D + ASSERT_EFI_ERROR(Status);=0D + if (CpuPowerMgmtVrConfig =3D=3D NULL) {=0D + return EFI_NOT_FOUND;=0D + }=0D + Status =3D GetConfigBlock (Policy, &gUsbConfigGuid, (VOID *) &UsbConfig)= ;=0D + ASSERT_EFI_ERROR(Status);=0D + if (UsbConfig =3D=3D NULL) {=0D + return EFI_NOT_FOUND;=0D + }=0D + Status =3D GetConfigBlock (Policy, &gSataConfigGuid, (VOID *) &SataConfi= g);=0D + ASSERT_EFI_ERROR(Status);=0D + if (SataConfig =3D=3D NULL) {=0D + return EFI_NOT_FOUND;=0D + }=0D + Status =3D GetConfigBlock (Policy, &gPcieRpConfigGuid, (VOID *) &PchPcie= Config);=0D + ASSERT_EFI_ERROR(Status);=0D + if (PchPcieConfig =3D=3D NULL) {=0D + return EFI_NOT_FOUND;=0D + }=0D + Status =3D GetConfigBlock (Policy, &gPmConfigGuid, (VOID *) &PmConfig);= =0D + ASSERT_EFI_ERROR(Status);=0D + if (PmConfig =3D=3D NULL) {=0D + return EFI_NOT_FOUND;=0D + }=0D + Status =3D GetConfigBlock (Policy, &gSerialIrqConfigGuid, (VOID *) &Seri= alIrqConfig);=0D + ASSERT_EFI_ERROR(Status);=0D + if (SerialIrqConfig =3D=3D NULL) {=0D + return EFI_NOT_FOUND;=0D + }=0D + Status =3D GetConfigBlock (Policy, &gHdAudioConfigGuid, (VOID *) &HdAudi= oConfig);=0D + ASSERT_EFI_ERROR(Status);=0D + if (HdAudioConfig =3D=3D NULL) {=0D + return EFI_NOT_FOUND;=0D + }=0D + Status =3D GetConfigBlock (Policy, &gIoApicConfigGuid, (VOID *) &IoApicC= onfig);=0D + ASSERT_EFI_ERROR(Status);=0D + if (IoApicConfig =3D=3D NULL) {=0D + return EFI_NOT_FOUND;=0D + }=0D +=0D + // FIXME/NB: This is insecure and not production-ready!=0D + // TODO: Configure SPI lockdown by variable on FrontPage?=0D + LockDownConfig->BiosLock =3D 0;=0D + LockDownConfig->SpiEiss =3D 0;=0D +=0D + // TODO: Why should this be here?=0D + // FSP should program it's default BDF value (but where is bus 0xF0?)=0D + IoApicConfig->BdfValid =3D 1;=0D +=0D + // Note: SerialIoDevMode default is satisfactory, but not entirely accur= ate.=0D + // Board has no GPIO expander on I2C4 (despite SetupUtility claim= =0D + // that it does - this appears to be static text?) and is UART0 me= rely supporting=0D + // the UART2 devfn?=0D +=0D + // Acer IDs (TODO: "Newgate" IDs)=0D +//FIXME FspsUpd->FspsConfig.DefaultSvid =3D 0x1025;=0D +//FIXME FspsUpd->FspsConfig.DefaultSid =3D 0x1037;=0D + PchGeneralConfig->SubSystemVendorId =3D 0x1025;=0D + PchGeneralConfig->SubSystemId =3D 0x1037;=0D +=0D + /* System Agent config */=0D + // Set the Thermal Control Circuit (TCC) activation value to 97C=0D + // even though FSP integration guide says to set it to 100C for SKL-U=0D + // (offset at 0), because when the TCC activates at 100C, the CPU=0D + // will have already shut itself down from overheating protection.=0D + CpuPowerMgmtBasicConfig->TccActivationOffset =3D 3;=0D +=0D + // VR Slew rate setting for improving audible noise=0D + CpuPowerMgmtVrConfig->AcousticNoiseMitigation =3D 1;=0D + CpuPowerMgmtVrConfig->SlowSlewRateForIa =3D 3; // Fast/16=0D + CpuPowerMgmtVrConfig->SlowSlewRateForGt =3D 3; // Fast/16=0D + CpuPowerMgmtVrConfig->SlowSlewRateForSa =3D 0; // Fast/2=0D + CpuPowerMgmtVrConfig->FastPkgCRampDisableIa =3D 0;=0D + CpuPowerMgmtVrConfig->FastPkgCRampDisableGt =3D 0;=0D + CpuPowerMgmtVrConfig->FastPkgCRampDisableSa =3D 0;=0D +=0D + // VR domain configuration (copied from board port, before VR config mov= ed=0D + // to SoC. Should match SKL-U (GT2, 15W) in the SKL-U datasheet, vol. 1= =0D + CpuPowerMgmtVrConfig->AcLoadline[SA_VR] =3D 1030; // 10.3mOhm (in 1/100= increments)=0D + CpuPowerMgmtVrConfig->DcLoadline[SA_VR] =3D 1030; // 10.3mOhm (in 1/100= increments)=0D + CpuPowerMgmtVrConfig->Psi1Threshold[SA_VR] =3D 80; // 20A (in 1/4 increm= ents)=0D + CpuPowerMgmtVrConfig->Psi2Threshold[SA_VR] =3D 16; // 4A (in 1/4 increme= nts)=0D + CpuPowerMgmtVrConfig->Psi3Threshold[SA_VR] =3D 4; // 1A (in 1/4 increme= nts)=0D + CpuPowerMgmtVrConfig->IccMax[SA_VR] =3D 18; // 4.5A (in 1/4 incre= ments)=0D + CpuPowerMgmtVrConfig->VrVoltageLimit[SA_VR] =3D 1520; // 1520mV=0D +=0D + CpuPowerMgmtVrConfig->AcLoadline[IA_VR] =3D 240; // 2.4mOhm (in 1/100 i= ncrements)=0D + CpuPowerMgmtVrConfig->DcLoadline[IA_VR] =3D 240; // 2.4mOhm (in 1/100 i= ncrements)=0D + CpuPowerMgmtVrConfig->Psi1Threshold[IA_VR] =3D 80; // 20A (in 1/4 increm= ents)=0D + CpuPowerMgmtVrConfig->Psi2Threshold[IA_VR] =3D 20; // 5A (in 1/4 increme= nts)=0D + CpuPowerMgmtVrConfig->Psi3Threshold[IA_VR] =3D 4; // 1A (in 1/4 increme= nts)=0D + CpuPowerMgmtVrConfig->IccMax[IA_VR] =3D 116; // 29A (in 1/4 increm= ents)=0D + CpuPowerMgmtVrConfig->VrVoltageLimit[IA_VR] =3D 1520; // 1520mV=0D +=0D + CpuPowerMgmtVrConfig->AcLoadline[GT_UNSLICED_VR] =3D 310; // 3.1mOhm (i= n 1/100 increments)=0D + CpuPowerMgmtVrConfig->DcLoadline[GT_UNSLICED_VR] =3D 310; // 3.1mOhm (i= n 1/100 increments)=0D + CpuPowerMgmtVrConfig->Psi1Threshold[GT_UNSLICED_VR] =3D 80; // 20A (in 1= /4 increments)=0D + CpuPowerMgmtVrConfig->Psi2Threshold[GT_UNSLICED_VR] =3D 20; // 5A (in 1/= 4 increments)=0D + CpuPowerMgmtVrConfig->Psi3Threshold[GT_UNSLICED_VR] =3D 4; // 1A (in 1/= 4 increments)=0D + CpuPowerMgmtVrConfig->IccMax[GT_UNSLICED_VR] =3D 124; // 31A (in 1= /4 increments)=0D + CpuPowerMgmtVrConfig->VrVoltageLimit[GT_UNSLICED_VR] =3D 1520; // 1520m= V=0D +=0D + CpuPowerMgmtVrConfig->AcLoadline[GT_SLICED_VR] =3D 310; // 3.1mOhm (in = 1/100 increments)=0D + CpuPowerMgmtVrConfig->DcLoadline[GT_SLICED_VR] =3D 310; // 3.1mOhm (in = 1/100 increments)=0D + CpuPowerMgmtVrConfig->Psi1Threshold[GT_SLICED_VR] =3D 80; // 20A (in 1/4= increments)=0D + CpuPowerMgmtVrConfig->Psi2Threshold[GT_SLICED_VR] =3D 20; // 5A (in 1/4 = increments)=0D + CpuPowerMgmtVrConfig->Psi3Threshold[GT_SLICED_VR] =3D 4; // 1A (in 1/4 = increments)=0D + CpuPowerMgmtVrConfig->IccMax[GT_SLICED_VR] =3D 124; // 31A (in 1/4= increments)=0D + CpuPowerMgmtVrConfig->VrVoltageLimit[GT_SLICED_VR] =3D 1520; // 1520mV= =0D +=0D + // PL1, PL2 override 35W, PL4 override 43W (in 125 mW increments)=0D + CpuPowerMgmtBasicConfig->PowerLimit1 =3D 280;=0D + CpuPowerMgmtBasicConfig->PowerLimit2Power =3D 280;=0D + CpuPowerMgmtBasicConfig->PowerLimit4 =3D 344;=0D +=0D + // ISL95857 VR=0D + // Send VR specific command for PS4 exit issue=0D + CpuPowerMgmtVrConfig->SendVrMbxCmd1 =3D 2;=0D + // Send VR mailbox command for IA/GT/SA rails=0D +//FIXME FspsUpd->FspsConfig.IslVrCmd =3D 2;=0D +=0D + /* Skycam config */=0D +// FspsUpd->FspsConfig.SaImguEnable =3D 0;=0D +// FspsUpd->FspsConfig.PchCio2Enable =3D 0;=0D +=0D + /* Sensor hub config */=0D +// FspsUpd->FspsConfig.PchIshEnable =3D 0;=0D +=0D + /* xHCI config */=0D +// FspsUpd->FspsConfig.SsicPortEnable =3D 0;=0D + // Configure USB2 ports in two blocks=0D + for (int i =3D 0; i < 3; i++) {=0D + UsbConfig->PortUsb20[i].Afe.Txiset =3D 0x2; // 16.9mV=0D + UsbConfig->PortUsb20[i].Afe.Predeemp =3D 1; // De-emphasis on=0D + UsbConfig->PortUsb20[i].Afe.Petxiset =3D 0x3;// 28.15mV=0D + UsbConfig->PortUsb20[i].Afe.Pehalfbit =3D 1; // Half-bit=0D + }=0D + for (int i =3D 3; i < 9; i++) {=0D + UsbConfig->PortUsb20[i].Afe.Txiset =3D 0; // 0mV=0D + UsbConfig->PortUsb20[i].Afe.Predeemp =3D 0x2;// Pre-emphasis and de-em= phasis on=0D + UsbConfig->PortUsb20[i].Afe.Petxiset =3D 0x7;// 56.3mV=0D + UsbConfig->PortUsb20[i].Afe.Pehalfbit =3D 1; // Half-bit=0D + }=0D + // Configure all USB3 ports=0D + for (int i =3D 0; i < 4; i++) {=0D + UsbConfig->PortUsb30[i].HsioTxDeEmphEnable =3D 1;=0D + UsbConfig->PortUsb30[i].HsioTxDeEmph =3D 0x29; // Default (approximat= ely -3.5dB de-emphasis)=0D + }=0D + // Disable all OC pins=0D + for (int i =3D 0; i < 9; i++) {=0D + UsbConfig->PortUsb20[i].OverCurrentPin =3D PchUsbOverCurrentPinSkip;=0D + }=0D + for (int i =3D 0; i < 4; i++) {=0D + UsbConfig->PortUsb30[i].OverCurrentPin =3D PchUsbOverCurrentPinSkip;=0D + }=0D +=0D + /* xDCI config */=0D +// FspsUpd->FspsConfig.XdciEnable =3D 0;=0D +=0D + /* SATA config */=0D + // This is a hard silicon requirement, discovered several times by coreb= oot boards=0D + SataConfig->PwrOptEnable =3D 1;=0D +=0D + /* PCIe config */=0D + // Port 1 (dGPU; x4)=0D + PchPcieConfig->RootPort[0].AdvancedErrorReporting =3D 1;=0D + PchPcieConfig->RootPort[0].LtrEnable =3D 1;=0D + PchPcieConfig->RootPort[0].ClkReqSupported =3D 1;=0D + PchPcieConfig->RootPort[0].ClkReqNumber =3D 0x0;=0D + PchPcieConfig->RootPort[0].MaxPayload =3D PchPcieMaxPayload256;=0D + // Port 7 (NGFF; x2)=0D + PchPcieConfig->RootPort[6].AdvancedErrorReporting =3D 1;=0D + PchPcieConfig->RootPort[6].LtrEnable =3D 1;=0D + PchPcieConfig->RootPort[6].ClkReqSupported =3D 1;=0D + PchPcieConfig->RootPort[6].ClkReqNumber =3D 0x3;=0D + PchPcieConfig->RootPort[6].MaxPayload =3D PchPcieMaxPayload256;=0D + // Port 9 (LAN)=0D + PchPcieConfig->RootPort[8].AdvancedErrorReporting =3D 1;=0D + PchPcieConfig->RootPort[8].LtrEnable =3D 1;=0D + PchPcieConfig->RootPort[8].ClkReqSupported =3D 1;=0D + PchPcieConfig->RootPort[8].ClkReqNumber =3D 0x1;=0D + PchPcieConfig->RootPort[8].MaxPayload =3D PchPcieMaxPayload256;=0D + // Port 10 (WLAN)=0D + PchPcieConfig->RootPort[9].AdvancedErrorReporting =3D 1;=0D + PchPcieConfig->RootPort[9].LtrEnable =3D 1;=0D + PchPcieConfig->RootPort[9].ClkReqSupported =3D 1;=0D + PchPcieConfig->RootPort[9].ClkReqNumber =3D 0x2;=0D + PchPcieConfig->RootPort[9].MaxPayload =3D PchPcieMaxPayload256;=0D + // L0s is broken/unnecessary at this Speed (AER: corrected errors); TODO= : Prefer PcieDeviceTable=0D +// PchPcieConfig->RootPort[9].Aspm =3D PchPcieAspmL1;=0D +=0D + /* LPC config */=0D + // EC/KBC requires continuous mode=0D + PmConfig->LpcClockRun =3D 1;=0D + SerialIrqConfig->SirqMode =3D PchContinuousMode;=0D +=0D + /* HDA config */=0D + HdAudioConfig->DspEndpointDmic =3D PchHdaDmic1chArray;=0D +=0D + /* SCS config */=0D + // Although platform NVS area shows this enabled, the SD card reader is = connected over USB, not SCS=0D +// FspsUpd->FspsConfig.ScsEmmcEnabled =3D 0;=0D +// FspsUpd->FspsConfig.ScsSdCardEnabled =3D 0;=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Int= el/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUp= dateLib/PeiSiliconPolicyUpdateLib.c index 5cc7c03c6146..5c601c7e2991 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c @@ -28,6 +28,39 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =0D #include =0D =0D +//=0D +// Function prototypes=0D +//=0D +/**=0D + Performs the remainder of board-specific FSP Policy initialization.=0D +=0D + @param[in] Policy - Policy PPI pointer.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspBoardPolicyUpdatePreMem (=0D + IN VOID *Policy=0D + );=0D +=0D +/**=0D + Performs the remainder of board-specific FSP Policy initialization.=0D +=0D + @param[in] Policy - Policy PPI pointer.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspBoardPolicyUpdate (=0D + IN VOID *Policy=0D + );=0D +=0D /**=0D Get the next microcode patch pointer.=0D =0D @@ -461,6 +494,9 @@ SiliconPolicyUpdatePreMem ( // Update PCD policy=0D //=0D InstallPlatformHsioPtssTable (Policy);=0D +=0D + // Board-specific policy overrides=0D + PeiFspBoardPolicyUpdatePreMem (Policy);=0D }=0D =0D return Policy;=0D @@ -543,6 +579,11 @@ SiliconPolicyUpdatePostMem ( if (CpuConfig !=3D NULL) {=0D CpuConfig->MicrocodePatchAddress =3D PlatformCpuLocateMicrocodePatch (= );=0D }=0D +=0D + if (Policy !=3D NULL) {=0D + // Board-specific policy overrides=0D + PeiFspBoardPolicyUpdate (Policy);=0D + }=0D return Policy;=0D }=0D =0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/I= ntel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicy= UpdateLib/PeiSiliconPolicyUpdateLib.inf index 97ec70f611b1..1daca8de1e84 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -40,8 +40,10 @@ =0D [Sources]=0D PeiSiliconPolicyUpdateLib.c=0D + PeiBoardPolicyUpdate.c=0D =0D [Guids]=0D + gMemoryConfigGuid=0D gMemoryConfigNoCrcGuid=0D gTianoLogoGuid ## CONSUMES=0D gGraphicsPeiConfigGuid ## CONSUMES=0D @@ -49,12 +51,26 @@ gHsioPciePreMemConfigGuid ## CONSUMES=0D gHsioSataPreMemConfigGuid ## CONSUMES=0D gSaMiscPeiPreMemConfigGuid ## CONSUMES=0D + gLockDownConfigGuid=0D + gPchGeneralConfigGuid=0D + gCpuPowerMgmtBasicConfigGuid=0D + gCpuPowerMgmtVrConfigGuid=0D + gUsbConfigGuid=0D + gSataConfigGuid=0D + gPcieRpConfigGuid=0D + gPmConfigGuid=0D + gSerialIrqConfigGuid=0D + gHdAudioConfigGuid=0D =0D [Pcd]=0D gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize=0D +# gSiPkgTokenSpaceGuid.PcdTsegSize=0D gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase=0D gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd ## CONSUME= S=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig ## CONSUME= S=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved ## CONSUME= S=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSUME= S=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSUME= S=0D gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## CONSUME= S=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_bo= ard.py b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_board.= py deleted file mode 100644 index 41668120f109..000000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_board.py +++ /dev/null @@ -1,68 +0,0 @@ -# @ build_board.py=0D -# This is a sample code provides Optional dynamic imports=0D -# of build functions to the BuildBios.py script=0D -#=0D -# Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D -# SPDX-License-Identifier: BSD-2-Clause-Patent=0D -#=0D -=0D -"""=0D -This module serves as a sample implementation of the build extension=0D -scripts=0D -"""=0D -=0D -=0D -def pre_build_ex(config, functions):=0D - """Additional Pre BIOS build function=0D -=0D - :param config: The environment variables to be used in the build proce= ss=0D - :type config: Dictionary=0D - :param functions: A dictionary of function pointers=0D - :type functions: Dictionary=0D - :returns: nothing=0D - """=0D - print("pre_build_ex")=0D - return None=0D -=0D -=0D -def build_ex(config, functions):=0D - """Additional BIOS build function=0D -=0D - :param config: The environment variables to be used in the build proce= ss=0D - :type config: Dictionary=0D - :param functions: A dictionary of function pointers=0D - :type functions: Dictionary=0D - :returns: config dictionary=0D - :rtype: Dictionary=0D - """=0D - print("build_ex")=0D - return None=0D -=0D -=0D -def post_build_ex(config, functions):=0D - """Additional Post BIOS build function=0D -=0D - :param config: The environment variables to be used in the post=0D - build process=0D - :type config: Dictionary=0D - :param functions: A dictionary of function pointers=0D - :type functions: Dictionary=0D - :returns: config dictionary=0D - :rtype: Dictionary=0D - """=0D - print("post_build_ex")=0D - return None=0D -=0D -=0D -def clean_ex(config, functions):=0D - """Additional clean function=0D -=0D - :param config: The environment variables to be used in the build proce= ss=0D - :type config: Dictionary=0D - :param functions: A dictionary of function pointers=0D - :type functions: Dictionary=0D - :returns: config dictionary=0D - :rtype: Dictionary=0D - """=0D - print("clean_ex")=0D - return None=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_co= nfig.cfg b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_conf= ig.cfg index f6ae4b342aa0..ea3cdb6d72a5 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.cfg +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.cfg @@ -1,5 +1,5 @@ # @ build_config.cfg=0D -# This is the KabylakeRvp3 board specific build settings=0D +# This is the Acer Aspire VN7-572G board specific build settings=0D #=0D # Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D @@ -7,16 +7,15 @@ =0D =0D [CONFIG]=0D -WORKSPACE_PLATFORM_BIN =3D=0D +WORKSPACE_PLATFORM_BIN =3D edk2-non-osi/Platform/Intel/KabylakeOpenBoardBi= nPkg=0D EDK_SETUP_OPTION =3D=0D openssl_path =3D=0D PLATFORM_BOARD_PACKAGE =3D KabylakeOpenBoardPkg=0D -PROJECT =3D KabylakeOpenBoardPkg/KabylakeRvp3=0D -BOARD =3D KabylakeRvp3=0D -FLASH_MAP_FDF =3D KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/FlashMapIn= clude.fdf=0D -PROJECT_DSC =3D KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc=0D -BOARD_PKG_PCD_DSC =3D KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.ds= c=0D -ADDITIONAL_SCRIPTS =3D KabylakeOpenBoardPkg/KabylakeRvp3/build_board.py=0D +PROJECT =3D KabylakeOpenBoardPkg/AspireVn7Dash572G=0D +BOARD =3D AspireVn7Dash572G=0D +FLASH_MAP_FDF =3D KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/Flash= MapInclude.fdf=0D +PROJECT_DSC =3D KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc=0D +BOARD_PKG_PCD_DSC =3D KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgP= cd.dsc=0D PrepRELEASE =3D DEBUG=0D SILENT_MODE =3D FALSE=0D EXT_CONFIG_CLEAR =3D=0D --=20 2.31.1