From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web09.11385.1628181369586880046 for ; Thu, 05 Aug 2021 09:36:09 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: jeremy.linton@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1D9DC31B; Thu, 5 Aug 2021 09:36:09 -0700 (PDT) Received: from u200856.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B099D3F66F; Thu, 5 Aug 2021 09:36:08 -0700 (PDT) From: "Jeremy Linton" To: devel@edk2.groups.io Cc: pete@akeo.ie, ardb+tianocore@kernel.org, awarkentin@vmware.com, Sunny.Wang@arm.com, samer.el-haj-mahmoud@arm.com, Jeremy Linton , =?UTF-8?q?Ren=C3=A9=20Treffer?= Subject: [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4 Date: Thu, 5 Aug 2021 11:35:50 -0500 Message-Id: <20210805163551.488035-5-jeremy.linton@arm.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210805163551.488035-1-jeremy.linton@arm.com> References: <20210805163551.488035-1-jeremy.linton@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable The CM4 has an actual pcie slot, so we need to move the linkup check to the configuration probe logic. Further the device restriction logic needs to be relaxed to support downstream PCIe switches. Suggested-by: Ren=C3=A9 Treffer Signed-off-by: Jeremy Linton --- .../Bcm2711PciHostBridgeLibConstructor.c | 5 ----- .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 24 +++++++++++++++-= ------ 2 files changed, 17 insertions(+), 12 deletions(-) diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm= 2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2= 711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c index 8587d2d36d..4d4c584726 100644 --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711Pci= HostBridgeLibConstructor.c +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711Pci= HostBridgeLibConstructor.c @@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor ( } while (((Data & 0x30) !=3D 0x030) && (Timeout)); DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=3D%x) Timeout=3D%d\n",= Data, Timeout)); =20 - if ((Data & 0x30) !=3D 0x30) { - DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=3D%x)\n", Data)); - return EFI_DEVICE_ERROR; - } - if ((Data & 0x80) !=3D 0x80) { DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=3D%x)\n", Dat= a)); return EFI_UNSUPPORTED; diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSeg= mentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegm= entLib.c index 44ce3b4b99..3ccc131eab 100644 --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib= .c +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib= .c @@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase ( UINT64 Base; UINT64 Offset; UINT32 Dev; + UINT32 Bus; + UINT32 Data; =20 Base =3D PCIE_REG_BASE; Offset =3D Address & 0xFFF; /* Pick off the 4k register offset= */ @@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase ( Base +=3D PCIE_EXT_CFG_DATA; if (mPciSegmentLastAccess !=3D Address) { Dev =3D EFI_PCI_ADDR_DEV (Address); + Bus =3D EFI_PCI_ADDR_BUS (Address); + =20 /* - * Scan things out directly rather than translating the "bus" to a= device, etc.. - * only we need to limit each bus to a single device. + * There can only be a single device on bus 1 (downstream of root)= . + * Subsequent busses (behind a PCIe switch) can have more. */ - if (Dev < 1) { - MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); - mPciSegmentLastAccess =3D Address; - } else { - mPciSegmentLastAccess =3D 0; + if (Dev > 0 && (Bus < 2)) { return 0xFFFFFFFF; } + + /* Don't probe slots if the link is down */ + Data =3D MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS); + if ((Data & 0x30) !=3D 0x30) { + DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=3D%x)\n", Da= ta)); + return 0xFFFFFFFF; + } + + MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); + mPciSegmentLastAccess =3D Address; } } return Base + Offset; --=20 2.13.7