From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) by mx.groups.io with SMTP id smtpd.web12.1118.1628294371193889638 for ; Fri, 06 Aug 2021 16:59:31 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=uDxm6Ru7; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.167.49, mailfrom: mw@semihalf.com) Received: by mail-lf1-f49.google.com with SMTP id n17so18426133lft.13 for ; Fri, 06 Aug 2021 16:59:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=KdjmHYSlazVtyZugQ4jCssuYvqjaBOY8AW/p5aRcvzE=; b=uDxm6Ru7HtRNukdcQ7xyfLSuTSRaK2vXZaxbgci3gN6qsxeDftsZR0X7S6Tp4KMUCC 51Oc1F9uS1jQmopsgbR89H34P8DuDZhOhIPQrxUmvqRhZz+Gg9dXCgWl5gTM3Lh/wy3F aEqGZw5b/F2ZydGlzu0O7Z8lTLeTDH1+YBQ6VSzoSSX+ey2YCg5aAiCqGICcq+IrnCWY ouTd2BuJiwiXNc6vVgVgLNeZyHwjYARP0C+setYLnShvyQVZ4W6uaCzCzBugDhFm1uMV tm+bl8t0TsyHyWlXW0+e2hgfKQJV7Ztfm0FO04+DG2ivPCns5bNmQ0Qah1J/7V57rFsP sRLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=KdjmHYSlazVtyZugQ4jCssuYvqjaBOY8AW/p5aRcvzE=; b=X/Tk0TJMfrvsmRJk9VQdn6a63nDlFUBbaIf7VZt6joa8680yM+XYgFLBIFc3ZM9ZU/ QfG61TxsOMTSqdBLZqH09+go3lCbPNcXp4yWC7l84tXoLQTqu0SG1gKCO54QzZyP01FG 9vDsq7H7/mRx/gCq7dg/xrBsqOUWIA3Tc9WzGEJEhA5rpa1TMJdqymPjab1+MPQkvBsc 5+7sa4Pz7zK5a4diyE8N30g57dAs5SQMKsI79tfZ66uefiEA2K48Ts2YEtZIABvE8Fgq 05++r9QrGZ2AFA8I4S8HaEcwlRVTz8i07mICoMkLEsStkmioRq2T8VV+ugqDc+FFT6N7 4Ktg== X-Gm-Message-State: AOAM5338ngYdqIzlMOXJTSS5YJyS/4uZcd3FcY4GZ2pas+YdKyuxPj0K PrV4MThr8BKSXyJ1UbIENrn9KiQPKcZZdAPE X-Google-Smtp-Source: ABdhPJwpUYHYwQ1x1lCL1KsdqBOvrZ+JOyA+BihIl3QctbeBgKT2QEVA4+etWZh/tDyo/yOsbPpkcw== X-Received: by 2002:ac2:5224:: with SMTP id i4mr5383080lfl.311.1628294369300; Fri, 06 Aug 2021 16:59:29 -0700 (PDT) Return-Path: Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id c11sm805075ljr.1.2021.08.06.16.59.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Aug 2021 16:59:28 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, alon.rotman@solid-run.com, Marcin Wojtas Subject: [edk2-platforms PATCH 0/4] SolidRun CEx7 Evaluation Board support Date: Sat, 7 Aug 2021 01:59:01 +0200 Message-Id: <20210806235905.3327396-1-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi, This patchset introduces support for the CEx7 Evaluation Board Support, together with the ACPI tables and DT (edk2-non-osi patch). Additional patch toggles the default HW description to ACPI for all platforms based on SoCs. Supported interaces: * SPI flash & memory-mapped variable storage access * uSD * eMMC * 7x PCIE root complex * USB * Networking: * 1Gbps RGMII via PHY * 2500Base-X via quad 1Gpbs switch * 5Gbps via SFP cage and PHY The patches are also available on public branches: https://github.com/semihalf-wojtas-marcin/edk2-platforms/commits/cex7-r20210806 https://github.com/semihalf-wojtas-marcin/edk2-non-osi/commits/cex7-r20210806 I would appreciate any comments or remarks. Best regards, Marcin Marcin Wojtas (3): edk2-platforms: Marvell: Armada7k8k/OcteonTx: Select ACPI description as a default SolidRun/Cn913xCEx7Eval: Add ACPI support SolidRun/Cn913xCEx7Eval: Add platform support edk2-non-osi: SolidRun/Cn913xCEx7Eval: Add DeviceTree Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc | 54 ++ Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc | 64 +++ Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc | 64 +++ Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc | 68 +++ Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 7 + Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc | 57 +++ Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf | 30 ++ Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf | 38 ++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf | 61 +++ Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.h | 30 ++ Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.h | 13 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h | 9 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h | 114 +++++ Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.c | 294 +++++++++++ Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 89 ++++ Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc | 17 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl | 383 +++++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl | 493 +++++++++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl | 515 ++++++++++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl | 120 +++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc | 74 +++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc | 87 ++++ 22 files changed, 2681 insertions(+) create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.h create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.c create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.c create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc -- 2.29.0