From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) by mx.groups.io with SMTP id smtpd.web12.2134.1628365054831439331 for ; Sat, 07 Aug 2021 12:37:35 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=dASSf1NL; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.167.52, mailfrom: mw@semihalf.com) Received: by mail-lf1-f52.google.com with SMTP id g13so25220622lfj.12 for ; Sat, 07 Aug 2021 12:37:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=EyOP+33+VPPjupKIyV2NUEs0P2Uy3WtUeAjMYco18xo=; b=dASSf1NLWbNKNajZhj9a7nFTh7JBSjWOLiYqEdeHY+5tt63dFMyNIj1LuqAJiByhnO rMPLCV7Kd9rnLhTdApx3WAov9oFIlZU3L/HSlJvN869OY6yRh/HQmf5SwNreqF5zWC40 4dbMt6hZKnfiKVfiO8Q3XZlpDzmUPRsX7nb5OQUFn6ZWasHAUYqoTyrPyoE15B/O6DnA rZh2FblsH0nUiXsLf24LpgrEe4kj/c0RY8DYjAytdeedNVVdcvKD3Ovbm/1sDYBHd1Ky 4hp81jVWOvbLUVzG2K1xDdV5xWMDo5qE/jB4HjlL6dTmA9g4ihNE/ZFBifuys6y5Wcp0 Gh6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=EyOP+33+VPPjupKIyV2NUEs0P2Uy3WtUeAjMYco18xo=; b=EjIGGoyP34XtJq1D7prVM6YZUg6E9VhdGAvM2iKRLpL9ghZL/B0f2lw+SUsBrpclAV FzZSKJfH9PUCSON7TXBz18f5WyWcmDo4vWLnHILLuIsiZI7/INuhjIDGPc2xbMgzijLF og4tJvRYxT2J5ipv4TEd1eqH84TGQLLLoyYbmYDWT9+XYZebhccJRj3NiUFXC7fsaCLy LHlqmDkTgasDTOevaLpp81d1A5FcrKIKfyw4XBLqR6kfXoVvlDOOMSJIXIIGjPIJhwzm OJ/8vJEL+IjLmQI5fXno19NJaGLhWxDeBr2DdS1futNfJaLbG3qSuk3RzgWp2tld96jn 4zEw== X-Gm-Message-State: AOAM5310AeL5nRUMHcte/fWBWalqPKjUn/to5We8s/cYhsiQYnFYLcut QrxcKupoM2Lh0m+9xE48H/FGhI+Gminu/8un X-Google-Smtp-Source: ABdhPJya5m9j5qqqG/s1CTP6r2bJDZ8WMNDx4Z8elREVum2OSFqtPtAwpEVianT7rTDIIY6rv/3TWA== X-Received: by 2002:ac2:5445:: with SMTP id d5mr2333651lfn.256.1628365052806; Sat, 07 Aug 2021 12:37:32 -0700 (PDT) Return-Path: Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id bq33sm103635lfb.88.2021.08.07.12.37.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Aug 2021 12:37:32 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, alon.rotman@solid-run.com, Marcin Wojtas Subject: [edk2-platforms PATCH v2 0/4] SolidRun CEx7 Evaluation Board support Date: Sat, 7 Aug 2021 21:36:37 +0200 Message-Id: <20210807193641.3355697-1-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi, The second version comes with a minor improvement, which is a result of the TF-A support update and changes around the default IO windows configuration. The patches are also available on public branches: https://github.com/semihalf-wojtas-marcin/edk2-platforms/commits/cex7-r20210807 https://github.com/semihalf-wojtas-marcin/edk2-non-osi/commits/cex7-r20210806 I would appreciate any comments or remarks. Best regards, Marcin Changelog: v1->v2: * 3/4: update IO windows reconfiguration, in order to align to the TF-A changes. Marcin Wojtas (3): edk2-platforms: Marvell: Armada7k8k/OcteonTx: Select ACPI description as a default SolidRun/Cn913xCEx7Eval: Add ACPI support SolidRun/Cn913xCEx7Eval: Add platform support edk2-non-osi: SolidRun/Cn913xCEx7Eval: Add DeviceTree Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc | 54 ++ Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc | 64 +++ Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc | 64 +++ Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc | 68 +++ Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 7 + Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc | 57 +++ Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf | 30 ++ Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf | 38 ++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf | 61 +++ Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.h | 31 ++ Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.h | 13 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h | 9 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h | 114 +++++ Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.c | 294 +++++++++++ Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 89 ++++ Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc | 17 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl | 383 +++++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl | 493 +++++++++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl | 515 ++++++++++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl | 120 +++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc | 74 +++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc | 87 ++++ 22 files changed, 2682 insertions(+) create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.h create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.c create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.c create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc -- 2.29.0