From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lj1-f173.google.com (mail-lj1-f173.google.com [209.85.208.173]) by mx.groups.io with SMTP id smtpd.web08.2148.1628365057558376314 for ; Sat, 07 Aug 2021 12:37:38 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=QLO14ZGy; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.208.173, mailfrom: mw@semihalf.com) Received: by mail-lj1-f173.google.com with SMTP id h2so5037343lji.6 for ; Sat, 07 Aug 2021 12:37:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CXnUG9Px6SF2jSWRy04l6zqp+fcSVlv+WGhKPv1We/M=; b=QLO14ZGy3oknTLFtvnk3mFPCOIQ1Is6euTpaAHTlttvMAa/6tEjoKMV6WoldmNjfpP BMo6qhUYiLNH/COpJG3WkUe1OFH+wDht0umCHrp9joB4qN4gLiRWY8qAHp4Jm0NhyFMu 0QQB4u5LH8xixM5TKQJY8Qcnwe+5R4NjKuODmP4pB1EyKyTNvKX+c1PKdLiT8kH0EbWS wX8SMJny0vNh2E+PZyKZ1P+gsuBEUSzVA+LdUmXCpIOed2Z6MRMHYzqcDmHoifJivqHH ML50HbBtuh8IlXXW91X1I2opowQ2dBMY5MEKwFBAZ1TvQW7zp4nQkpXrIZLy/QZFLMe9 Npvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CXnUG9Px6SF2jSWRy04l6zqp+fcSVlv+WGhKPv1We/M=; b=KvGhhvXSP9GpPh++u640dxLygWIjffgMeZhusKwKy18shdmuxDE7HGcrUmYESZ4gy6 b4C2X6K+TLLL1TTHAPh+8R2tC9OwirfbTHvuuemGwhRkbYqu9mQ2zWoKlzb7rSyp6w5F ZqwGJjEDIgacvo5NAlJ+QcryQ9BaSBUkySjx8MVm9Qws/pJ2nrXpOiktdN1B1IAPWkF0 QRxpViaYgw/3/npHdO3Re35LVEREWCRXut/YeRXVzYHscuAZ7ZcnjZUCOnHM6Sr/tpaU MdG1T0KpaoFfk6TtomFSKS3eur9xciDfEeTGuKK5zXXel503SG4Qk+wbs68KRfzkkGKe 9V+Q== X-Gm-Message-State: AOAM531BOtFG0JJDsJDSqSvXTRx71/eH6WC7BjYpsAiAr/mpKZ3Jhv6u L70holJy/OLiOoZ+I+YTEwcPsF4ZEmnvAcSr X-Google-Smtp-Source: ABdhPJw7AOSRKnTwetXkgF6sXARsNRdLO8yvnGRo9BjFOX6yMQ82AtscNuWKAw0VieWoP5y0BTIQFg== X-Received: by 2002:a05:651c:245:: with SMTP id x5mr10250904ljn.92.1628365055511; Sat, 07 Aug 2021 12:37:35 -0700 (PDT) Return-Path: Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id bq33sm103635lfb.88.2021.08.07.12.37.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Aug 2021 12:37:34 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, alon.rotman@solid-run.com, Marcin Wojtas Subject: [edk2-platforms PATCH v2 2/3] SolidRun/Cn913xCEx7Eval: Add ACPI support Date: Sat, 7 Aug 2021 21:36:39 +0200 Message-Id: <20210807193641.3355697-3-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210807193641.3355697-1-mw@semihalf.com> References: <20210807193641.3355697-1-mw@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable This patch adds ACPI tables description for the SolidRun CN913x CEx7 Evaluation Board platform. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf = | 61 +++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h = | 9 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h = | 114 +++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl = | 383 +++++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl = | 493 +++++++++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl = | 515 ++++++++++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl = | 120 +++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc = | 74 +++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc = | 87 ++++ 9 files changed, 1856 insertions(+) create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.= inf create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/= Dbg2.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/= Pcie.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/= Cn9130EvalSsdt.asl create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/= Cn9131EvalSsdt.asl create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/= Cn9132EvalSsdt.asl create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/= Cn913xCEx7Dsdt.asl create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/= Dbg2.aslc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/= Mcfg.aslc diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf new file mode 100644 index 0000000000..27e7294014 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf @@ -0,0 +1,61 @@ +## @file=0D +# Component description file for PlatformAcpiTables module.=0D +#=0D +# ACPI table data and ASL sources required to boot the platform.=0D +#=0D +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
=0D +# Copyright (c) 2019, Marvell International Ltd. and its affiliates.
= =0D +# Copyright (c) 2021, Semihalf.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001B=0D + BASE_NAME =3D PlatformAcpiTables=0D + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD= =0D + MODULE_TYPE =3D USER_DEFINED=0D + VERSION_STRING =3D 1.0=0D +=0D +[Sources]=0D + Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl=0D + Cn913xCEx7Eval/Cn9130EvalSsdt.asl=0D + Cn913xCEx7Eval/Cn9131EvalSsdt.asl=0D + Cn913xCEx7Eval/Cn9132EvalSsdt.asl=0D + Cn913xCEx7Eval/Dbg2.aslc=0D + Cn913xCEx7Eval/Mcfg.aslc=0D + Fadt.aslc=0D + Gtdt.aslc=0D + Madt.aslc=0D + Pptt.aslc=0D + Spcr.aslc=0D +=0D +[Packages]=0D + ArmPkg/ArmPkg.dec=0D + ArmPlatformPkg/ArmPlatformPkg.dec=0D + EmbeddedPkg/EmbeddedPkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + MdePkg/MdePkg.dec=0D + Silicon/Marvell/Marvell.dec=0D +=0D +[FixedPcd]=0D + gArmPlatformTokenSpaceGuid.PcdCoreCount=0D +=0D + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum=0D + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum=0D + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum=0D + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum=0D +=0D + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase=0D + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum=0D + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase=0D +=0D + gArmTokenSpaceGuid.PcdGicDistributorBase=0D + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase=0D +=0D +[BuildOptions]=0D + *_*_*_ASLCC_FLAGS =3D -DCN9131=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h = b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h new file mode 100644 index 0000000000..a18b7c1396 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h @@ -0,0 +1,9 @@ +/**=0D +=0D + Copyright (C) 2021, Semihalf.=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#define CN913X_DBG2_UART_REG_BASE 0xF2702200=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h = b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h new file mode 100644 index 0000000000..592e47d0c4 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h @@ -0,0 +1,114 @@ +/**=0D +=0D + Copyright (C) 2019, Marvell International Ltd. and its affiliates.=0D + Copyright (C) 2021, Semihalf.=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#define CP0_PCI0_BUS_MIN 0x0=0D +#define CP0_PCI0_BUS_MAX 0x0=0D +#define CP0_PCI0_BUS_COUNT 0x1=0D +#define CP0_PCI0_MMIO32_BASE 0xC0000000=0D +#define CP0_PCI0_MMIO32_SIZE 0x20000000=0D +#define CP0_PCI0_MMIO32_MAX 0xDFFFFFFF=0D +#define CP0_PCI0_MMIO64_BASE 0x810000000=0D +#define CP0_PCI0_MMIO64_SIZE 0x80000000=0D +#define CP0_PCI0_MMIO64_MAX 0x88FFFFFFF=0D +#define CP0_PCI0_IO_BASE 0x0=0D +#define CP0_PCI0_IO_SIZE 0x10000=0D +#define CP0_PCI0_IO_TRANSLATION 0x80FF00000=0D +#define CP0_PCI0_ECAM_BASE 0x800008000=0D +#define CP0_PCI0_ECAM_SIZE 0x100000=0D +#define CP0_PCI0_ECAM_MAX 0x800107FFF=0D +=0D +#define CP1_PCI0_BUS_MIN 0x0=0D +#define CP1_PCI0_BUS_MAX 0x0=0D +#define CP1_PCI0_BUS_COUNT 0x1=0D +#define CP1_PCI0_MMIO32_BASE 0xE3000000=0D +#define CP1_PCI0_MMIO32_SIZE 0x1000000=0D +#define CP1_PCI0_MMIO32_MAX 0xE3FFFFFF=0D +#define CP1_PCI0_MMIO64_BASE 0x890000000=0D +#define CP1_PCI0_MMIO64_SIZE 0x10000000=0D +#define CP1_PCI0_MMIO64_MAX 0x89FFFFFFF=0D +#define CP1_PCI0_IO_BASE 0x0=0D +#define CP1_PCI0_IO_SIZE 0x10000=0D +#define CP1_PCI0_IO_TRANSLATION 0xE2F00000=0D +#define CP1_PCI0_ECAM_BASE 0xE2008000=0D +#define CP1_PCI0_ECAM_SIZE 0x100000=0D +=0D +#define CP1_PCI1_BUS_MIN 0x0=0D +#define CP1_PCI1_BUS_MAX 0x0=0D +#define CP1_PCI1_BUS_COUNT 0x1=0D +#define CP1_PCI1_MMIO32_BASE 0xE5000000=0D +#define CP1_PCI1_MMIO32_SIZE 0x1000000=0D +#define CP1_PCI1_MMIO32_MAX 0xE5FFFFFF=0D +#define CP1_PCI1_MMIO64_BASE 0x8A0000000=0D +#define CP1_PCI1_MMIO64_SIZE 0x10000000=0D +#define CP1_PCI1_MMIO64_MAX 0x8AFFFFFFF=0D +#define CP1_PCI1_IO_BASE 0x0=0D +#define CP1_PCI1_IO_SIZE 0x10000=0D +#define CP1_PCI1_IO_TRANSLATION 0xE4F00000=0D +#define CP1_PCI1_ECAM_BASE 0xE4008000=0D +#define CP1_PCI1_ECAM_SIZE 0x100000=0D +=0D +#define CP1_PCI2_BUS_MIN 0x0=0D +#define CP1_PCI2_BUS_MAX 0x0=0D +#define CP1_PCI2_BUS_COUNT 0x1=0D +#define CP1_PCI2_MMIO32_BASE 0xE7000000=0D +#define CP1_PCI2_MMIO32_SIZE 0x1000000=0D +#define CP1_PCI2_MMIO32_MAX 0xE7FFFFFF=0D +#define CP1_PCI2_MMIO64_BASE 0x8B0000000=0D +#define CP1_PCI2_MMIO64_SIZE 0x10000000=0D +#define CP1_PCI2_MMIO64_MAX 0x8BFFFFFFF=0D +#define CP1_PCI2_IO_BASE 0x0=0D +#define CP1_PCI2_IO_SIZE 0x10000=0D +#define CP1_PCI2_IO_TRANSLATION 0xE6F00000=0D +#define CP1_PCI2_ECAM_BASE 0xE6008000=0D +#define CP1_PCI2_ECAM_SIZE 0x100000=0D +=0D +#define CP2_PCI0_BUS_MIN 0x0=0D +#define CP2_PCI0_BUS_MAX 0x0=0D +#define CP2_PCI0_BUS_COUNT 0x1=0D +#define CP2_PCI0_MMIO32_BASE 0xEA000000=0D +#define CP2_PCI0_MMIO32_SIZE 0x1000000=0D +#define CP2_PCI0_MMIO32_MAX 0xEAFFFFFF=0D +#define CP2_PCI0_MMIO64_BASE 0x8C0000000=0D +#define CP2_PCI0_MMIO64_SIZE 0x10000000=0D +#define CP2_PCI0_MMIO64_MAX 0x8CFFFFFFF=0D +#define CP2_PCI0_IO_BASE 0x0=0D +#define CP2_PCI0_IO_SIZE 0x10000=0D +#define CP2_PCI0_IO_TRANSLATION 0xE9F00000=0D +#define CP2_PCI0_ECAM_BASE 0xE9008000=0D +#define CP2_PCI0_ECAM_SIZE 0x100000=0D +=0D +#define CP2_PCI1_BUS_MIN 0x0=0D +#define CP2_PCI1_BUS_MAX 0x0=0D +#define CP2_PCI1_BUS_COUNT 0x1=0D +#define CP2_PCI1_MMIO32_BASE 0xEC000000=0D +#define CP2_PCI1_MMIO32_SIZE 0x1000000=0D +#define CP2_PCI1_MMIO32_MAX 0xECFFFFFF=0D +#define CP2_PCI1_MMIO64_BASE 0x8D0000000=0D +#define CP2_PCI1_MMIO64_SIZE 0x10000000=0D +#define CP2_PCI1_MMIO64_MAX 0x8DFFFFFFF=0D +#define CP2_PCI1_IO_BASE 0x0=0D +#define CP2_PCI1_IO_SIZE 0x10000=0D +#define CP2_PCI1_IO_TRANSLATION 0xEBF00000=0D +#define CP2_PCI1_ECAM_BASE 0xEB008000=0D +#define CP2_PCI1_ECAM_SIZE 0x100000=0D +=0D +#define CP2_PCI2_BUS_MIN 0x0=0D +#define CP2_PCI2_BUS_MAX 0x0=0D +#define CP2_PCI2_BUS_COUNT 0x1=0D +#define CP2_PCI2_MMIO32_BASE 0xEE000000=0D +#define CP2_PCI2_MMIO32_SIZE 0x1000000=0D +#define CP2_PCI2_MMIO32_MAX 0xEEFFFFFF=0D +#define CP2_PCI2_MMIO64_BASE 0x8E0000000=0D +#define CP2_PCI2_MMIO64_SIZE 0x10000000=0D +#define CP2_PCI2_MMIO64_MAX 0x8EFFFFFFF=0D +#define CP2_PCI2_IO_BASE 0x0=0D +#define CP2_PCI2_IO_SIZE 0x10000=0D +#define CP2_PCI2_IO_TRANSLATION 0xEDF00000=0D +#define CP2_PCI2_ECAM_BASE 0xED008000=0D +#define CP2_PCI2_ECAM_SIZE 0x100000=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130E= valSsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130= EvalSsdt.asl new file mode 100644 index 0000000000..70bdecb620 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt= .asl @@ -0,0 +1,383 @@ +/** @file=0D +=0D + Differentiated System Description Table Fields (DSDT)=0D +=0D + Copyright (c) 2018, Linaro Ltd. All rights reserved.
=0D + Copyright (C) 2019, Marvell International Ltd. and its affiliates.
=0D + Copyright (C) 2021, Semihalf.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "Cn913xCEx7Eval/Dbg2.h"=0D +#include "Cn913xCEx7Eval/Pcie.h"=0D +#include "IcuInterrupts.h"=0D +=0D +DefinitionBlock ("Cn9130CEx7EvalSsdt.aml", "SSDT", 2, "MRVL", "CN913X", 3)= =0D +{=0D + Scope (_SB)=0D + {=0D + Device (MMC1)=0D + {=0D + Name (_HID, "MRVL0004") // _HID: Hardware ID=0D + Name (_UID, 0x01) // _UID: Unique ID=0D + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D +=0D + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D + {=0D + Memory32Fixed (ReadWrite,=0D + 0xF2780000, // Address Base (MMIO)=0D + 0x00000300, // Address Length=0D + )=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, )=0D + {=0D + CP_GIC_SPI_CP0_SDMMC=0D + }=0D + })=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "clock-frequency", 400000000 },=0D + Package () { "bus-width", 4 },=0D + Package () { "no-1-8-v", 0x1 },=0D + Package () { "broken-cd", 0x1 },=0D + }=0D + })=0D + }=0D +=0D + Device (XHC0)=0D + {=0D + Name (_HID, "PNP0D10") // _HID: Hardware ID=0D + Name (_UID, 0x00) // _UID: Unique ID=0D + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D +=0D + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D + {=0D + Memory32Fixed (ReadWrite,=0D + 0xF2500000, // Address Base (MMIO)=0D + 0x00004000, // Address Length=0D + )=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, )=0D + {=0D + CP_GIC_SPI_CP0_USB_H0=0D + }=0D + })=0D + }=0D +=0D + Device (XHC1)=0D + {=0D + Name (_HID, "PNP0D10") // _HID: Hardware ID=0D + Name (_UID, 0x01) // _UID: Unique ID=0D + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D +=0D + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D + {=0D + Memory32Fixed (ReadWrite,=0D + 0xF2510000, // Address Base (MMIO)=0D + 0x00004000, // Address Length=0D + )=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, )=0D + {=0D + CP_GIC_SPI_CP0_USB_H1=0D + }=0D + })=0D + }=0D +=0D + Device (COM2)=0D + {=0D + Name (_HID, "MRVL0001") // _HID: H= ardware ID=0D + Name (_CID, "HISI0031") // _CID: C= ompatible ID=0D + Name (_UID, 0x01) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_ADR, CN913X_DBG2_UART_REG_BASE) // _ADR: A= ddress=0D + Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings=0D + {=0D + Memory32Fixed (ReadWrite,=0D + CN913X_DBG2_UART_REG_BASE, // Address= Base=0D + 0x00000100, // Address= Length=0D + )=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, )=0D + {=0D + CP_GIC_SPI_CP0_UART2=0D + }=0D + })=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "clock-frequency", FixedPcdGet32 (PcdSe= rialClockRate) },=0D + Package () { "reg-io-width", 1 },=0D + Package () { "reg-shift", 2 },=0D + }=0D + })=0D + }=0D +=0D + Device (SMI0)=0D + {=0D + Name (_HID, "MRVL0100") // _HID: H= ardware ID=0D + Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Memory32Fixed (ReadWrite,=0D + 0xf212a200, // Address= Base=0D + 0x00000010, // Address= Length=0D + )=0D + })=0D + Device (PHY0)=0D + {=0D + Name (_ADR, 0x0)=0D + }=0D + }=0D +=0D + Device (PP20)=0D + {=0D + Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D + Name (_CCA, 0x01) // Cache-c= oherent controller=0D + Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)=0D + Memory32Fixed (ReadWrite, 0xf2129000 , 0xb000)=0D + Memory32Fixed (ReadWrite, 0xf2220000 , 0x800)=0D + })=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "clock-frequency", 333333333 },=0D + }=0D + })=0D + Device (ETH0)=0D + {=0D + Name (_ADR, 0x0)=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, )=0D + {=0D + CP_GIC_SPI_PP2_CP0_PORT0=0D + }=0D + })=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "port-id", 0 },=0D + Package () { "gop-port-id", 0 },=0D + Package () { "phy-mode", "10gbase-kr"},=0D + Package () { "managed", "in-band-status"},=0D + }=0D + })=0D + }=0D + Device (ETH1)=0D + {=0D + Name (_ADR, 0x0)=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, )=0D + {=0D + CP_GIC_SPI_PP2_CP0_PORT1=0D + }=0D + })=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "port-id", 1 },=0D + Package () { "gop-port-id", 2 },=0D + Package () { "phy-mode", "rgmii-id"},=0D + Package () { "phy-handle", \_SB.SMI0.PHY0},=0D + }=0D + })=0D + }=0D + Device (ETH2)=0D + {=0D + Name (_ADR, 0x0)=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, )=0D + {=0D + CP_GIC_SPI_PP2_CP0_PORT2=0D + }=0D + })=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "port-id", 2 },=0D + Package () { "gop-port-id", 3 },=0D + Package () { "phy-mode", "2500base-x"},=0D + },=0D + ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),=0D + Package () {=0D + Package () {"fixed-link", "LNK0"}=0D + }=0D + })=0D + Name (LNK0, Package(){ // Data-only subnode of port=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () {"speed", 2500},=0D + Package () {"full-duplex", 1}=0D + }=0D + })=0D + }=0D + }=0D +=0D + Device (RNG0)=0D + {=0D + Name (_HID, "PRP0001") // _HID= : Hardware ID=0D + Name (_UID, 0x00) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)=0D + {=0D + CP_GIC_SPI_CP0_EIP_RNG0=0D + }=0D + })=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "compatible", "inside-secure,safexcel-eip= 76" },=0D + }=0D + })=0D + }=0D +=0D + //=0D + // PCIe Root Bus=0D + //=0D + Device (PCI0)=0D + {=0D + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar= e ID=0D + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID=0D + Name (_SEG, 0x00) // _SEG: PCI Segment=0D + Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D + Name (_UID, 0x00) // _UID: Unique ID=0D + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_PRT, Package () // _PRT: PCI Routing Table=0D + {=0D + Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x1, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x2, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x3, 0x0, 0x40 }=0D + })=0D +=0D + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin= gs=0D + {=0D + Name (RBUF, ResourceTemplate ()=0D + {=0D + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P= osDecode,=0D + 0x0000, // Granularity= =0D + CP0_PCI0_BUS_MIN, // Range Minim= um=0D + CP0_PCI0_BUS_MAX, // Range Maxim= um=0D + 0x0000, // Translation= Offset=0D + CP0_PCI0_BUS_COUNT // Length=0D + )=0D + DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite,=0D + 0x00000000, // Granularity= =0D + CP0_PCI0_MMIO32_BASE, // Range Minim= um=0D + CP0_PCI0_MMIO32_MAX, // Range Maxim= um=0D + 0x00000000, // Translation= Offset=0D + CP0_PCI0_MMIO32_SIZE // Length=0D + )=0D + QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite,=0D + 0x0000000000000000, // Granularity= =0D + CP0_PCI0_MMIO64_BASE, // Range Minim= um=0D + CP0_PCI0_MMIO64_MAX, // Range Maxim= um=0D + 0x00000000, // Translation= Offset=0D + CP0_PCI0_MMIO64_SIZE // Length=0D + )=0D + QWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco= de, EntireRange,=0D + 0x00000000, // Granularity= =0D + CP0_PCI0_IO_BASE, // Range Minim= um=0D + 0x0000FFFF, // Range Maxim= um=0D + CP0_PCI0_IO_TRANSLATION, // Translation= Address=0D + CP0_PCI0_IO_SIZE, // Length=0D + ,=0D + ,=0D + ,=0D + TypeTranslation=0D + )=0D + })=0D + Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */=0D + } // Method(_CRS)=0D +=0D + Device (RES0)=0D + {=0D + Name (_HID, "PNP0C02")=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite,=0D + 0x0000000000000000, // Granularity= =0D + CP0_PCI0_ECAM_BASE, // Range Minim= um=0D + CP0_PCI0_ECAM_MAX, // Range Maxim= um=0D + 0x00000000, // Translation= Offset=0D + CP0_PCI0_ECAM_SIZE // Length=0D + )=0D + })=0D + }=0D + Name (SUPP, 0x00)=0D + Name (CTRL, 0x00)=0D + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap= abilities=0D + {=0D + CreateDWordField (Arg3, 0x00, CDW1)=0D + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03= dd766") /* PCI Host Bridge Device */))=0D + {=0D + CreateDWordField (Arg3, 0x04, CDW2)=0D + CreateDWordField (Arg3, 0x08, CDW3)=0D + Store (CDW2, SUPP) /* \_SB_.PCI0.SUPP */=0D + Store (CDW3, CTRL) /* \_SB_.PCI0.CTRL */=0D + If (LNotEqual (And (SUPP, 0x16), 0x16))=0D + {=0D + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI0.CTRL */=0D + }=0D +=0D + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI0.CTRL */=0D + If (LNotEqual (Arg1, One))=0D + {=0D + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI0._OSC.CDW1 */=0D + }=0D +=0D + If (LNotEqual (CDW3, CTRL))=0D + {=0D + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI0._OSC.CDW1 */=0D + }=0D +=0D + Store (CTRL, CDW3) /* \_SB_.PCI0._OSC.CDW3 */=0D + Return (Arg3)=0D + }=0D + Else=0D + {=0D + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI0._OSC.CDW1 */=0D + Return (Arg3)=0D + }=0D + } // Method(_OSC)=0D + }=0D + }=0D +}=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131E= valSsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131= EvalSsdt.asl new file mode 100644 index 0000000000..930134b86f --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt= .asl @@ -0,0 +1,493 @@ +/** @file=0D +=0D + Secondary System Description Table Fields (SSDT)=0D +=0D + Copyright (c) 2018, Linaro Ltd. All rights reserved.
=0D + Copyright (c) 2019, Marvell International Ltd. and its affiliates.
=0D + Copyright (C) 2021, Semihalf.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "Cn913xCEx7Eval/Pcie.h"=0D +#include "IcuInterrupts.h"=0D +=0D +DefinitionBlock ("Cn9131CEx7EvalSsdt.aml", "SSDT", 2, "MRVL", "CN913X", 3)= =0D +{=0D + Scope (_SB)=0D + {=0D + Device (AHC0)=0D + {=0D + Name (_HID, "LNRO001E") // _HID: Hardware ID=0D + Name (_UID, 0x00) // _UID: Unique ID=0D + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_CLS, Package (0x03) // _CLS: Class Code=0D + {=0D + 0x01,=0D + 0x06,=0D + 0x01=0D + })=0D +=0D + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D + {=0D + Memory32Fixed (ReadWrite,=0D + 0xF4540000, // Address Base (MMIO)=0D + 0x00030000, // Address Length=0D + )=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, )=0D + {=0D + CP_GIC_SPI_CP1_SATA_H0=0D + }=0D + })=0D + }=0D +=0D + Device (XHC2)=0D + {=0D + Name (_HID, "PNP0D10") // _HID: Hardware ID=0D + Name (_UID, 0x02) // _UID: Unique ID=0D + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D +=0D + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D + {=0D + Memory32Fixed (ReadWrite,=0D + 0xF4510000, // Address Base (MMIO)=0D + 0x00004000, // Address Length=0D + )=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, )=0D + {=0D + CP_GIC_SPI_CP1_USB_H1=0D + }=0D + })=0D + }=0D +=0D + Device (XSM1)=0D + {=0D + Name (_HID, "MRVL0101") // _HID: H= ardware ID=0D + Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Memory32Fixed (ReadWrite,=0D + 0xf412a600, // Address= Base=0D + 0x00000010, // Address= Length=0D + )=0D + })=0D + Device (PHY0)=0D + {=0D + Name (_ADR, 0x0)=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "compatible", "ethernet-phy-ieee802.3= -c45" },=0D + }=0D + })=0D + }=0D + }=0D +=0D + Device (PP21)=0D + {=0D + Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D + Name (_CCA, 0x01) // Cache-c= oherent controller=0D + Name (_UID, 0x01) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)=0D + Memory32Fixed (ReadWrite, 0xf4129000 , 0xb000)=0D + Memory32Fixed (ReadWrite, 0xf4220000 , 0x800)=0D + })=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "clock-frequency", 333333333 },=0D + }=0D + })=0D + Device (ETH0)=0D + {=0D + Name (_ADR, 0x0)=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, )=0D + {=0D + CP_GIC_SPI_PP2_CP1_PORT0=0D + }=0D + })=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "port-id", 0 },=0D + Package () { "gop-port-id", 0 },=0D + Package () { "phy-mode", "5gbase-r"},=0D + Package () { "phy-handle", \_SB.XSM1.PHY0},=0D + }=0D + })=0D + }=0D + }=0D +=0D + Device (RNG1)=0D + {=0D + Name (_HID, "PRP0001") // _HID= : Hardware ID=0D + Name (_UID, 0x01) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Memory32Fixed (ReadWrite, 0xF4760000, 0x7D)=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)=0D + {=0D + CP_GIC_SPI_CP1_EIP_RNG0=0D + }=0D + })=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "compatible", "inside-secure,safexcel-eip= 76" },=0D + }=0D + })=0D + }=0D +=0D + Device (PCI1)=0D + {=0D + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar= e ID=0D + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID=0D + Name (_SEG, 0x01) // _SEG: PCI Segment=0D + Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D + Name (_UID, 0x01) // _UID: Unique ID=0D + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_PRT, Package () // _PRT: PCI Routing Table=0D + {=0D + Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x1, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x2, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x3, 0x0, 0x40 }=0D + })=0D +=0D + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin= gs=0D + {=0D + Name (RBUF, ResourceTemplate ()=0D + {=0D + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P= osDecode,=0D + 0x0000, // Granularity= =0D + CP1_PCI0_BUS_MIN, // Range Minim= um=0D + CP1_PCI0_BUS_MAX, // Range Maxim= um=0D + 0x0000, // Translation= Offset=0D + CP1_PCI0_BUS_COUNT // Length=0D + )=0D + DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite,=0D + 0x00000000, // Granularity= =0D + CP1_PCI0_MMIO32_BASE, // Range Minim= um=0D + CP1_PCI0_MMIO32_MAX, // Range Maxim= um=0D + 0x00000000, // Translation= Offset=0D + CP1_PCI0_MMIO32_SIZE // Length=0D + )=0D + QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite,=0D + 0x0000000000000000, // Granularity= =0D + CP1_PCI0_MMIO64_BASE, // Range Minim= um=0D + CP1_PCI0_MMIO64_MAX, // Range Maxim= um=0D + 0x00000000, // Translation= Offset=0D + CP1_PCI0_MMIO64_SIZE // Length=0D + )=0D + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco= de, EntireRange,=0D + 0x00000000, // Granularity= =0D + CP1_PCI0_IO_BASE, // Range Minim= um=0D + 0x0000FFFF, // Range Maxim= um=0D + CP1_PCI0_IO_TRANSLATION, // Translation= Address=0D + CP1_PCI0_IO_SIZE, // Length=0D + ,=0D + ,=0D + ,=0D + TypeTranslation=0D + )=0D + })=0D + Return (RBUF) /* \_SB_.PCI1._CRS.RBUF */=0D + } // Method(_CRS)=0D +=0D + Device (RES0)=0D + {=0D + Name (_HID, "PNP0C02")=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Memory32Fixed (ReadWrite,=0D + CP1_PCI0_ECAM_BASE, // Range Minim= um=0D + CP1_PCI0_ECAM_SIZE // Length=0D + )=0D + })=0D + }=0D + Name (SUPP, 0x00)=0D + Name (CTRL, 0x00)=0D + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap= abilities=0D + {=0D + CreateDWordField (Arg3, 0x00, CDW1)=0D + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03= dd766") /* PCI Host Bridge Device */))=0D + {=0D + CreateDWordField (Arg3, 0x04, CDW2)=0D + CreateDWordField (Arg3, 0x08, CDW3)=0D + Store (CDW2, SUPP) /* \_SB_.PCI1.SUPP */=0D + Store (CDW3, CTRL) /* \_SB_.PCI1.CTRL */=0D + If (LNotEqual (And (SUPP, 0x16), 0x16))=0D + {=0D + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI1.CTRL */=0D + }=0D +=0D + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI1.CTRL */=0D + If (LNotEqual (Arg1, One))=0D + {=0D + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI1._OSC.CDW1 */=0D + }=0D +=0D + If (LNotEqual (CDW3, CTRL))=0D + {=0D + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI1._OSC.CDW1 */=0D + }=0D +=0D + Store (CTRL, CDW3) /* \_SB_.PCI1._OSC.CDW3 */=0D + Return (Arg3)=0D + }=0D + Else=0D + {=0D + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI1._OSC.CDW1 */=0D + Return (Arg3)=0D + }=0D + } // Method(_OSC)=0D + }=0D +=0D + Device (PCI2)=0D + {=0D + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar= e ID=0D + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID=0D + Name (_SEG, 0x02) // _SEG: PCI Segment=0D + Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D + Name (_UID, 0x02) // _UID: Unique ID=0D + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_PRT, Package () // _PRT: PCI Routing Table=0D + {=0D + Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x1, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x2, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x3, 0x0, 0x40 }=0D + })=0D +=0D + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin= gs=0D + {=0D + Name (RBUF, ResourceTemplate ()=0D + {=0D + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P= osDecode,=0D + 0x0000, // Granularity= =0D + CP1_PCI1_BUS_MIN, // Range Minim= um=0D + CP1_PCI1_BUS_MAX, // Range Maxim= um=0D + 0x0000, // Translation= Offset=0D + CP1_PCI1_BUS_COUNT // Length=0D + )=0D + DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite,=0D + 0x00000000, // Granularity= =0D + CP1_PCI1_MMIO32_BASE, // Range Minim= um=0D + CP1_PCI1_MMIO32_MAX, // Range Maxim= um=0D + 0x00000000, // Translation= Offset=0D + CP1_PCI1_MMIO32_SIZE // Length=0D + )=0D + QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite,=0D + 0x0000000000000000, // Granularity= =0D + CP1_PCI1_MMIO64_BASE, // Range Minim= um=0D + CP1_PCI1_MMIO64_MAX, // Range Maxim= um=0D + 0x00000000, // Translation= Offset=0D + CP1_PCI1_MMIO64_SIZE // Length=0D + )=0D + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco= de, EntireRange,=0D + 0x00000000, // Granularity= =0D + CP1_PCI1_IO_BASE, // Range Minim= um=0D + 0x0000FFFF, // Range Maxim= um=0D + CP1_PCI1_IO_TRANSLATION, // Translation= Address=0D + CP1_PCI1_IO_SIZE, // Length=0D + ,=0D + ,=0D + ,=0D + TypeTranslation=0D + )=0D + })=0D + Return (RBUF) /* \_SB_.PCI2._CRS.RBUF */=0D + } // Method(_CRS)=0D +=0D + Device (RES0)=0D + {=0D + Name (_HID, "PNP0C02")=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Memory32Fixed (ReadWrite,=0D + CP1_PCI1_ECAM_BASE, // Range Minim= um=0D + CP1_PCI1_ECAM_SIZE // Length=0D + )=0D + })=0D + }=0D + Name (SUPP, 0x00)=0D + Name (CTRL, 0x00)=0D + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap= abilities=0D + {=0D + CreateDWordField (Arg3, 0x00, CDW1)=0D + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03= dd766") /* PCI Host Bridge Device */))=0D + {=0D + CreateDWordField (Arg3, 0x04, CDW2)=0D + CreateDWordField (Arg3, 0x08, CDW3)=0D + Store (CDW2, SUPP) /* \_SB_.PCI2.SUPP */=0D + Store (CDW3, CTRL) /* \_SB_.PCI2.CTRL */=0D + If (LNotEqual (And (SUPP, 0x16), 0x16))=0D + {=0D + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI2.CTRL */=0D + }=0D +=0D + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI2.CTRL */=0D + If (LNotEqual (Arg1, One))=0D + {=0D + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI2._OSC.CDW1 */=0D + }=0D +=0D + If (LNotEqual (CDW3, CTRL))=0D + {=0D + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI2._OSC.CDW1 */=0D + }=0D +=0D + Store (CTRL, CDW3) /* \_SB_.PCI2._OSC.CDW3 */=0D + Return (Arg3)=0D + }=0D + Else=0D + {=0D + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI2._OSC.CDW1 */=0D + Return (Arg3)=0D + }=0D + } // Method(_OSC)=0D + }=0D +=0D + Device (PCI3)=0D + {=0D + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar= e ID=0D + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID=0D + Name (_SEG, 0x03) // _SEG: PCI Segment=0D + Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D + Name (_UID, 0x03) // _UID: Unique ID=0D + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_PRT, Package () // _PRT: PCI Routing Table=0D + {=0D + Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x1, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x2, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x3, 0x0, 0x40 }=0D + })=0D +=0D + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin= gs=0D + {=0D + Name (RBUF, ResourceTemplate ()=0D + {=0D + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P= osDecode,=0D + 0x0000, // Granularity= =0D + CP1_PCI2_BUS_MIN, // Range Minim= um=0D + CP1_PCI2_BUS_MAX, // Range Maxim= um=0D + 0x0000, // Translation= Offset=0D + CP1_PCI2_BUS_COUNT // Length=0D + )=0D + DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite,=0D + 0x00000000, // Granularity= =0D + CP1_PCI2_MMIO32_BASE, // Range Minim= um=0D + CP1_PCI2_MMIO32_MAX, // Range Maxim= um=0D + 0x00000000, // Translation= Offset=0D + CP1_PCI2_MMIO32_SIZE // Length=0D + )=0D + QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite,=0D + 0x0000000000000000, // Granularity= =0D + CP1_PCI2_MMIO64_BASE, // Range Minim= um=0D + CP1_PCI2_MMIO64_MAX, // Range Maxim= um=0D + 0x00000000, // Translation= Offset=0D + CP1_PCI2_MMIO64_SIZE // Length=0D + )=0D + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco= de, EntireRange,=0D + 0x00000000, // Granularity= =0D + CP1_PCI2_IO_BASE, // Range Minim= um=0D + 0x0000FFFF, // Range Maxim= um=0D + CP1_PCI2_IO_TRANSLATION, // Translation= Address=0D + CP1_PCI2_IO_SIZE, // Length=0D + ,=0D + ,=0D + ,=0D + TypeTranslation=0D + )=0D + })=0D + Return (RBUF) /* \_SB_.PCI3._CRS.RBUF */=0D + } // Method(_CRS)=0D +=0D + Device (RES0)=0D + {=0D + Name (_HID, "PNP0C02")=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Memory32Fixed (ReadWrite,=0D + CP1_PCI2_ECAM_BASE, // Range Minim= um=0D + CP1_PCI2_ECAM_SIZE // Length=0D + )=0D + })=0D + }=0D + Name (SUPP, 0x00)=0D + Name (CTRL, 0x00)=0D + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap= abilities=0D + {=0D + CreateDWordField (Arg3, 0x00, CDW1)=0D + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03= dd766") /* PCI Host Bridge Device */))=0D + {=0D + CreateDWordField (Arg3, 0x04, CDW2)=0D + CreateDWordField (Arg3, 0x08, CDW3)=0D + Store (CDW2, SUPP) /* \_SB_.PCI3.SUPP */=0D + Store (CDW3, CTRL) /* \_SB_.PCI3.CTRL */=0D + If (LNotEqual (And (SUPP, 0x16), 0x16))=0D + {=0D + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI3.CTRL */=0D + }=0D +=0D + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI3.CTRL */=0D + If (LNotEqual (Arg1, One))=0D + {=0D + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI3._OSC.CDW1 */=0D + }=0D +=0D + If (LNotEqual (CDW3, CTRL))=0D + {=0D + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI3._OSC.CDW1 */=0D + }=0D +=0D + Store (CTRL, CDW3) /* \_SB_.PCI3._OSC.CDW3 */=0D + Return (Arg3)=0D + }=0D + Else=0D + {=0D + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI3._OSC.CDW1 */=0D + Return (Arg3)=0D + }=0D + } // Method(_OSC)=0D + }=0D + }=0D +}=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132E= valSsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132= EvalSsdt.asl new file mode 100644 index 0000000000..64341095b1 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt= .asl @@ -0,0 +1,515 @@ +/** @file=0D +=0D + Secondary System Description Table Fields (SSDT)=0D +=0D + Copyright (c) 2018, Linaro Ltd. All rights reserved.
=0D + Copyright (c) 2019, Marvell International Ltd. and its affiliates.
=0D + Copyright (C) 2021, Semihalf.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "Cn913xCEx7Eval/Pcie.h"=0D +#include "IcuInterrupts.h"=0D +=0D +DefinitionBlock ("Cn9132CEx7EvalSsdt.aml", "SSDT", 2, "MRVL", "CN913X", 3)= =0D +{=0D + Scope (_SB)=0D + {=0D + Device (AHC1)=0D + {=0D + Name (_HID, "LNRO001E") // _HID: Hardware ID=0D + Name (_UID, 0x01) // _UID: Unique ID=0D + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_CLS, Package (0x03) // _CLS: Class Code=0D + {=0D + 0x01,=0D + 0x06,=0D + 0x01=0D + })=0D +=0D + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D + {=0D + Memory32Fixed (ReadWrite,=0D + 0xF6540000, // Address Base (MMIO)=0D + 0x00030000, // Address Length=0D + )=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, )=0D + {=0D + CP_GIC_SPI_CP2_SATA_H0=0D + }=0D + })=0D + }=0D +=0D + Device (XHC3)=0D + {=0D + Name (_HID, "PNP0D10") // _HID: Hardware ID=0D + Name (_UID, 0x03) // _UID: Unique ID=0D + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D +=0D + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D + {=0D + Memory32Fixed (ReadWrite,=0D + 0xF6500000, // Address Base (MMIO)=0D + 0x00004000, // Address Length=0D + )=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, )=0D + {=0D + CP_GIC_SPI_CP2_USB_H0=0D + }=0D + })=0D + }=0D + Device (XHC4)=0D + {=0D + Name (_HID, "PNP0D10") // _HID: Hardware ID=0D + Name (_UID, 0x04) // _UID: Unique ID=0D + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D +=0D + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D + {=0D + Memory32Fixed (ReadWrite,=0D + 0xF6510000, // Address Base (MMIO)=0D + 0x00004000, // Address Length=0D + )=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, )=0D + {=0D + CP_GIC_SPI_CP2_USB_H1=0D + }=0D + })=0D + }=0D +=0D + Device (XSM2)=0D + {=0D + Name (_HID, "MRVL0101") // _HID: H= ardware ID=0D + Name (_UID, 0x01) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Memory32Fixed (ReadWrite,=0D + 0xf412a600, // Address= Base=0D + 0x00000010, // Address= Length=0D + )=0D + })=0D + Device (PHY0)=0D + {=0D + Name (_ADR, 0x0)=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "compatible", "ethernet-phy-ieee802.3= -c45" },=0D + }=0D + })=0D + }=0D + }=0D +=0D + Device (PP22)=0D + {=0D + Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D + Name (_CCA, 0x01) // Cache-c= oherent controller=0D + Name (_UID, 0x02) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Memory32Fixed (ReadWrite, 0xf6000000 , 0x100000)=0D + Memory32Fixed (ReadWrite, 0xf6129000 , 0xb000)=0D + Memory32Fixed (ReadWrite, 0xf6220000 , 0x800)=0D + })=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "clock-frequency", 333333333 },=0D + }=0D + })=0D + Device (ETH0)=0D + {=0D + Name (_ADR, 0x0)=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv= e, ,, )=0D + {=0D + CP_GIC_SPI_PP2_CP2_PORT0=0D + }=0D + })=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "port-id", 0 },=0D + Package () { "gop-port-id", 0 },=0D + Package () { "phy-mode", "5gbase-r"},=0D + Package () { "phy-handle", \_SB.XSM2.PHY0},=0D + }=0D + })=0D + }=0D + }=0D +=0D + Device (RNG2)=0D + {=0D + Name (_HID, "PRP0001") // _HID= : Hardware ID=0D + Name (_UID, 0x02) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Memory32Fixed (ReadWrite, 0xF6760000, 0x7D)=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)=0D + {=0D + CP_GIC_SPI_CP2_EIP_RNG0=0D + }=0D + })=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "compatible", "inside-secure,safexcel-eip= 76" },=0D + }=0D + })=0D + }=0D +=0D + Device (PCI4)=0D + {=0D + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar= e ID=0D + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID=0D + Name (_SEG, 0x04) // _SEG: PCI Segment=0D + Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D + Name (_UID, 0x04) // _UID: Unique ID=0D + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_PRT, Package () // _PRT: PCI Routing Table=0D + {=0D + Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x1, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x2, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x3, 0x0, 0x40 }=0D + })=0D +=0D + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin= gs=0D + {=0D + Name (RBUF, ResourceTemplate ()=0D + {=0D + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P= osDecode,=0D + 0x0000, // Granularity= =0D + CP2_PCI0_BUS_MIN, // Range Minim= um=0D + CP2_PCI0_BUS_MAX, // Range Maxim= um=0D + 0x0000, // Translation= Offset=0D + CP2_PCI0_BUS_COUNT // Length=0D + )=0D + DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite,=0D + 0x00000000, // Granularity= =0D + CP2_PCI0_MMIO32_BASE, // Range Minim= um=0D + CP2_PCI0_MMIO32_MAX, // Range Maxim= um=0D + 0x00000000, // Translation= Offset=0D + CP2_PCI0_MMIO32_SIZE // Length=0D + )=0D + QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite,=0D + 0x0000000000000000, // Granularity= =0D + CP2_PCI0_MMIO64_BASE, // Range Minim= um=0D + CP2_PCI0_MMIO64_MAX, // Range Maxim= um=0D + 0x00000000, // Translation= Offset=0D + CP2_PCI0_MMIO64_SIZE // Length=0D + )=0D + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco= de, EntireRange,=0D + 0x00000000, // Granularity= =0D + CP2_PCI0_IO_BASE, // Range Minim= um=0D + 0x0000FFFF, // Range Maxim= um=0D + CP2_PCI0_IO_TRANSLATION, // Translation= Address=0D + CP2_PCI0_IO_SIZE, // Length=0D + ,=0D + ,=0D + ,=0D + TypeTranslation=0D + )=0D + })=0D + Return (RBUF) /* \_SB_.PCI4._CRS.RBUF */=0D + } // Method(_CRS)=0D +=0D + Device (RES0)=0D + {=0D + Name (_HID, "PNP0C02")=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Memory32Fixed (ReadWrite,=0D + CP2_PCI0_ECAM_BASE, // Range Minim= um=0D + CP2_PCI0_ECAM_SIZE // Length=0D + )=0D + })=0D + }=0D + Name (SUPP, 0x00)=0D + Name (CTRL, 0x00)=0D + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap= abilities=0D + {=0D + CreateDWordField (Arg3, 0x00, CDW1)=0D + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03= dd766") /* PCI Host Bridge Device */))=0D + {=0D + CreateDWordField (Arg3, 0x04, CDW2)=0D + CreateDWordField (Arg3, 0x08, CDW3)=0D + Store (CDW2, SUPP) /* \_SB_.PCI4.SUPP */=0D + Store (CDW3, CTRL) /* \_SB_.PCI4.CTRL */=0D + If (LNotEqual (And (SUPP, 0x16), 0x16))=0D + {=0D + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI4.CTRL */=0D + }=0D +=0D + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI4.CTRL */=0D + If (LNotEqual (Arg1, One))=0D + {=0D + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI4._OSC.CDW1 */=0D + }=0D +=0D + If (LNotEqual (CDW3, CTRL))=0D + {=0D + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI4._OSC.CDW1 */=0D + }=0D +=0D + Store (CTRL, CDW3) /* \_SB_.PCI4._OSC.CDW3 */=0D + Return (Arg3)=0D + }=0D + Else=0D + {=0D + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI4._OSC.CDW1 */=0D + Return (Arg3)=0D + }=0D + } // Method(_OSC)=0D + }=0D +=0D + Device (PCI5)=0D + {=0D + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar= e ID=0D + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID=0D + Name (_SEG, 0x05) // _SEG: PCI Segment=0D + Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D + Name (_UID, 0x05) // _UID: Unique ID=0D + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_PRT, Package () // _PRT: PCI Routing Table=0D + {=0D + Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x1, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x2, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x3, 0x0, 0x40 }=0D + })=0D +=0D + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin= gs=0D + {=0D + Name (RBUF, ResourceTemplate ()=0D + {=0D + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P= osDecode,=0D + 0x0000, // Granularity= =0D + CP2_PCI1_BUS_MIN, // Range Minim= um=0D + CP2_PCI1_BUS_MAX, // Range Maxim= um=0D + 0x0000, // Translation= Offset=0D + CP2_PCI1_BUS_COUNT // Length=0D + )=0D + DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite,=0D + 0x00000000, // Granularity= =0D + CP2_PCI1_MMIO32_BASE, // Range Minim= um=0D + CP2_PCI1_MMIO32_MAX, // Range Maxim= um=0D + 0x00000000, // Translation= Offset=0D + CP2_PCI1_MMIO32_SIZE // Length=0D + )=0D + QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite,=0D + 0x0000000000000000, // Granularity= =0D + CP2_PCI1_MMIO64_BASE, // Range Minim= um=0D + CP2_PCI1_MMIO64_MAX, // Range Maxim= um=0D + 0x00000000, // Translation= Offset=0D + CP2_PCI1_MMIO64_SIZE // Length=0D + )=0D + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco= de, EntireRange,=0D + 0x00000000, // Granularity= =0D + CP2_PCI1_IO_BASE, // Range Minim= um=0D + 0x0000FFFF, // Range Maxim= um=0D + CP2_PCI1_IO_TRANSLATION, // Translation= Address=0D + CP2_PCI1_IO_SIZE, // Length=0D + ,=0D + ,=0D + ,=0D + TypeTranslation=0D + )=0D + })=0D + Return (RBUF) /* \_SB_.PCI5._CRS.RBUF */=0D + } // Method(_CRS)=0D +=0D + Device (RES0)=0D + {=0D + Name (_HID, "PNP0C02")=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Memory32Fixed (ReadWrite,=0D + CP2_PCI1_ECAM_BASE, // Range Minim= um=0D + CP2_PCI1_ECAM_SIZE // Length=0D + )=0D + })=0D + }=0D + Name (SUPP, 0x00)=0D + Name (CTRL, 0x00)=0D + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap= abilities=0D + {=0D + CreateDWordField (Arg3, 0x00, CDW1)=0D + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03= dd766") /* PCI Host Bridge Device */))=0D + {=0D + CreateDWordField (Arg3, 0x04, CDW2)=0D + CreateDWordField (Arg3, 0x08, CDW3)=0D + Store (CDW2, SUPP) /* \_SB_.PCI5.SUPP */=0D + Store (CDW3, CTRL) /* \_SB_.PCI5.CTRL */=0D + If (LNotEqual (And (SUPP, 0x16), 0x16))=0D + {=0D + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI5.CTRL */=0D + }=0D +=0D + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI5.CTRL */=0D + If (LNotEqual (Arg1, One))=0D + {=0D + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI5._OSC.CDW1 */=0D + }=0D +=0D + If (LNotEqual (CDW3, CTRL))=0D + {=0D + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI5._OSC.CDW1 */=0D + }=0D +=0D + Store (CTRL, CDW3) /* \_SB_.PCI5._OSC.CDW3 */=0D + Return (Arg3)=0D + }=0D + Else=0D + {=0D + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI5._OSC.CDW1 */=0D + Return (Arg3)=0D + }=0D + } // Method(_OSC)=0D + }=0D +=0D + Device (PCI6)=0D + {=0D + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar= e ID=0D + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID=0D + Name (_SEG, 0x06) // _SEG: PCI Segment=0D + Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D + Name (_UID, 0x06) // _UID: Unique ID=0D + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_PRT, Package () // _PRT: PCI Routing Table=0D + {=0D + Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x1, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x2, 0x0, 0x40 },=0D + Package () { 0xFFFF, 0x3, 0x0, 0x40 }=0D + })=0D +=0D + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin= gs=0D + {=0D + Name (RBUF, ResourceTemplate ()=0D + {=0D + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P= osDecode,=0D + 0x0000, // Granularity= =0D + CP2_PCI2_BUS_MIN, // Range Minim= um=0D + CP2_PCI2_BUS_MAX, // Range Maxim= um=0D + 0x0000, // Translation= Offset=0D + CP2_PCI2_BUS_COUNT // Length=0D + )=0D + DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite,=0D + 0x00000000, // Granularity= =0D + CP2_PCI2_MMIO32_BASE, // Range Minim= um=0D + CP2_PCI2_MMIO32_MAX, // Range Maxim= um=0D + 0x00000000, // Translation= Offset=0D + CP2_PCI2_MMIO32_SIZE // Length=0D + )=0D + QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite,=0D + 0x0000000000000000, // Granularity= =0D + CP2_PCI2_MMIO64_BASE, // Range Minim= um=0D + CP2_PCI2_MMIO64_MAX, // Range Maxim= um=0D + 0x00000000, // Translation= Offset=0D + CP2_PCI2_MMIO64_SIZE // Length=0D + )=0D + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco= de, EntireRange,=0D + 0x00000000, // Granularity= =0D + CP2_PCI2_IO_BASE, // Range Minim= um=0D + 0x0000FFFF, // Range Maxim= um=0D + CP2_PCI2_IO_TRANSLATION, // Translation= Address=0D + CP2_PCI2_IO_SIZE, // Length=0D + ,=0D + ,=0D + ,=0D + TypeTranslation=0D + )=0D + })=0D + Return (RBUF) /* \_SB_.PCI6._CRS.RBUF */=0D + } // Method(_CRS)=0D +=0D + Device (RES0)=0D + {=0D + Name (_HID, "PNP0C02")=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Memory32Fixed (ReadWrite,=0D + CP2_PCI2_ECAM_BASE, // Range Minim= um=0D + CP2_PCI2_ECAM_SIZE // Length=0D + )=0D + })=0D + }=0D + Name (SUPP, 0x00)=0D + Name (CTRL, 0x00)=0D + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap= abilities=0D + {=0D + CreateDWordField (Arg3, 0x00, CDW1)=0D + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03= dd766") /* PCI Host Bridge Device */))=0D + {=0D + CreateDWordField (Arg3, 0x04, CDW2)=0D + CreateDWordField (Arg3, 0x08, CDW3)=0D + Store (CDW2, SUPP) /* \_SB_.PCI6.SUPP */=0D + Store (CDW3, CTRL) /* \_SB_.PCI6.CTRL */=0D + If (LNotEqual (And (SUPP, 0x16), 0x16))=0D + {=0D + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI6.CTRL */=0D + }=0D +=0D + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI6.CTRL */=0D + If (LNotEqual (Arg1, One))=0D + {=0D + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI6._OSC.CDW1 */=0D + }=0D +=0D + If (LNotEqual (CDW3, CTRL))=0D + {=0D + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI6._OSC.CDW1 */=0D + }=0D +=0D + Store (CTRL, CDW3) /* \_SB_.PCI6._OSC.CDW3 */=0D + Return (Arg3)=0D + }=0D + Else=0D + {=0D + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI6._OSC.CDW1 */=0D + Return (Arg3)=0D + }=0D + } // Method(_OSC)=0D + }=0D + }=0D +}=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xC= Ex7Dsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913x= CEx7Dsdt.asl new file mode 100644 index 0000000000..c54937fc7b --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt= .asl @@ -0,0 +1,120 @@ +/** @file=0D +=0D + Differentiated System Description Table Fields (DSDT)=0D +=0D + Copyright (c) 2018, Linaro Ltd. All rights reserved.
=0D + Copyright (C) 2019, Marvell International Ltd. and its affiliates.
=0D + Copyright (C) 2021, Semihalf.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +DefinitionBlock ("Cn913xCEx7.aml", "DSDT", 2, "MRVL", "CN9130", 3)=0D +{=0D + Scope (_SB)=0D + {=0D + Device (CPU0)=0D + {=0D + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D + Name (_UID, 0x000) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D + }=0D + Device (CPU1)=0D + {=0D + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D + Name (_UID, 0x001) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D + }=0D + Device (CPU2)=0D + {=0D + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D + Name (_UID, 0x100) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D + }=0D + Device (CPU3)=0D + {=0D + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D + Name (_UID, 0x101) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D + }=0D +=0D + Device (MMC0)=0D + {=0D + Name (_HID, "MRVL0003") // _HID: Hardware ID=0D + Name (_UID, 0x00) // _UID: Unique ID=0D + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D +=0D + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D + {=0D + Memory32Fixed (ReadWrite,=0D + 0xF06E0000, // Address Base (MMIO)=0D + 0x00000300, // Address Length=0D + )=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, )=0D + {=0D + 48=0D + }=0D + })=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "clock-frequency", 400000000 },=0D + Package () { "bus-width", 8 },=0D + Package () { "no-sd", 0x1 },=0D + Package () { "no-sdio", 0x1 },=0D + Package () { "mmc-ddr-1_8v", 0x1 },=0D + Package () { "mmc-hs400-1_8v", 0x1 },=0D + Package () { "non-removable", 0x1 },=0D + }=0D + })=0D + }=0D +=0D + Device (COM1)=0D + {=0D + Name (_HID, "MRVL0001") // _HID: H= ardware ID=0D + Name (_CID, "HISI0031") // _CID: C= ompatible ID=0D + Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D + Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress=0D + Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings=0D + {=0D + Memory32Fixed (ReadWrite,=0D + FixedPcdGet64(PcdSerialRegisterBase), // Address= Base=0D + 0x00000100, // Address= Length=0D + )=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, )=0D + {=0D + 51=0D + }=0D + })=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "clock-frequency", FixedPcdGet32 (PcdSe= rialClockRate) },=0D + Package () { "reg-io-width", 1 },=0D + Package () { "reg-shift", 2 },=0D + }=0D + })=0D + }=0D + }=0D +}=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.as= lc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc new file mode 100644 index 0000000000..143da73f5c --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc @@ -0,0 +1,74 @@ +/** @file=0D +* Debug Port Table (DBG2)=0D +*=0D +* Copyright (c) 2020 Linaro Ltd. All rights reserved.=0D +* Copyright (c) 2021 ARM Ltd. All rights reserved.=0D +* Copyright (c) 2021 Semihalf. All rights reserved.=0D +*=0D +* SPDX-License-Identifier: BSD-2-Clause-Patent=0D +*=0D +**/=0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include "AcpiHeader.h"=0D +#include "Cn913xCEx7Eval/Dbg2.h"=0D +=0D +#pragma pack(1)=0D +=0D +#define CN913X_UART_STR { '\\', '_', 'S', 'B', '.', 'C', 'O', 'M', '2', 0x= 00 }=0D +=0D +typedef struct {=0D + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device;=0D + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister;=0D + UINT32 AddressSize;=0D + UINT8 NameSpaceString[10];=0D +} DBG2_DEBUG_DEVICE_INFORMATION;=0D +=0D +typedef struct {=0D + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description;=0D + DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo;=0D +} DBG2_TABLE;=0D +=0D +=0D +STATIC DBG2_TABLE Dbg2 =3D {=0D + {=0D + __ACPI_HEADER (=0D + EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE,=0D + DBG2_TABLE,=0D + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION=0D + ),=0D + OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo),=0D + 1 /* NumberOfDebugPorts */=0D + },=0D + {=0D + {=0D + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,=0D + sizeof (DBG2_DEBUG_DEVICE_INFORMATION),=0D + 1, /* NumberofGenericAddressRegist= ers */=0D + 10, /* NameSpaceStringLength */=0D + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString),=0D + 0, /* OemDataLength */=0D + 0, /* OemDataOffset */=0D + EFI_ACPI_DBG2_PORT_TYPE_SERIAL,=0D + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_SUBSET_COMPATIBLE_WITH_MS_DB= GP_SPEC,=0D + {=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE=0D + },=0D + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister),=0D + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize)=0D + },=0D + MV_UART_AS32 (CN913X_DBG2_UART_REG_BASE), /* BaseAddress */= =0D + SIZE_4KB, /* AddressSize */= =0D + CN913X_UART_STR, /* NameSpaceStrin= g */=0D + }=0D +};=0D +=0D +#pragma pack()=0D +=0D +// Reference the table being generated to prevent the optimizer from remov= ing=0D +// the data structure from the executable=0D +VOID* CONST ReferenceAcpiTable =3D &Dbg2;=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.as= lc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc new file mode 100644 index 0000000000..181bbe5530 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc @@ -0,0 +1,87 @@ +/** @file=0D +=0D + Memory mapped config space base address table (MCFG)=0D +=0D + Copyright (c) 2017, Linaro Ltd. All rights reserved.
=0D + Copyright (C) 2019, Marvell International Ltd. and its affiliates.
=0D + Copyright (C) 2021, Semihalf.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +=0D +#include "AcpiHeader.h"=0D +#include "Cn913xCEx7Eval/Pcie.h"=0D +=0D +#include =0D +=0D +#pragma pack(1)=0D +typedef struct {=0D + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;=0D + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCAT= ION_STRUCTURE Structure[7];=0D +} ACPI_6_0_MCFG_STRUCTURE;=0D +#pragma pack()=0D +=0D +STATIC ACPI_6_0_MCFG_STRUCTURE Mcfg =3D {=0D + {=0D + __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SP= ACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,=0D + ACPI_6_0_MCFG_STRUCTURE,=0D + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE= _REVISION),=0D + EFI_ACPI_RESERVED_QWORD=0D + },=0D + {=0D + {=0D + CP0_PCI0_ECAM_BASE, // BaseAddress=0D + 0, // PciSegmentGroupNumber=0D + CP0_PCI0_BUS_MIN, // StartBusNumber=0D + CP0_PCI0_BUS_MAX, // EndBusNumber=0D + EFI_ACPI_RESERVED_DWORD // Reserved=0D + },=0D + {=0D + CP1_PCI0_ECAM_BASE, // BaseAddress=0D + 1, // PciSegmentGroupNumber=0D + CP1_PCI0_BUS_MIN, // StartBusNumber=0D + CP1_PCI0_BUS_MAX, // EndBusNumber=0D + EFI_ACPI_RESERVED_DWORD // Reserved=0D + },=0D + {=0D + CP1_PCI1_ECAM_BASE, // BaseAddress=0D + 2, // PciSegmentGroupNumber=0D + CP1_PCI1_BUS_MIN, // StartBusNumber=0D + CP1_PCI1_BUS_MAX, // EndBusNumber=0D + EFI_ACPI_RESERVED_DWORD // Reserved=0D + },=0D + {=0D + CP1_PCI2_ECAM_BASE, // BaseAddress=0D + 3, // PciSegmentGroupNumber=0D + CP1_PCI2_BUS_MIN, // StartBusNumber=0D + CP1_PCI2_BUS_MAX, // EndBusNumber=0D + EFI_ACPI_RESERVED_DWORD // Reserved=0D + },=0D + {=0D + CP2_PCI0_ECAM_BASE, // BaseAddress=0D + 4, // PciSegmentGroupNumber=0D + CP2_PCI0_BUS_MIN, // StartBusNumber=0D + CP2_PCI0_BUS_MAX, // EndBusNumber=0D + EFI_ACPI_RESERVED_DWORD // Reserved=0D + },=0D + {=0D + CP2_PCI1_ECAM_BASE, // BaseAddress=0D + 5, // PciSegmentGroupNumber=0D + CP2_PCI1_BUS_MIN, // StartBusNumber=0D + CP2_PCI1_BUS_MAX, // EndBusNumber=0D + EFI_ACPI_RESERVED_DWORD // Reserved=0D + },=0D + {=0D + CP2_PCI2_ECAM_BASE, // BaseAddress=0D + 6, // PciSegmentGroupNumber=0D + CP2_PCI2_BUS_MIN, // StartBusNumber=0D + CP2_PCI2_BUS_MAX, // EndBusNumber=0D + EFI_ACPI_RESERVED_DWORD // Reserved=0D + }=0D + }=0D +};=0D +=0D +VOID CONST * CONST ReferenceAcpiTable =3D &Mcfg;=0D --=20 2.29.0