* [edk2-platforms PATCH v2 2/3] SolidRun/Cn913xCEx7Eval: Add ACPI support
2021-08-07 19:36 [edk2-platforms PATCH v2 0/4] SolidRun CEx7 Evaluation Board support Marcin Wojtas
2021-08-07 19:36 ` [edk2-platforms PATCH v2 1/3] Marvell: Armada7k8k/OcteonTx: Select ACPI description as a default Marcin Wojtas
@ 2021-08-07 19:36 ` Marcin Wojtas
2021-08-07 19:36 ` [edk2-platforms PATCH v2 3/3] SolidRun/Cn913xCEx7Eval: Add platform support Marcin Wojtas
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Marcin Wojtas @ 2021-08-07 19:36 UTC (permalink / raw)
To: devel
Cc: leif, ardb+tianocore, jaz, gjb, Samer.El-Haj-Mahmoud, jon,
alon.rotman, Marcin Wojtas
This patch adds ACPI tables description for the SolidRun
CN913x CEx7 Evaluation Board platform.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf | 61 +++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h | 9 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h | 114 +++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl | 383 +++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl | 493 +++++++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl | 515 ++++++++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl | 120 +++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc | 74 +++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc | 87 ++++
9 files changed, 1856 insertions(+)
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf
new file mode 100644
index 0000000000..27e7294014
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf
@@ -0,0 +1,61 @@
+## @file
+# Component description file for PlatformAcpiTables module.
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+# Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR>
+# Copyright (c) 2021, Semihalf.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = PlatformAcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl
+ Cn913xCEx7Eval/Cn9130EvalSsdt.asl
+ Cn913xCEx7Eval/Cn9131EvalSsdt.asl
+ Cn913xCEx7Eval/Cn9132EvalSsdt.asl
+ Cn913xCEx7Eval/Dbg2.aslc
+ Cn913xCEx7Eval/Mcfg.aslc
+ Fadt.aslc
+ Gtdt.aslc
+ Madt.aslc
+ Pptt.aslc
+ Spcr.aslc
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Marvell/Marvell.dec
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+
+[BuildOptions]
+ *_*_*_ASLCC_FLAGS = -DCN9131
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h
new file mode 100644
index 0000000000..a18b7c1396
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h
@@ -0,0 +1,9 @@
+/**
+
+ Copyright (C) 2021, Semihalf.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#define CN913X_DBG2_UART_REG_BASE 0xF2702200
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h
new file mode 100644
index 0000000000..592e47d0c4
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h
@@ -0,0 +1,114 @@
+/**
+
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+ Copyright (C) 2021, Semihalf.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#define CP0_PCI0_BUS_MIN 0x0
+#define CP0_PCI0_BUS_MAX 0x0
+#define CP0_PCI0_BUS_COUNT 0x1
+#define CP0_PCI0_MMIO32_BASE 0xC0000000
+#define CP0_PCI0_MMIO32_SIZE 0x20000000
+#define CP0_PCI0_MMIO32_MAX 0xDFFFFFFF
+#define CP0_PCI0_MMIO64_BASE 0x810000000
+#define CP0_PCI0_MMIO64_SIZE 0x80000000
+#define CP0_PCI0_MMIO64_MAX 0x88FFFFFFF
+#define CP0_PCI0_IO_BASE 0x0
+#define CP0_PCI0_IO_SIZE 0x10000
+#define CP0_PCI0_IO_TRANSLATION 0x80FF00000
+#define CP0_PCI0_ECAM_BASE 0x800008000
+#define CP0_PCI0_ECAM_SIZE 0x100000
+#define CP0_PCI0_ECAM_MAX 0x800107FFF
+
+#define CP1_PCI0_BUS_MIN 0x0
+#define CP1_PCI0_BUS_MAX 0x0
+#define CP1_PCI0_BUS_COUNT 0x1
+#define CP1_PCI0_MMIO32_BASE 0xE3000000
+#define CP1_PCI0_MMIO32_SIZE 0x1000000
+#define CP1_PCI0_MMIO32_MAX 0xE3FFFFFF
+#define CP1_PCI0_MMIO64_BASE 0x890000000
+#define CP1_PCI0_MMIO64_SIZE 0x10000000
+#define CP1_PCI0_MMIO64_MAX 0x89FFFFFFF
+#define CP1_PCI0_IO_BASE 0x0
+#define CP1_PCI0_IO_SIZE 0x10000
+#define CP1_PCI0_IO_TRANSLATION 0xE2F00000
+#define CP1_PCI0_ECAM_BASE 0xE2008000
+#define CP1_PCI0_ECAM_SIZE 0x100000
+
+#define CP1_PCI1_BUS_MIN 0x0
+#define CP1_PCI1_BUS_MAX 0x0
+#define CP1_PCI1_BUS_COUNT 0x1
+#define CP1_PCI1_MMIO32_BASE 0xE5000000
+#define CP1_PCI1_MMIO32_SIZE 0x1000000
+#define CP1_PCI1_MMIO32_MAX 0xE5FFFFFF
+#define CP1_PCI1_MMIO64_BASE 0x8A0000000
+#define CP1_PCI1_MMIO64_SIZE 0x10000000
+#define CP1_PCI1_MMIO64_MAX 0x8AFFFFFFF
+#define CP1_PCI1_IO_BASE 0x0
+#define CP1_PCI1_IO_SIZE 0x10000
+#define CP1_PCI1_IO_TRANSLATION 0xE4F00000
+#define CP1_PCI1_ECAM_BASE 0xE4008000
+#define CP1_PCI1_ECAM_SIZE 0x100000
+
+#define CP1_PCI2_BUS_MIN 0x0
+#define CP1_PCI2_BUS_MAX 0x0
+#define CP1_PCI2_BUS_COUNT 0x1
+#define CP1_PCI2_MMIO32_BASE 0xE7000000
+#define CP1_PCI2_MMIO32_SIZE 0x1000000
+#define CP1_PCI2_MMIO32_MAX 0xE7FFFFFF
+#define CP1_PCI2_MMIO64_BASE 0x8B0000000
+#define CP1_PCI2_MMIO64_SIZE 0x10000000
+#define CP1_PCI2_MMIO64_MAX 0x8BFFFFFFF
+#define CP1_PCI2_IO_BASE 0x0
+#define CP1_PCI2_IO_SIZE 0x10000
+#define CP1_PCI2_IO_TRANSLATION 0xE6F00000
+#define CP1_PCI2_ECAM_BASE 0xE6008000
+#define CP1_PCI2_ECAM_SIZE 0x100000
+
+#define CP2_PCI0_BUS_MIN 0x0
+#define CP2_PCI0_BUS_MAX 0x0
+#define CP2_PCI0_BUS_COUNT 0x1
+#define CP2_PCI0_MMIO32_BASE 0xEA000000
+#define CP2_PCI0_MMIO32_SIZE 0x1000000
+#define CP2_PCI0_MMIO32_MAX 0xEAFFFFFF
+#define CP2_PCI0_MMIO64_BASE 0x8C0000000
+#define CP2_PCI0_MMIO64_SIZE 0x10000000
+#define CP2_PCI0_MMIO64_MAX 0x8CFFFFFFF
+#define CP2_PCI0_IO_BASE 0x0
+#define CP2_PCI0_IO_SIZE 0x10000
+#define CP2_PCI0_IO_TRANSLATION 0xE9F00000
+#define CP2_PCI0_ECAM_BASE 0xE9008000
+#define CP2_PCI0_ECAM_SIZE 0x100000
+
+#define CP2_PCI1_BUS_MIN 0x0
+#define CP2_PCI1_BUS_MAX 0x0
+#define CP2_PCI1_BUS_COUNT 0x1
+#define CP2_PCI1_MMIO32_BASE 0xEC000000
+#define CP2_PCI1_MMIO32_SIZE 0x1000000
+#define CP2_PCI1_MMIO32_MAX 0xECFFFFFF
+#define CP2_PCI1_MMIO64_BASE 0x8D0000000
+#define CP2_PCI1_MMIO64_SIZE 0x10000000
+#define CP2_PCI1_MMIO64_MAX 0x8DFFFFFFF
+#define CP2_PCI1_IO_BASE 0x0
+#define CP2_PCI1_IO_SIZE 0x10000
+#define CP2_PCI1_IO_TRANSLATION 0xEBF00000
+#define CP2_PCI1_ECAM_BASE 0xEB008000
+#define CP2_PCI1_ECAM_SIZE 0x100000
+
+#define CP2_PCI2_BUS_MIN 0x0
+#define CP2_PCI2_BUS_MAX 0x0
+#define CP2_PCI2_BUS_COUNT 0x1
+#define CP2_PCI2_MMIO32_BASE 0xEE000000
+#define CP2_PCI2_MMIO32_SIZE 0x1000000
+#define CP2_PCI2_MMIO32_MAX 0xEEFFFFFF
+#define CP2_PCI2_MMIO64_BASE 0x8E0000000
+#define CP2_PCI2_MMIO64_SIZE 0x10000000
+#define CP2_PCI2_MMIO64_MAX 0x8EFFFFFFF
+#define CP2_PCI2_IO_BASE 0x0
+#define CP2_PCI2_IO_SIZE 0x10000
+#define CP2_PCI2_IO_TRANSLATION 0xEDF00000
+#define CP2_PCI2_ECAM_BASE 0xED008000
+#define CP2_PCI2_ECAM_SIZE 0x100000
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl
new file mode 100644
index 0000000000..70bdecb620
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl
@@ -0,0 +1,383 @@
+/** @file
+
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.<BR>
+ Copyright (C) 2021, Semihalf.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "Cn913xCEx7Eval/Dbg2.h"
+#include "Cn913xCEx7Eval/Pcie.h"
+#include "IcuInterrupts.h"
+
+DefinitionBlock ("Cn9130CEx7EvalSsdt.aml", "SSDT", 2, "MRVL", "CN913X", 3)
+{
+ Scope (_SB)
+ {
+ Device (MMC1)
+ {
+ Name (_HID, "MRVL0004") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF2780000, // Address Base (MMIO)
+ 0x00000300, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP0_SDMMC
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", 400000000 },
+ Package () { "bus-width", 4 },
+ Package () { "no-1-8-v", 0x1 },
+ Package () { "broken-cd", 0x1 },
+ }
+ })
+ }
+
+ Device (XHC0)
+ {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF2500000, // Address Base (MMIO)
+ 0x00004000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP0_USB_H0
+ }
+ })
+ }
+
+ Device (XHC1)
+ {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF2510000, // Address Base (MMIO)
+ 0x00004000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP0_USB_H1
+ }
+ })
+ }
+
+ Device (COM2)
+ {
+ Name (_HID, "MRVL0001") // _HID: Hardware ID
+ Name (_CID, "HISI0031") // _CID: Compatible ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_ADR, CN913X_DBG2_UART_REG_BASE) // _ADR: Address
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ CN913X_DBG2_UART_REG_BASE, // Address Base
+ 0x00000100, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP0_UART2
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", FixedPcdGet32 (PcdSerialClockRate) },
+ Package () { "reg-io-width", 1 },
+ Package () { "reg-shift", 2 },
+ }
+ })
+ }
+
+ Device (SMI0)
+ {
+ Name (_HID, "MRVL0100") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0xf212a200, // Address Base
+ 0x00000010, // Address Length
+ )
+ })
+ Device (PHY0)
+ {
+ Name (_ADR, 0x0)
+ }
+ }
+
+ Device (PP20)
+ {
+ Name (_HID, "MRVL0110") // _HID: Hardware ID
+ Name (_CCA, 0x01) // Cache-coherent controller
+ Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)
+ Memory32Fixed (ReadWrite, 0xf2129000 , 0xb000)
+ Memory32Fixed (ReadWrite, 0xf2220000 , 0x800)
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", 333333333 },
+ }
+ })
+ Device (ETH0)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP0_PORT0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 0 },
+ Package () { "gop-port-id", 0 },
+ Package () { "phy-mode", "10gbase-kr"},
+ Package () { "managed", "in-band-status"},
+ }
+ })
+ }
+ Device (ETH1)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP0_PORT1
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 1 },
+ Package () { "gop-port-id", 2 },
+ Package () { "phy-mode", "rgmii-id"},
+ Package () { "phy-handle", \_SB.SMI0.PHY0},
+ }
+ })
+ }
+ Device (ETH2)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP0_PORT2
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 2 },
+ Package () { "gop-port-id", 3 },
+ Package () { "phy-mode", "2500base-x"},
+ },
+ ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
+ Package () {
+ Package () {"fixed-link", "LNK0"}
+ }
+ })
+ Name (LNK0, Package(){ // Data-only subnode of port
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"speed", 2500},
+ Package () {"full-duplex", 1}
+ }
+ })
+ }
+ }
+
+ Device (RNG0)
+ {
+ Name (_HID, "PRP0001") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)
+ {
+ CP_GIC_SPI_CP0_EIP_RNG0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "compatible", "inside-secure,safexcel-eip76" },
+ }
+ })
+ }
+
+ //
+ // PCIe Root Bus
+ //
+ Device (PCI0)
+ {
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
+ Name (_SEG, 0x00) // _SEG: PCI Segment
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ Package () { 0xFFFF, 0x0, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x1, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x2, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x3, 0x0, 0x40 }
+ })
+
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ CP0_PCI0_BUS_MIN, // Range Minimum
+ CP0_PCI0_BUS_MAX, // Range Maximum
+ 0x0000, // Translation Offset
+ CP0_PCI0_BUS_COUNT // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ CP0_PCI0_MMIO32_BASE, // Range Minimum
+ CP0_PCI0_MMIO32_MAX, // Range Maximum
+ 0x00000000, // Translation Offset
+ CP0_PCI0_MMIO32_SIZE // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ CP0_PCI0_MMIO64_BASE, // Range Minimum
+ CP0_PCI0_MMIO64_MAX, // Range Maximum
+ 0x00000000, // Translation Offset
+ CP0_PCI0_MMIO64_SIZE // Length
+ )
+ QWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Granularity
+ CP0_PCI0_IO_BASE, // Range Minimum
+ 0x0000FFFF, // Range Maximum
+ CP0_PCI0_IO_TRANSLATION, // Translation Address
+ CP0_PCI0_IO_SIZE, // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ })
+ Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */
+ } // Method(_CRS)
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02")
+ Name (_CRS, ResourceTemplate ()
+ {
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ CP0_PCI0_ECAM_BASE, // Range Minimum
+ CP0_PCI0_ECAM_MAX, // Range Maximum
+ 0x00000000, // Translation Offset
+ CP0_PCI0_ECAM_SIZE // Length
+ )
+ })
+ }
+ Name (SUPP, 0x00)
+ Name (CTRL, 0x00)
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, 0x00, CDW1)
+ If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Store (CDW2, SUPP) /* \_SB_.PCI0.SUPP */
+ Store (CDW3, CTRL) /* \_SB_.PCI0.CTRL */
+ If (LNotEqual (And (SUPP, 0x16), 0x16))
+ {
+ And (CTRL, 0x1E, CTRL) /* \_SB_.PCI0.CTRL */
+ }
+
+ And (CTRL, 0x1D, CTRL) /* \_SB_.PCI0.CTRL */
+ If (LNotEqual (Arg1, One))
+ {
+ Or (CDW1, 0x08, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+ }
+
+ If (LNotEqual (CDW3, CTRL))
+ {
+ Or (CDW1, 0x10, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+ }
+
+ Store (CTRL, CDW3) /* \_SB_.PCI0._OSC.CDW3 */
+ Return (Arg3)
+ }
+ Else
+ {
+ Or (CDW1, 0x04, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+ Return (Arg3)
+ }
+ } // Method(_OSC)
+ }
+ }
+}
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl
new file mode 100644
index 0000000000..930134b86f
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl
@@ -0,0 +1,493 @@
+/** @file
+
+ Secondary System Description Table Fields (SSDT)
+
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR>
+ Copyright (C) 2021, Semihalf.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "Cn913xCEx7Eval/Pcie.h"
+#include "IcuInterrupts.h"
+
+DefinitionBlock ("Cn9131CEx7EvalSsdt.aml", "SSDT", 2, "MRVL", "CN913X", 3)
+{
+ Scope (_SB)
+ {
+ Device (AHC0)
+ {
+ Name (_HID, "LNRO001E") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_CLS, Package (0x03) // _CLS: Class Code
+ {
+ 0x01,
+ 0x06,
+ 0x01
+ })
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF4540000, // Address Base (MMIO)
+ 0x00030000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP1_SATA_H0
+ }
+ })
+ }
+
+ Device (XHC2)
+ {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF4510000, // Address Base (MMIO)
+ 0x00004000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP1_USB_H1
+ }
+ })
+ }
+
+ Device (XSM1)
+ {
+ Name (_HID, "MRVL0101") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0xf412a600, // Address Base
+ 0x00000010, // Address Length
+ )
+ })
+ Device (PHY0)
+ {
+ Name (_ADR, 0x0)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "compatible", "ethernet-phy-ieee802.3-c45" },
+ }
+ })
+ }
+ }
+
+ Device (PP21)
+ {
+ Name (_HID, "MRVL0110") // _HID: Hardware ID
+ Name (_CCA, 0x01) // Cache-coherent controller
+ Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)
+ Memory32Fixed (ReadWrite, 0xf4129000 , 0xb000)
+ Memory32Fixed (ReadWrite, 0xf4220000 , 0x800)
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", 333333333 },
+ }
+ })
+ Device (ETH0)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP1_PORT0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 0 },
+ Package () { "gop-port-id", 0 },
+ Package () { "phy-mode", "5gbase-r"},
+ Package () { "phy-handle", \_SB.XSM1.PHY0},
+ }
+ })
+ }
+ }
+
+ Device (RNG1)
+ {
+ Name (_HID, "PRP0001") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xF4760000, 0x7D)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)
+ {
+ CP_GIC_SPI_CP1_EIP_RNG0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "compatible", "inside-secure,safexcel-eip76" },
+ }
+ })
+ }
+
+ Device (PCI1)
+ {
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
+ Name (_SEG, 0x01) // _SEG: PCI Segment
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ Package () { 0xFFFF, 0x0, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x1, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x2, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x3, 0x0, 0x40 }
+ })
+
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ CP1_PCI0_BUS_MIN, // Range Minimum
+ CP1_PCI0_BUS_MAX, // Range Maximum
+ 0x0000, // Translation Offset
+ CP1_PCI0_BUS_COUNT // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ CP1_PCI0_MMIO32_BASE, // Range Minimum
+ CP1_PCI0_MMIO32_MAX, // Range Maximum
+ 0x00000000, // Translation Offset
+ CP1_PCI0_MMIO32_SIZE // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ CP1_PCI0_MMIO64_BASE, // Range Minimum
+ CP1_PCI0_MMIO64_MAX, // Range Maximum
+ 0x00000000, // Translation Offset
+ CP1_PCI0_MMIO64_SIZE // Length
+ )
+ DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Granularity
+ CP1_PCI0_IO_BASE, // Range Minimum
+ 0x0000FFFF, // Range Maximum
+ CP1_PCI0_IO_TRANSLATION, // Translation Address
+ CP1_PCI0_IO_SIZE, // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ })
+ Return (RBUF) /* \_SB_.PCI1._CRS.RBUF */
+ } // Method(_CRS)
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02")
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ CP1_PCI0_ECAM_BASE, // Range Minimum
+ CP1_PCI0_ECAM_SIZE // Length
+ )
+ })
+ }
+ Name (SUPP, 0x00)
+ Name (CTRL, 0x00)
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, 0x00, CDW1)
+ If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Store (CDW2, SUPP) /* \_SB_.PCI1.SUPP */
+ Store (CDW3, CTRL) /* \_SB_.PCI1.CTRL */
+ If (LNotEqual (And (SUPP, 0x16), 0x16))
+ {
+ And (CTRL, 0x1E, CTRL) /* \_SB_.PCI1.CTRL */
+ }
+
+ And (CTRL, 0x1D, CTRL) /* \_SB_.PCI1.CTRL */
+ If (LNotEqual (Arg1, One))
+ {
+ Or (CDW1, 0x08, CDW1) /* \_SB_.PCI1._OSC.CDW1 */
+ }
+
+ If (LNotEqual (CDW3, CTRL))
+ {
+ Or (CDW1, 0x10, CDW1) /* \_SB_.PCI1._OSC.CDW1 */
+ }
+
+ Store (CTRL, CDW3) /* \_SB_.PCI1._OSC.CDW3 */
+ Return (Arg3)
+ }
+ Else
+ {
+ Or (CDW1, 0x04, CDW1) /* \_SB_.PCI1._OSC.CDW1 */
+ Return (Arg3)
+ }
+ } // Method(_OSC)
+ }
+
+ Device (PCI2)
+ {
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
+ Name (_SEG, 0x02) // _SEG: PCI Segment
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ Package () { 0xFFFF, 0x0, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x1, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x2, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x3, 0x0, 0x40 }
+ })
+
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ CP1_PCI1_BUS_MIN, // Range Minimum
+ CP1_PCI1_BUS_MAX, // Range Maximum
+ 0x0000, // Translation Offset
+ CP1_PCI1_BUS_COUNT // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ CP1_PCI1_MMIO32_BASE, // Range Minimum
+ CP1_PCI1_MMIO32_MAX, // Range Maximum
+ 0x00000000, // Translation Offset
+ CP1_PCI1_MMIO32_SIZE // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ CP1_PCI1_MMIO64_BASE, // Range Minimum
+ CP1_PCI1_MMIO64_MAX, // Range Maximum
+ 0x00000000, // Translation Offset
+ CP1_PCI1_MMIO64_SIZE // Length
+ )
+ DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Granularity
+ CP1_PCI1_IO_BASE, // Range Minimum
+ 0x0000FFFF, // Range Maximum
+ CP1_PCI1_IO_TRANSLATION, // Translation Address
+ CP1_PCI1_IO_SIZE, // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ })
+ Return (RBUF) /* \_SB_.PCI2._CRS.RBUF */
+ } // Method(_CRS)
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02")
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ CP1_PCI1_ECAM_BASE, // Range Minimum
+ CP1_PCI1_ECAM_SIZE // Length
+ )
+ })
+ }
+ Name (SUPP, 0x00)
+ Name (CTRL, 0x00)
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, 0x00, CDW1)
+ If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Store (CDW2, SUPP) /* \_SB_.PCI2.SUPP */
+ Store (CDW3, CTRL) /* \_SB_.PCI2.CTRL */
+ If (LNotEqual (And (SUPP, 0x16), 0x16))
+ {
+ And (CTRL, 0x1E, CTRL) /* \_SB_.PCI2.CTRL */
+ }
+
+ And (CTRL, 0x1D, CTRL) /* \_SB_.PCI2.CTRL */
+ If (LNotEqual (Arg1, One))
+ {
+ Or (CDW1, 0x08, CDW1) /* \_SB_.PCI2._OSC.CDW1 */
+ }
+
+ If (LNotEqual (CDW3, CTRL))
+ {
+ Or (CDW1, 0x10, CDW1) /* \_SB_.PCI2._OSC.CDW1 */
+ }
+
+ Store (CTRL, CDW3) /* \_SB_.PCI2._OSC.CDW3 */
+ Return (Arg3)
+ }
+ Else
+ {
+ Or (CDW1, 0x04, CDW1) /* \_SB_.PCI2._OSC.CDW1 */
+ Return (Arg3)
+ }
+ } // Method(_OSC)
+ }
+
+ Device (PCI3)
+ {
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
+ Name (_SEG, 0x03) // _SEG: PCI Segment
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ Package () { 0xFFFF, 0x0, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x1, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x2, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x3, 0x0, 0x40 }
+ })
+
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ CP1_PCI2_BUS_MIN, // Range Minimum
+ CP1_PCI2_BUS_MAX, // Range Maximum
+ 0x0000, // Translation Offset
+ CP1_PCI2_BUS_COUNT // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ CP1_PCI2_MMIO32_BASE, // Range Minimum
+ CP1_PCI2_MMIO32_MAX, // Range Maximum
+ 0x00000000, // Translation Offset
+ CP1_PCI2_MMIO32_SIZE // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ CP1_PCI2_MMIO64_BASE, // Range Minimum
+ CP1_PCI2_MMIO64_MAX, // Range Maximum
+ 0x00000000, // Translation Offset
+ CP1_PCI2_MMIO64_SIZE // Length
+ )
+ DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Granularity
+ CP1_PCI2_IO_BASE, // Range Minimum
+ 0x0000FFFF, // Range Maximum
+ CP1_PCI2_IO_TRANSLATION, // Translation Address
+ CP1_PCI2_IO_SIZE, // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ })
+ Return (RBUF) /* \_SB_.PCI3._CRS.RBUF */
+ } // Method(_CRS)
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02")
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ CP1_PCI2_ECAM_BASE, // Range Minimum
+ CP1_PCI2_ECAM_SIZE // Length
+ )
+ })
+ }
+ Name (SUPP, 0x00)
+ Name (CTRL, 0x00)
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, 0x00, CDW1)
+ If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Store (CDW2, SUPP) /* \_SB_.PCI3.SUPP */
+ Store (CDW3, CTRL) /* \_SB_.PCI3.CTRL */
+ If (LNotEqual (And (SUPP, 0x16), 0x16))
+ {
+ And (CTRL, 0x1E, CTRL) /* \_SB_.PCI3.CTRL */
+ }
+
+ And (CTRL, 0x1D, CTRL) /* \_SB_.PCI3.CTRL */
+ If (LNotEqual (Arg1, One))
+ {
+ Or (CDW1, 0x08, CDW1) /* \_SB_.PCI3._OSC.CDW1 */
+ }
+
+ If (LNotEqual (CDW3, CTRL))
+ {
+ Or (CDW1, 0x10, CDW1) /* \_SB_.PCI3._OSC.CDW1 */
+ }
+
+ Store (CTRL, CDW3) /* \_SB_.PCI3._OSC.CDW3 */
+ Return (Arg3)
+ }
+ Else
+ {
+ Or (CDW1, 0x04, CDW1) /* \_SB_.PCI3._OSC.CDW1 */
+ Return (Arg3)
+ }
+ } // Method(_OSC)
+ }
+ }
+}
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl
new file mode 100644
index 0000000000..64341095b1
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl
@@ -0,0 +1,515 @@
+/** @file
+
+ Secondary System Description Table Fields (SSDT)
+
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR>
+ Copyright (C) 2021, Semihalf.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "Cn913xCEx7Eval/Pcie.h"
+#include "IcuInterrupts.h"
+
+DefinitionBlock ("Cn9132CEx7EvalSsdt.aml", "SSDT", 2, "MRVL", "CN913X", 3)
+{
+ Scope (_SB)
+ {
+ Device (AHC1)
+ {
+ Name (_HID, "LNRO001E") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_CLS, Package (0x03) // _CLS: Class Code
+ {
+ 0x01,
+ 0x06,
+ 0x01
+ })
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF6540000, // Address Base (MMIO)
+ 0x00030000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP2_SATA_H0
+ }
+ })
+ }
+
+ Device (XHC3)
+ {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF6500000, // Address Base (MMIO)
+ 0x00004000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP2_USB_H0
+ }
+ })
+ }
+ Device (XHC4)
+ {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF6510000, // Address Base (MMIO)
+ 0x00004000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP2_USB_H1
+ }
+ })
+ }
+
+ Device (XSM2)
+ {
+ Name (_HID, "MRVL0101") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0xf412a600, // Address Base
+ 0x00000010, // Address Length
+ )
+ })
+ Device (PHY0)
+ {
+ Name (_ADR, 0x0)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "compatible", "ethernet-phy-ieee802.3-c45" },
+ }
+ })
+ }
+ }
+
+ Device (PP22)
+ {
+ Name (_HID, "MRVL0110") // _HID: Hardware ID
+ Name (_CCA, 0x01) // Cache-coherent controller
+ Name (_UID, 0x02) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xf6000000 , 0x100000)
+ Memory32Fixed (ReadWrite, 0xf6129000 , 0xb000)
+ Memory32Fixed (ReadWrite, 0xf6220000 , 0x800)
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", 333333333 },
+ }
+ })
+ Device (ETH0)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP2_PORT0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 0 },
+ Package () { "gop-port-id", 0 },
+ Package () { "phy-mode", "5gbase-r"},
+ Package () { "phy-handle", \_SB.XSM2.PHY0},
+ }
+ })
+ }
+ }
+
+ Device (RNG2)
+ {
+ Name (_HID, "PRP0001") // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xF6760000, 0x7D)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)
+ {
+ CP_GIC_SPI_CP2_EIP_RNG0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "compatible", "inside-secure,safexcel-eip76" },
+ }
+ })
+ }
+
+ Device (PCI4)
+ {
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
+ Name (_SEG, 0x04) // _SEG: PCI Segment
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ Package () { 0xFFFF, 0x0, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x1, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x2, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x3, 0x0, 0x40 }
+ })
+
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ CP2_PCI0_BUS_MIN, // Range Minimum
+ CP2_PCI0_BUS_MAX, // Range Maximum
+ 0x0000, // Translation Offset
+ CP2_PCI0_BUS_COUNT // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ CP2_PCI0_MMIO32_BASE, // Range Minimum
+ CP2_PCI0_MMIO32_MAX, // Range Maximum
+ 0x00000000, // Translation Offset
+ CP2_PCI0_MMIO32_SIZE // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ CP2_PCI0_MMIO64_BASE, // Range Minimum
+ CP2_PCI0_MMIO64_MAX, // Range Maximum
+ 0x00000000, // Translation Offset
+ CP2_PCI0_MMIO64_SIZE // Length
+ )
+ DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Granularity
+ CP2_PCI0_IO_BASE, // Range Minimum
+ 0x0000FFFF, // Range Maximum
+ CP2_PCI0_IO_TRANSLATION, // Translation Address
+ CP2_PCI0_IO_SIZE, // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ })
+ Return (RBUF) /* \_SB_.PCI4._CRS.RBUF */
+ } // Method(_CRS)
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02")
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ CP2_PCI0_ECAM_BASE, // Range Minimum
+ CP2_PCI0_ECAM_SIZE // Length
+ )
+ })
+ }
+ Name (SUPP, 0x00)
+ Name (CTRL, 0x00)
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, 0x00, CDW1)
+ If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Store (CDW2, SUPP) /* \_SB_.PCI4.SUPP */
+ Store (CDW3, CTRL) /* \_SB_.PCI4.CTRL */
+ If (LNotEqual (And (SUPP, 0x16), 0x16))
+ {
+ And (CTRL, 0x1E, CTRL) /* \_SB_.PCI4.CTRL */
+ }
+
+ And (CTRL, 0x1D, CTRL) /* \_SB_.PCI4.CTRL */
+ If (LNotEqual (Arg1, One))
+ {
+ Or (CDW1, 0x08, CDW1) /* \_SB_.PCI4._OSC.CDW1 */
+ }
+
+ If (LNotEqual (CDW3, CTRL))
+ {
+ Or (CDW1, 0x10, CDW1) /* \_SB_.PCI4._OSC.CDW1 */
+ }
+
+ Store (CTRL, CDW3) /* \_SB_.PCI4._OSC.CDW3 */
+ Return (Arg3)
+ }
+ Else
+ {
+ Or (CDW1, 0x04, CDW1) /* \_SB_.PCI4._OSC.CDW1 */
+ Return (Arg3)
+ }
+ } // Method(_OSC)
+ }
+
+ Device (PCI5)
+ {
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
+ Name (_SEG, 0x05) // _SEG: PCI Segment
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number
+ Name (_UID, 0x05) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ Package () { 0xFFFF, 0x0, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x1, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x2, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x3, 0x0, 0x40 }
+ })
+
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ CP2_PCI1_BUS_MIN, // Range Minimum
+ CP2_PCI1_BUS_MAX, // Range Maximum
+ 0x0000, // Translation Offset
+ CP2_PCI1_BUS_COUNT // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ CP2_PCI1_MMIO32_BASE, // Range Minimum
+ CP2_PCI1_MMIO32_MAX, // Range Maximum
+ 0x00000000, // Translation Offset
+ CP2_PCI1_MMIO32_SIZE // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ CP2_PCI1_MMIO64_BASE, // Range Minimum
+ CP2_PCI1_MMIO64_MAX, // Range Maximum
+ 0x00000000, // Translation Offset
+ CP2_PCI1_MMIO64_SIZE // Length
+ )
+ DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Granularity
+ CP2_PCI1_IO_BASE, // Range Minimum
+ 0x0000FFFF, // Range Maximum
+ CP2_PCI1_IO_TRANSLATION, // Translation Address
+ CP2_PCI1_IO_SIZE, // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ })
+ Return (RBUF) /* \_SB_.PCI5._CRS.RBUF */
+ } // Method(_CRS)
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02")
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ CP2_PCI1_ECAM_BASE, // Range Minimum
+ CP2_PCI1_ECAM_SIZE // Length
+ )
+ })
+ }
+ Name (SUPP, 0x00)
+ Name (CTRL, 0x00)
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, 0x00, CDW1)
+ If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Store (CDW2, SUPP) /* \_SB_.PCI5.SUPP */
+ Store (CDW3, CTRL) /* \_SB_.PCI5.CTRL */
+ If (LNotEqual (And (SUPP, 0x16), 0x16))
+ {
+ And (CTRL, 0x1E, CTRL) /* \_SB_.PCI5.CTRL */
+ }
+
+ And (CTRL, 0x1D, CTRL) /* \_SB_.PCI5.CTRL */
+ If (LNotEqual (Arg1, One))
+ {
+ Or (CDW1, 0x08, CDW1) /* \_SB_.PCI5._OSC.CDW1 */
+ }
+
+ If (LNotEqual (CDW3, CTRL))
+ {
+ Or (CDW1, 0x10, CDW1) /* \_SB_.PCI5._OSC.CDW1 */
+ }
+
+ Store (CTRL, CDW3) /* \_SB_.PCI5._OSC.CDW3 */
+ Return (Arg3)
+ }
+ Else
+ {
+ Or (CDW1, 0x04, CDW1) /* \_SB_.PCI5._OSC.CDW1 */
+ Return (Arg3)
+ }
+ } // Method(_OSC)
+ }
+
+ Device (PCI6)
+ {
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
+ Name (_SEG, 0x06) // _SEG: PCI Segment
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number
+ Name (_UID, 0x06) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ Package () { 0xFFFF, 0x0, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x1, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x2, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x3, 0x0, 0x40 }
+ })
+
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ CP2_PCI2_BUS_MIN, // Range Minimum
+ CP2_PCI2_BUS_MAX, // Range Maximum
+ 0x0000, // Translation Offset
+ CP2_PCI2_BUS_COUNT // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ CP2_PCI2_MMIO32_BASE, // Range Minimum
+ CP2_PCI2_MMIO32_MAX, // Range Maximum
+ 0x00000000, // Translation Offset
+ CP2_PCI2_MMIO32_SIZE // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ CP2_PCI2_MMIO64_BASE, // Range Minimum
+ CP2_PCI2_MMIO64_MAX, // Range Maximum
+ 0x00000000, // Translation Offset
+ CP2_PCI2_MMIO64_SIZE // Length
+ )
+ DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Granularity
+ CP2_PCI2_IO_BASE, // Range Minimum
+ 0x0000FFFF, // Range Maximum
+ CP2_PCI2_IO_TRANSLATION, // Translation Address
+ CP2_PCI2_IO_SIZE, // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ })
+ Return (RBUF) /* \_SB_.PCI6._CRS.RBUF */
+ } // Method(_CRS)
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02")
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ CP2_PCI2_ECAM_BASE, // Range Minimum
+ CP2_PCI2_ECAM_SIZE // Length
+ )
+ })
+ }
+ Name (SUPP, 0x00)
+ Name (CTRL, 0x00)
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, 0x00, CDW1)
+ If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Store (CDW2, SUPP) /* \_SB_.PCI6.SUPP */
+ Store (CDW3, CTRL) /* \_SB_.PCI6.CTRL */
+ If (LNotEqual (And (SUPP, 0x16), 0x16))
+ {
+ And (CTRL, 0x1E, CTRL) /* \_SB_.PCI6.CTRL */
+ }
+
+ And (CTRL, 0x1D, CTRL) /* \_SB_.PCI6.CTRL */
+ If (LNotEqual (Arg1, One))
+ {
+ Or (CDW1, 0x08, CDW1) /* \_SB_.PCI6._OSC.CDW1 */
+ }
+
+ If (LNotEqual (CDW3, CTRL))
+ {
+ Or (CDW1, 0x10, CDW1) /* \_SB_.PCI6._OSC.CDW1 */
+ }
+
+ Store (CTRL, CDW3) /* \_SB_.PCI6._OSC.CDW3 */
+ Return (Arg3)
+ }
+ Else
+ {
+ Or (CDW1, 0x04, CDW1) /* \_SB_.PCI6._OSC.CDW1 */
+ Return (Arg3)
+ }
+ } // Method(_OSC)
+ }
+ }
+}
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl
new file mode 100644
index 0000000000..c54937fc7b
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl
@@ -0,0 +1,120 @@
+/** @file
+
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.<BR>
+ Copyright (C) 2021, Semihalf.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+DefinitionBlock ("Cn913xCEx7.aml", "DSDT", 2, "MRVL", "CN9130", 3)
+{
+ Scope (_SB)
+ {
+ Device (CPU0)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x000) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ }
+ Device (CPU1)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x001) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ }
+ Device (CPU2)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x100) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ }
+ Device (CPU3)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x101) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ }
+
+ Device (MMC0)
+ {
+ Name (_HID, "MRVL0003") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF06E0000, // Address Base (MMIO)
+ 0x00000300, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 48
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", 400000000 },
+ Package () { "bus-width", 8 },
+ Package () { "no-sd", 0x1 },
+ Package () { "no-sdio", 0x1 },
+ Package () { "mmc-ddr-1_8v", 0x1 },
+ Package () { "mmc-hs400-1_8v", 0x1 },
+ Package () { "non-removable", 0x1 },
+ }
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, "MRVL0001") // _HID: Hardware ID
+ Name (_CID, "HISI0031") // _CID: Compatible ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
+ Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ FixedPcdGet64(PcdSerialRegisterBase), // Address Base
+ 0x00000100, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 51
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", FixedPcdGet32 (PcdSerialClockRate) },
+ Package () { "reg-io-width", 1 },
+ Package () { "reg-shift", 2 },
+ }
+ })
+ }
+ }
+}
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc
new file mode 100644
index 0000000000..143da73f5c
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc
@@ -0,0 +1,74 @@
+/** @file
+* Debug Port Table (DBG2)
+*
+* Copyright (c) 2020 Linaro Ltd. All rights reserved.
+* Copyright (c) 2021 ARM Ltd. All rights reserved.
+* Copyright (c) 2021 Semihalf. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/DebugPort2Table.h>
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+
+#include "AcpiHeader.h"
+#include "Cn913xCEx7Eval/Dbg2.h"
+
+#pragma pack(1)
+
+#define CN913X_UART_STR { '\\', '_', 'S', 'B', '.', 'C', 'O', 'M', '2', 0x00 }
+
+typedef struct {
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister;
+ UINT32 AddressSize;
+ UINT8 NameSpaceString[10];
+} DBG2_DEBUG_DEVICE_INFORMATION;
+
+typedef struct {
+ EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description;
+ DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo;
+} DBG2_TABLE;
+
+
+STATIC DBG2_TABLE Dbg2 = {
+ {
+ __ACPI_HEADER (
+ EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE,
+ DBG2_TABLE,
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION
+ ),
+ OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo),
+ 1 /* NumberOfDebugPorts */
+ },
+ {
+ {
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
+ sizeof (DBG2_DEBUG_DEVICE_INFORMATION),
+ 1, /* NumberofGenericAddressRegisters */
+ 10, /* NameSpaceStringLength */
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString),
+ 0, /* OemDataLength */
+ 0, /* OemDataOffset */
+ EFI_ACPI_DBG2_PORT_TYPE_SERIAL,
+ EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_SUBSET_COMPATIBLE_WITH_MS_DBGP_SPEC,
+ {
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE
+ },
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister),
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize)
+ },
+ MV_UART_AS32 (CN913X_DBG2_UART_REG_BASE), /* BaseAddress */
+ SIZE_4KB, /* AddressSize */
+ CN913X_UART_STR, /* NameSpaceString */
+ }
+};
+
+#pragma pack()
+
+// Reference the table being generated to prevent the optimizer from removing
+// the data structure from the executable
+VOID* CONST ReferenceAcpiTable = &Dbg2;
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc
new file mode 100644
index 0000000000..181bbe5530
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc
@@ -0,0 +1,87 @@
+/** @file
+
+ Memory mapped config space base address table (MCFG)
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.<BR>
+ Copyright (C) 2021, Semihalf.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/AcpiLib.h>
+
+#include "AcpiHeader.h"
+#include "Cn913xCEx7Eval/Pcie.h"
+
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure[7];
+} ACPI_6_0_MCFG_STRUCTURE;
+#pragma pack()
+
+STATIC ACPI_6_0_MCFG_STRUCTURE Mcfg = {
+ {
+ __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ ACPI_6_0_MCFG_STRUCTURE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION),
+ EFI_ACPI_RESERVED_QWORD
+ },
+ {
+ {
+ CP0_PCI0_ECAM_BASE, // BaseAddress
+ 0, // PciSegmentGroupNumber
+ CP0_PCI0_BUS_MIN, // StartBusNumber
+ CP0_PCI0_BUS_MAX, // EndBusNumber
+ EFI_ACPI_RESERVED_DWORD // Reserved
+ },
+ {
+ CP1_PCI0_ECAM_BASE, // BaseAddress
+ 1, // PciSegmentGroupNumber
+ CP1_PCI0_BUS_MIN, // StartBusNumber
+ CP1_PCI0_BUS_MAX, // EndBusNumber
+ EFI_ACPI_RESERVED_DWORD // Reserved
+ },
+ {
+ CP1_PCI1_ECAM_BASE, // BaseAddress
+ 2, // PciSegmentGroupNumber
+ CP1_PCI1_BUS_MIN, // StartBusNumber
+ CP1_PCI1_BUS_MAX, // EndBusNumber
+ EFI_ACPI_RESERVED_DWORD // Reserved
+ },
+ {
+ CP1_PCI2_ECAM_BASE, // BaseAddress
+ 3, // PciSegmentGroupNumber
+ CP1_PCI2_BUS_MIN, // StartBusNumber
+ CP1_PCI2_BUS_MAX, // EndBusNumber
+ EFI_ACPI_RESERVED_DWORD // Reserved
+ },
+ {
+ CP2_PCI0_ECAM_BASE, // BaseAddress
+ 4, // PciSegmentGroupNumber
+ CP2_PCI0_BUS_MIN, // StartBusNumber
+ CP2_PCI0_BUS_MAX, // EndBusNumber
+ EFI_ACPI_RESERVED_DWORD // Reserved
+ },
+ {
+ CP2_PCI1_ECAM_BASE, // BaseAddress
+ 5, // PciSegmentGroupNumber
+ CP2_PCI1_BUS_MIN, // StartBusNumber
+ CP2_PCI1_BUS_MAX, // EndBusNumber
+ EFI_ACPI_RESERVED_DWORD // Reserved
+ },
+ {
+ CP2_PCI2_ECAM_BASE, // BaseAddress
+ 6, // PciSegmentGroupNumber
+ CP2_PCI2_BUS_MIN, // StartBusNumber
+ CP2_PCI2_BUS_MAX, // EndBusNumber
+ EFI_ACPI_RESERVED_DWORD // Reserved
+ }
+ }
+};
+
+VOID CONST * CONST ReferenceAcpiTable = &Mcfg;
--
2.29.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [edk2-platforms PATCH v2 3/3] SolidRun/Cn913xCEx7Eval: Add platform support
2021-08-07 19:36 [edk2-platforms PATCH v2 0/4] SolidRun CEx7 Evaluation Board support Marcin Wojtas
2021-08-07 19:36 ` [edk2-platforms PATCH v2 1/3] Marvell: Armada7k8k/OcteonTx: Select ACPI description as a default Marcin Wojtas
2021-08-07 19:36 ` [edk2-platforms PATCH v2 2/3] SolidRun/Cn913xCEx7Eval: Add ACPI support Marcin Wojtas
@ 2021-08-07 19:36 ` Marcin Wojtas
2021-08-07 19:36 ` [edk2-non-osi PATCH] SolidRun/Cn913xCEx7Eval: Add DeviceTree Marcin Wojtas
2021-08-17 15:56 ` [edk2-platforms PATCH v2 0/4] SolidRun CEx7 Evaluation Board support Ard Biesheuvel
4 siblings, 0 replies; 7+ messages in thread
From: Marcin Wojtas @ 2021-08-07 19:36 UTC (permalink / raw)
To: devel
Cc: leif, ardb+tianocore, jaz, gjb, Samer.El-Haj-Mahmoud, jon,
alon.rotman, Marcin Wojtas
This patch adds the required platform description files, along with
the hardware configuration libraries, for the SolidRun
CN913x CEx7 Evaluation Board. Supported interfaces:
* SPI flash & memory-mapped variable storage access
* uSD
* eMMC
* 7x PCIE root complex
* USB
* Networking:
* 1Gbps RGMII via PHY
* 2500Base-X via quad 1Gpbs switch
* 5Gbps via SFP cage and PHY
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc | 54 ++++
Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc | 64 +++++
Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc | 64 +++++
Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc | 68 +++++
Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc | 57 ++++
Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf | 30 ++
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf | 38 +++
Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.h | 31 +++
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.h | 13 +
Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.c | 294 ++++++++++++++++++++
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 89 ++++++
Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc | 17 ++
12 files changed, 819 insertions(+)
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.h
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.h
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.c
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.c
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc b/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
new file mode 100644
index 0000000000..ad0983087d
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
@@ -0,0 +1,54 @@
+## @file
+# Component description file for the CN9130 Development Board (variant A)
+#
+# Copyright (c) 2019 Marvell International Ltd.<BR>
+# Copyright (c) 2021 Semihalf.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+ # ComPhy
+ gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
+ # ComPhy0
+ # 0: PCIE0 5 Gbps
+ # 1: PCIE0 5 Gbps
+ # 2: PCIE0 5 Gbps
+ # 3: PCIE0 5 Gbps
+ # 4: SFI 10.31 Gbps
+ # 5: SGMII2 3.125 Gbps
+ gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SGMII2)}
+ gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
+
+ # UtmiPhy
+ gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+
+ # MDIO
+ gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1 }
+
+ # PHY
+ gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+
+ # NET
+ gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_SGMII) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF }
+ gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
+ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
+
+ # NonDiscoverableDevices
+ gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc b/Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc
new file mode 100644
index 0000000000..c6b0cefa8d
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc
@@ -0,0 +1,64 @@
+## @file
+# Component description file for the CN9131 Development Board (variant A)
+#
+# Copyright (c) 2019 Marvell International Ltd.<BR>
+# Copyright (c) 2021 Semihalf.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+ # CP115 count
+ gMarvellTokenSpaceGuid.PcdMaxCpCount|2
+
+ # MPP
+ gMarvellTokenSpaceGuid.PcdMppChipCount|3
+
+ # CP115 #1 MPP
+ gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
+ gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
+ gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0x7 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x7, 0x0, 0x0, 0x0, 0x2, 0x2, 0x2, 0x8, 0x8, 0x9 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+ # ComPhy
+ gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
+ # ComPhy1
+ # 0: PCIE0 5 Gbps
+ # 1: PCIE0 5 Gbps
+ # 2: SFI 5.15625 Gbps
+ # 3: SATA1 5 Gbps
+ # 4: PCIE1 5 Gbps
+ # 5: PCIE2 5 Gbps
+ gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)}
+ gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5_15625G), $(CP_5G), $(CP_5G), $(CP_5G) }
+
+ # UtmiPhy
+ gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+
+ # NET
+ gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_SGMII), $(PHY_SFI) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
+
+ # NonDiscoverableDevices
+ gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc b/Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc
new file mode 100644
index 0000000000..34f9a3f2fb
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc
@@ -0,0 +1,64 @@
+## @file
+# Component description file for the CN9132 Development Board (variant A)
+#
+# Copyright (c) 2019 Marvell International Ltd.<BR>
+# Copyright (c) 2021 Semihalf.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+ # CP115 count
+ gMarvellTokenSpaceGuid.PcdMaxCpCount|3
+
+ # MPP
+ gMarvellTokenSpaceGuid.PcdMppChipCount|4
+
+ # CP115 #2 MPP
+ gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000
+ gMarvellTokenSpaceGuid.PcdChip3MppPinCount|64
+ gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0x7, 0x7 }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x7, 0x0, 0x0, 0xFF, 0xFF, 0x2, 0x2, 0x8, 0x8, 0xFF }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0xFF, 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0xFF, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+ # ComPhy
+ gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 }
+ # ComPhy2
+ # 0: PCIE0 5 Gbps
+ # 1: USB3_HOST0 5 Gbps
+ # 2: SFI 5.15625 Gbps
+ # 3: SATA1 5 Gbps
+ # 4: PCIE1 5 Gbps
+ # 5: PCIE2 5 Gbps
+ gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)}
+ gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5_15625G), $(CP_5G), $(CP_5G), $(CP_5G) }
+
+ # UtmiPhy
+ gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+
+ # NET
+ gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000), $(PHY_SPEED_10000) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_SGMII), $(PHY_SFI), $(PHY_SFI) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 }
+ gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 }
+
+ # NonDiscoverableDevices
+ gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc
new file mode 100644
index 0000000000..17463c09c6
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc
@@ -0,0 +1,68 @@
+## @file
+# Component description file for the CN9130 Development Board (variant A)
+#
+# Copyright (c) 2019 Marvell International Ltd.<BR>
+# Copyright (c) 2021 Semihalf.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+ # CP115 count
+ gMarvellTokenSpaceGuid.PcdMaxCpCount|1
+
+ # MPP
+ gMarvellTokenSpaceGuid.PcdMppChipCount|2
+
+ # APN807 MPP
+ gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+ gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
+ gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
+
+ # CP115 #0 MPP
+ gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
+ gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
+ gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0x7 }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x7, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2, 0x2, 0x2, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x8, 0x8, 0x8, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x6, 0x6, 0x2, 0x0, 0x2, 0xB, 0xE, 0xE, 0xE, 0xE }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+ # I2C
+ gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50 }
+ gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }
+ gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000
+ gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
+
+ # SPI
+ gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680
+ gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
+ gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
+
+ gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
+ gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
+
+ # NonDiscoverableDevices
+ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 }
+
+ # RTC
+ gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000
+
+ # Variable store
+ gMarvellTokenSpaceGuid.PcdSpiMemoryBase|0xEF000000
+[PcdsDynamicDefault.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0xEF3C0000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0xEF3E0000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0xEF3D0000
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc
new file mode 100644
index 0000000000..6cb82acb13
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc
@@ -0,0 +1,57 @@
+## @file
+# Component description file for the CN913x CEx7 Evaluation Board
+#
+# Copyright (c) 2021 Semihalf
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = Cn913xCEx7Eval
+ PLATFORM_GUID = 4e2ffdd1-c82e-497e-936b-76217e54848a
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001B
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH)
+ SUPPORTED_ARCHITECTURES = AARCH64|ARM
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
+ BOARD_DXE_FV_COMPONENTS = Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc
+ CAPSULE_ENABLE = TRUE
+
+ #
+ # Network definition
+ #
+ DEFINE NETWORK_IP6_ENABLE = FALSE
+ DEFINE NETWORK_TLS_ENABLE = FALSE
+ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE
+ DEFINE NETWORK_ISCSI_ENABLE = FALSE
+
+!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+!include MdePkg/MdeLibs.dsc.inc
+!include Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc
+!include Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
+!include Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc
+!include Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc
+
+[Components.common]
+ Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf
+
+[Components.AARCH64]
+ Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf
+
+[LibraryClasses.common]
+ NonDiscoverableInitLib|Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
+ ArmadaBoardDescLib|Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf
+
+[PcdsFixedAtBuild.common]
+ #Platform description
+ gMarvellTokenSpaceGuid.PcdProductManufacturer|"SolidRun"
+ gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN913x CEx7 Evaluation Board"
+ gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.1"
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf
new file mode 100644
index 0000000000..ea13ff7ad7
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf
@@ -0,0 +1,30 @@
+## @file
+#
+# Copyright (C) 2019, Marvell International Ltd. and its affiliates<BR>
+# Copyright (C) 2021, Semihalf<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = Cn913xCEx7EvalBoardDescriptionLib
+ FILE_GUID = 97c47d82-b9b9-4bff-9175-3f26671efea6
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmadaBoardDescLib
+
+[Sources]
+ BoardDescriptionLib.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Marvell/Marvell.dec
+
+[LibraryClasses]
+ DebugLib
+ IoLib
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
new file mode 100644
index 0000000000..c58ba8397a
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
@@ -0,0 +1,38 @@
+## @file
+#
+# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+# Copyright (c) 2019, Marvell International Ltd. All rights reserved.<BR>
+# Copyright (c) 2021, Semihalf. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = Cn913xCExEvalNonDiscoverableInitLib
+ FILE_GUID = 8e6a8766-df51-497f-9743-fc0d9170ced8
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NonDiscoverableInitLib
+
+[Sources]
+ NonDiscoverableInitLib.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Marvell/Marvell.dec
+
+[LibraryClasses]
+ DebugLib
+ IoLib
+ MvGpioLib
+
+[Protocols]
+ gEmbeddedGpioProtocolGuid
+
+[Depex]
+ gMarvellPlatformInitCompleteProtocolGuid
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.h b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.h
new file mode 100644
index 0000000000..6e04c9cd9e
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.h
@@ -0,0 +1,31 @@
+/**
+*
+* Copyright (C) 2021, Semihalf.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#ifndef BOARD_DESCRIPTION_LIB_H__
+#define BOARD_DESCRIPTION_LIB_H__
+
+#define IO_WIN_ALR_OFFSET(WinId) (0xF06F0000 + 0x0 + (0x10 * (WinId)))
+#define IO_WIN_AHR_OFFSET(WinId) (0xF06F0000 + 0x8 + (0x10 * (WinId)))
+#define IO_WIN_CR_OFFSET(WinId) (0xF06F0000 + 0xC + (0x10 * (WinId)))
+#define IO_WIN_ENABLE_BIT 0x1
+#define IO_WIN_ADDRESS_SHIFT 16
+#define IO_WIN_ADDRESS_MASK 0xFFFFFFF0
+
+#define MCI0_TARGET_ID 0x0
+#define MCI1_TARGET_ID 0x1
+#define CP1_PCIE_WIN64_BASE 0x890000000
+#define CP1_PCIE_WIN64_SIZE 0x30000000
+#define CP1_PCIE_WIN64_ID 0x5
+#define CP2_PCIE_WIN64_BASE 0x8c0000000
+#define CP2_PCIE_WIN64_SIZE 0x30000000
+#define CP2_PCIE_WIN64_ID 0x6
+
+#define CP0_GPIO1_DATA_OUT_REG 0xF2440140
+#define CP0_GPIO1_OUT_EN_REG 0xF2440144
+#define CP0_GPIO1_PIN_MASK (1 << 7)
+
+#endif
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.h b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.h
new file mode 100644
index 0000000000..937b84b99d
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.h
@@ -0,0 +1,13 @@
+/**
+*
+* Copyright (c) 2021, Semihalf. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#ifndef NON_DISCOVERABLE_INIT_LIB_H__
+#define NON_DISCOVERABLE_INIT_LIB_H__
+
+#define CN913X_CEX7_AP_SDMMC_VCCQ_PIN 26
+
+#endif
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.c b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.c
new file mode 100644
index 0000000000..f5bb6302fe
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.c
@@ -0,0 +1,294 @@
+/**
+*
+* Copyright (C) 2021, Semihalf.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Uefi.h>
+
+#include <Library/ArmadaBoardDescLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/MvGpioLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include "BoardDescriptionLib.h"
+
+STATIC
+VOID
+ConfigureIoWindow (
+ UINT64 WinBaseAddress,
+ UINT64 WinSize,
+ UINTN WinId,
+ UINT32 WinTargetId
+ )
+{
+ UINT32 AddressHigh;
+ UINT32 AddressLow;
+ UINT64 MaxAddress;
+
+ /* Disable IO window. */
+ MmioWrite32 (IO_WIN_ALR_OFFSET(WinId), 0);
+
+ /* Calculate the end address. */
+ MaxAddress = (WinBaseAddress + WinSize - 1);
+
+ AddressLow = (UINT32)((WinBaseAddress >> IO_WIN_ADDRESS_SHIFT) & IO_WIN_ADDRESS_MASK);
+ AddressLow |= IO_WIN_ENABLE_BIT;
+ AddressHigh = (UINT32)((MaxAddress >> IO_WIN_ADDRESS_SHIFT) & IO_WIN_ADDRESS_MASK);
+
+ /* Write start address and end address for IO window. */
+ MmioWrite32 (IO_WIN_ALR_OFFSET(WinId), AddressLow);
+ MmioWrite32 (IO_WIN_AHR_OFFSET(WinId), AddressHigh);
+
+ /* Write window target. */
+ MmioWrite32 (IO_WIN_CR_OFFSET(WinId), WinTargetId);
+}
+
+//
+// General purpose routine for per-board initalization
+//
+EFI_STATUS
+ArmadaBoardInit (
+ VOID
+ )
+{
+ /*
+ * Due to lack of sufficient number of IO windows registers,
+ * the CP1/CP2 PCIE configuration must be performed after the
+ * early firmware stages. Replace the MCI 0/1 indirect
+ * windows, which are no longer needed.
+ */
+ ConfigureIoWindow (
+ CP1_PCIE_WIN64_BASE,
+ CP1_PCIE_WIN64_SIZE,
+ CP1_PCIE_WIN64_ID,
+ MCI0_TARGET_ID
+ );
+
+ ConfigureIoWindow (
+ CP2_PCIE_WIN64_BASE,
+ CP2_PCIE_WIN64_SIZE,
+ CP2_PCIE_WIN64_ID,
+ MCI1_TARGET_ID
+ );
+
+ /* Enable FAN */
+ MmioAnd32 (CP0_GPIO1_DATA_OUT_REG, ~CP0_GPIO1_PIN_MASK);
+ MmioAnd32 (CP0_GPIO1_OUT_EN_REG, ~CP0_GPIO1_PIN_MASK);
+
+ return EFI_SUCCESS;
+}
+
+//
+// GPIO Expander
+//
+EFI_STATUS
+EFIAPI
+ArmadaBoardGpioExpanderGet (
+ IN OUT MV_GPIO_EXPANDER **GpioExpanders,
+ IN OUT UINTN *GpioExpanderCount
+ )
+{
+ /* No GPIO expanders on board */
+ *GpioExpanders = NULL;
+ *GpioExpanderCount = 0;
+
+ return EFI_SUCCESS;
+}
+
+//
+// PCIE
+//
+STATIC
+MV_PCIE_CONTROLLER mPcieController[] = {
+ { /* CP0 PCIE0 @0xF2600000 */
+ .PcieDbiAddress = 0xF2600000,
+ .ConfigSpaceAddress = 0x800000000,
+ .HaveResetGpio = FALSE,
+ .PcieResetGpio = { 0 },
+ .PcieBusMin = 0,
+ .PcieBusMax = 0xFE,
+ .PcieIoTranslation = 0x80FF00000,
+ .PcieIoWinBase = 0x0,
+ .PcieIoWinSize = 0x10000,
+ .PcieMmio32Translation = 0,
+ .PcieMmio32WinBase = 0xC0000000,
+ .PcieMmio32WinSize = 0x20000000,
+ .PcieMmio64Translation = 0,
+ .PcieMmio64WinBase = 0x810000000,
+ .PcieMmio64WinSize = 0x80000000,
+ },
+ { /* CP1 PCIE0 @0xF4600000 */
+ .PcieDbiAddress = 0xF4600000,
+ .ConfigSpaceAddress = 0xE2000000,
+ .HaveResetGpio = FALSE,
+ .PcieResetGpio = { 0 },
+ .PcieBusMin = 0,
+ .PcieBusMax = 0xE,
+ .PcieIoTranslation = 0xE2F00000,
+ .PcieIoWinBase = 0x0,
+ .PcieIoWinSize = 0x10000,
+ .PcieMmio32Translation = 0,
+ .PcieMmio32WinBase = 0xE3000000,
+ .PcieMmio32WinSize = 0x1000000,
+ .PcieMmio64Translation = 0,
+ .PcieMmio64WinBase = 0x890000000,
+ .PcieMmio64WinSize = 0x10000000,
+ },
+ { /* CP1 PCIE1 @0xF4620000 */
+ .PcieDbiAddress = 0xF4620000,
+ .ConfigSpaceAddress = 0xE4000000,
+ .HaveResetGpio = FALSE,
+ .PcieResetGpio = { 0 },
+ .PcieBusMin = 0,
+ .PcieBusMax = 0xE,
+ .PcieIoTranslation = 0xE4F00000,
+ .PcieIoWinBase = 0x0,
+ .PcieIoWinSize = 0x10000,
+ .PcieMmio32Translation = 0,
+ .PcieMmio32WinBase = 0xE5000000,
+ .PcieMmio32WinSize = 0x1000000,
+ .PcieMmio64Translation = 0,
+ .PcieMmio64WinBase = 0x8A0000000,
+ .PcieMmio64WinSize = 0x10000000,
+ },
+ { /* CP1 PCIE2 @0xF4640000 */
+ .PcieDbiAddress = 0xF4640000,
+ .ConfigSpaceAddress = 0xE6000000,
+ .HaveResetGpio = FALSE,
+ .PcieResetGpio = { 0 },
+ .PcieBusMin = 0,
+ .PcieBusMax = 0xE,
+ .PcieIoTranslation = 0xE6F00000,
+ .PcieIoWinBase = 0x0,
+ .PcieIoWinSize = 0x10000,
+ .PcieMmio32Translation = 0,
+ .PcieMmio32WinBase = 0xE7000000,
+ .PcieMmio32WinSize = 0x1000000,
+ .PcieMmio64Translation = 0,
+ .PcieMmio64WinBase = 0x8B0000000,
+ .PcieMmio64WinSize = 0x10000000,
+ },
+ { /* CP2 PCIE0 @0xF6600000 */
+ .PcieDbiAddress = 0xF6600000,
+ .ConfigSpaceAddress = 0xE9000000,
+ .HaveResetGpio = FALSE,
+ .PcieResetGpio = { 0 },
+ .PcieBusMin = 0,
+ .PcieBusMax = 0xE,
+ .PcieIoTranslation = 0xE9F00000,
+ .PcieIoWinBase = 0x0,
+ .PcieIoWinSize = 0x10000,
+ .PcieMmio32Translation = 0,
+ .PcieMmio32WinBase = 0xEA000000,
+ .PcieMmio32WinSize = 0x1000000,
+ .PcieMmio64Translation = 0,
+ .PcieMmio64WinBase = 0x8C0000000,
+ .PcieMmio64WinSize = 0x10000000,
+ },
+ { /* CP2 PCIE1 @0xF6620000 */
+ .PcieDbiAddress = 0xF6620000,
+ .ConfigSpaceAddress = 0xEB000000,
+ .HaveResetGpio = FALSE,
+ .PcieResetGpio = { 0 },
+ .PcieBusMin = 0,
+ .PcieBusMax = 0xE,
+ .PcieIoTranslation = 0xEBF00000,
+ .PcieIoWinBase = 0x0,
+ .PcieIoWinSize = 0x10000,
+ .PcieMmio32Translation = 0,
+ .PcieMmio32WinBase = 0xEC000000,
+ .PcieMmio32WinSize = 0x1000000,
+ .PcieMmio64Translation = 0,
+ .PcieMmio64WinBase = 0x8D0000000,
+ .PcieMmio64WinSize = 0x10000000,
+ },
+ { /* CP2 PCIE2 @0xF6640000 */
+ .PcieDbiAddress = 0xF6640000,
+ .ConfigSpaceAddress = 0xED000000,
+ .HaveResetGpio = FALSE,
+ .PcieResetGpio = { 0 },
+ .PcieBusMin = 0,
+ .PcieBusMax = 0xE,
+ .PcieIoTranslation = 0xEDF00000,
+ .PcieIoWinBase = 0x0,
+ .PcieIoWinSize = 0x10000,
+ .PcieMmio32Translation = 0,
+ .PcieMmio32WinBase = 0xEE000000,
+ .PcieMmio32WinSize = 0x1000000,
+ .PcieMmio64Translation = 0,
+ .PcieMmio64WinBase = 0x8E0000000,
+ .PcieMmio64WinSize = 0x10000000,
+ },
+};
+
+/**
+ Return the number and description of PCIE controllers used on the platform.
+
+ @param[in out] **PcieControllers Array containing PCIE controllers'
+ description.
+ @param[in out] *PcieControllerCount Amount of used PCIE controllers.
+
+ @retval EFI_SUCCESS The data were obtained successfully.
+ @retval other Return error status.
+
+**/
+EFI_STATUS
+EFIAPI
+ArmadaBoardPcieControllerGet (
+ IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers,
+ IN OUT UINTN *PcieControllerCount
+ )
+{
+ *PcieControllers = mPcieController;
+ *PcieControllerCount = ARRAY_SIZE (mPcieController);
+
+ return EFI_SUCCESS;
+}
+
+//
+// Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDescLib
+//
+STATIC
+MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] = {
+ { /* eMMC 0xF06E0000 */
+ 0, /* SOC will be filled by MvBoardDescDxe */
+ 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */
+ TRUE, /* Xenon1v8Enabled */
+ /*
+ * Force 4-bit bus width - work-around for non
+ * functional HS400 mode.
+ */
+ FALSE, /* Xenon8BitBusEnabled */
+ FALSE, /* XenonSlowModeEnabled */
+ 0x40, /* XenonTuningStepDivisor */
+ EmbeddedSlot /* SlotType */
+ },
+ { /* SD/MMC 0xF2780000 */
+ 0, /* SOC will be filled by MvBoardDescDxe */
+ 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */
+ FALSE, /* Xenon1v8Enabled */
+ FALSE, /* Xenon8BitBusEnabled */
+ FALSE, /* XenonSlowModeEnabled */
+ 0x19, /* XenonTuningStepDivisor */
+ EmbeddedSlot /* SlotType */
+ },
+};
+
+EFI_STATUS
+EFIAPI
+ArmadaBoardDescSdMmcGet (
+ OUT UINTN *SdMmcDevCount,
+ OUT MV_BOARD_SDMMC_DESC **SdMmcDesc
+ )
+{
+ *SdMmcDesc = mSdMmcDescTemplate;
+ *SdMmcDevCount = ARRAY_SIZE (mSdMmcDescTemplate);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.c b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.c
new file mode 100644
index 0000000000..18312ac403
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.c
@@ -0,0 +1,89 @@
+/**
+*
+* Copyright (c) 2017, Linaro Ltd. All rights reserved.
+* Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+* Copyright (c) 2021, Semihalf. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Uefi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/MvGpioLib.h>
+#include <Library/NonDiscoverableDeviceRegistrationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/NonDiscoverableDevice.h>
+
+#include "NonDiscoverableInitLib.h"
+
+STATIC
+EFI_STATUS
+EFIAPI
+ConfigurePins (
+ IN CONST MV_GPIO_PIN *VbusPin,
+ IN UINTN PinCount,
+ IN MV_GPIO_DRIVER_TYPE DriverType
+ )
+{
+ EMBEDDED_GPIO_MODE Mode;
+ EMBEDDED_GPIO_PIN Gpio;
+ EMBEDDED_GPIO *GpioProtocol;
+ EFI_STATUS Status;
+ UINTN Index;
+
+ Status = MvGpioGetProtocol (DriverType, &GpioProtocol);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Unable to find GPIO protocol\n", __FUNCTION__));
+ return Status;
+ }
+
+ for (Index = 0; Index < PinCount; Index++) {
+ Mode = VbusPin->ActiveHigh ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0;
+ Gpio = GPIO (VbusPin->ControllerId, VbusPin->PinNumber);
+ GpioProtocol->Set (GpioProtocol, Gpio, Mode);
+ VbusPin++;
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC CONST MV_GPIO_PIN mApSdMmcPins[] = {
+ {
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,
+ MV_GPIO_CP0_CONTROLLER0,
+ CN913X_CEX7_AP_SDMMC_VCCQ_PIN,
+ TRUE,
+ },
+};
+
+STATIC
+EFI_STATUS
+EFIAPI
+ApSdMmcInit (
+ IN NON_DISCOVERABLE_DEVICE *This
+ )
+{
+ return ConfigurePins (mApSdMmcPins,
+ ARRAY_SIZE (mApSdMmcPins),
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER);
+}
+
+NON_DISCOVERABLE_DEVICE_INIT
+EFIAPI
+NonDiscoverableDeviceInitializerGet (
+ IN NON_DISCOVERABLE_DEVICE_TYPE Type,
+ IN UINTN Index
+ )
+{
+ if (Type == NonDiscoverableDeviceTypeSdhci && Index == 0) {
+ return ApSdMmcInit;
+ }
+
+ return NULL;
+}
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc
new file mode 100644
index 0000000000..6cf2be0b1e
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2021 Semihalf
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+# Per-board additional content of the DXE phase firmware volume
+
+ INF Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf
+
+ # DTB
+ INF RuleOverride = DTB Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf
+
+ # ACPI support
+!if $(ARCH) == AARCH64
+ INF RuleOverride = ACPITABLE Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf
+!endif
--
2.29.0
^ permalink raw reply related [flat|nested] 7+ messages in thread