From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) by mx.groups.io with SMTP id smtpd.web10.2194.1628365058462750321 for ; Sat, 07 Aug 2021 12:37:39 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=t2+FEnEv; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.208.177, mailfrom: mw@semihalf.com) Received: by mail-lj1-f177.google.com with SMTP id u13so17220898lje.5 for ; Sat, 07 Aug 2021 12:37:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f3+2w2dk8cLh/0NCDI5t8Tb3pk20G3u/zPLIOb7iNII=; b=t2+FEnEvDy58Zxe0//1L2wnm15MqBgi1wEgfid2W9+xWAdrMqXkGfGRNosmHKAkJJe Zn71KJbyGflFLhxj3lH7v/D1TDXtWTIGPryreJ0wdJWDk3GX6uRWKRIc0/1f5RnbrVPu 4CDvkN5ILj29QarpvPZWdUgiNg1XzbUJpgb7ufYoLFpymJhXK3yq/LEmgf1xkPa2lZIw a/iv5bP/wZlaKpIehRFk2cBhNuUKwG6bfZsTunoGNadRvtscz9wrktal5F+Y7bCjygkn hPNW/xpkx/T6sHlE0Ght7cRv56c/rMy3+JzRaskpVWUlXmUl7dwTmFZlKS8s5zaeDOou 2phw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f3+2w2dk8cLh/0NCDI5t8Tb3pk20G3u/zPLIOb7iNII=; b=gbMidUSR4/TufOR2ak3POvlF/Yq8YZ0n/FCutmmRqe0Er06FN4lTKB6MjG9ekfV+x3 E5ZyNPR9eL4dry256gYEZ6NXEu9EKFUCDlJwWF8R8WxYKFjUpqM1oFUXVOHCZwJC1+69 xkEAuqyVTyezACEFVXKF40KBTjS5bLfn0ZMNKdrm3BOBlfE65NmLOD8SMQdRYYoKY1I7 +zkVFTadT4Hq0H8hJb0rxqIR5RSSlazmrT7DF/29+2uNmIhsMt/NmxX97q4viyDlmho8 bCKanUMZ1F4K9y01zqQJiU6TtxWpkHI9y8ctdjUtxU43dgY6wwJ+4sofmY2hxdfTRs84 hjxA== X-Gm-Message-State: AOAM5309firhwfbNE0yvGOC3ZaLwp3vEv2VkbWyoT+P2kgNHioB3LPzC 30mstskUsh7Ug19ho70aRpw9GqugP+hN85bz X-Google-Smtp-Source: ABdhPJyWuiTPVcP7XpCYz1wR3EBdH752bKLqRkb0fX8EjcPTHSMBzjmdeakqidCGbiupG4Yf8PuHqw== X-Received: by 2002:a2e:580e:: with SMTP id m14mr10464726ljb.9.1628365056620; Sat, 07 Aug 2021 12:37:36 -0700 (PDT) Return-Path: Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id bq33sm103635lfb.88.2021.08.07.12.37.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Aug 2021 12:37:36 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, alon.rotman@solid-run.com, Marcin Wojtas Subject: [edk2-platforms PATCH v2 3/3] SolidRun/Cn913xCEx7Eval: Add platform support Date: Sat, 7 Aug 2021 21:36:40 +0200 Message-Id: <20210807193641.3355697-4-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210807193641.3355697-1-mw@semihalf.com> References: <20210807193641.3355697-1-mw@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable This patch adds the required platform description files, along with the hardware configuration libraries, for the SolidRun CN913x CEx7 Evaluation Board. Supported interfaces: * SPI flash & memory-mapped variable storage access * uSD * eMMC * 7x PCIE root complex * USB * Networking: * 1Gbps RGMII via PHY * 2500Base-X via quad 1Gpbs switch * 5Gbps via SFP cage and PHY Signed-off-by: Marcin Wojtas --- Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc = | 54 ++++ Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc = | 64 +++++ Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc = | 64 +++++ Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc = | 68 +++++ Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc = | 57 ++++ Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.i= nf | 30 ++ Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableIni= tLib.inf | 38 +++ Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.h= | 31 +++ Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableIni= tLib.h | 13 + Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.c= | 294 ++++++++++++++++++++ Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableIni= tLib.c | 89 ++++++ Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc = | 17 ++ 12 files changed, 819 insertions(+) create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/Bo= ardDescriptionLib.inf create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib= /NonDiscoverableInitLib.inf create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/Bo= ardDescriptionLib.h create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib= /NonDiscoverableInitLib.h create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/Bo= ardDescriptionLib.c create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib= /NonDiscoverableInitLib.c create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc b/Platform= /SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc new file mode 100644 index 0000000000..ad0983087d --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc @@ -0,0 +1,54 @@ +## @file=0D +# Component description file for the CN9130 Development Board (variant A)= =0D +#=0D +# Copyright (c) 2019 Marvell International Ltd.
=0D +# Copyright (c) 2021 Semihalf.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +##########################################################################= ######=0D +#=0D +# Pcd Section - list of all EDK II PCD Entries defined by this Platform=0D +#=0D +##########################################################################= ######=0D +[PcdsFixedAtBuild.common]=0D + # ComPhy=0D + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }=0D + # ComPhy0=0D + # 0: PCIE0 5 Gbps=0D + # 1: PCIE0 5 Gbps=0D + # 2: PCIE0 5 Gbps=0D + # 3: PCIE0 5 Gbps=0D + # 4: SFI 10.31 Gbps=0D + # 5: SGMII2 3.125 Gbps=0D + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SGMII2)}=0D + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }=0D +=0D + # UtmiPhy=0D + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }=0D + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1) }=0D +=0D + # MDIO=0D + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1 }=0D +=0D + # PHY=0D + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }=0D + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }=0D + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }=0D + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE=0D +=0D + # NET=0D + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }=0D + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1 }=0D + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_2500) }=0D + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_SGMII) }=0D + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF }=0D + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }=0D + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }=0D + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }=0D +=0D + # NonDiscoverableDevices=0D + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 }=0D + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }=0D diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc b/Platform= /SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc new file mode 100644 index 0000000000..c6b0cefa8d --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc @@ -0,0 +1,64 @@ +## @file=0D +# Component description file for the CN9131 Development Board (variant A)= =0D +#=0D +# Copyright (c) 2019 Marvell International Ltd.
=0D +# Copyright (c) 2021 Semihalf.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +##########################################################################= ######=0D +#=0D +# Pcd Section - list of all EDK II PCD Entries defined by this Platform=0D +#=0D +##########################################################################= ######=0D +[PcdsFixedAtBuild.common]=0D + # CP115 count=0D + gMarvellTokenSpaceGuid.PcdMaxCpCount|2=0D +=0D + # MPP=0D + gMarvellTokenSpaceGuid.PcdMppChipCount|3=0D +=0D + # CP115 #1 MPP=0D + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE=0D + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000=0D + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64=0D + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 }=0D + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3, 0x3, 0= x3, 0x0, 0x0, 0x0 }=0D + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x7, 0x7 }=0D + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x7, 0x0, 0x0, 0x0, 0x2, 0x2, 0= x2, 0x8, 0x8, 0x9 }=0D + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 }=0D + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 }=0D + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 }=0D +=0D + # ComPhy=0D + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }=0D + # ComPhy1=0D + # 0: PCIE0 5 Gbps=0D + # 1: PCIE0 5 Gbps=0D + # 2: SFI 5.15625 Gbps=0D + # 3: SATA1 5 Gbps=0D + # 4: PCIE1 5 Gbps=0D + # 5: PCIE2 5 Gbps=0D + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)}=0D + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= _15625G), $(CP_5G), $(CP_5G), $(CP_5G) }=0D +=0D + # UtmiPhy=0D + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1 }= =0D + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }=0D +=0D + # NET=0D + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 }=0D + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0x0 }=0D + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000) }=0D + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_SGMII), $(PHY_SFI) }=0D + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF }=0D + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1 }=0D + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 }=0D + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }=0D +=0D + # NonDiscoverableDevices=0D + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 }=0D + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1 }=0D + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }=0D diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc b/Platform= /SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc new file mode 100644 index 0000000000..34f9a3f2fb --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc @@ -0,0 +1,64 @@ +## @file=0D +# Component description file for the CN9132 Development Board (variant A)= =0D +#=0D +# Copyright (c) 2019 Marvell International Ltd.
=0D +# Copyright (c) 2021 Semihalf.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +##########################################################################= ######=0D +#=0D +# Pcd Section - list of all EDK II PCD Entries defined by this Platform=0D +#=0D +##########################################################################= ######=0D +[PcdsFixedAtBuild.common]=0D + # CP115 count=0D + gMarvellTokenSpaceGuid.PcdMaxCpCount|3=0D +=0D + # MPP=0D + gMarvellTokenSpaceGuid.PcdMppChipCount|4=0D +=0D + # CP115 #2 MPP=0D + gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE=0D + gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000=0D + gMarvellTokenSpaceGuid.PcdChip3MppPinCount|64=0D + gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0, 0x0 }=0D + gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF }=0D + gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0x0, 0x7, 0x7 }=0D + gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x7, 0x0, 0x0, 0xFF, 0xFF, 0= x2, 0x2, 0x8, 0x8, 0xFF }=0D + gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0xFF, 0x0, 0x0, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF }=0D + gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0= x0, 0x0, 0xFF, 0xFF, 0xFF }=0D + gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0, 0x0 }=0D +=0D + # ComPhy=0D + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 }=0D + # ComPhy2=0D + # 0: PCIE0 5 Gbps=0D + # 1: USB3_HOST0 5 Gbps=0D + # 2: SFI 5.15625 Gbps=0D + # 3: SATA1 5 Gbps=0D + # 4: PCIE1 5 Gbps=0D + # 5: PCIE2 5 Gbps=0D + gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_USB3_HOST= 0), $(CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)}=0D + gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= _15625G), $(CP_5G), $(CP_5G), $(CP_5G) }=0D +=0D + # UtmiPhy=0D + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0= x1, 0x1 }=0D + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_= HOST1) }=0D +=0D + # NET=0D + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 }=0D + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0x0, 0x0= }=0D + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000), $(PHY_SPEED_10000) }=0D + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_SGMII), $(PHY_SFI), $(PHY_SFI) }=0D + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF, 0xFF }= =0D + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 }= =0D + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 }=0D + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 }=0D +=0D + # NonDiscoverableDevices=0D + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }=0D + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1, 0x1 }=0D + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }=0D diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc b/Platform= /SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc new file mode 100644 index 0000000000..17463c09c6 --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc @@ -0,0 +1,68 @@ +## @file=0D +# Component description file for the CN9130 Development Board (variant A)= =0D +#=0D +# Copyright (c) 2019 Marvell International Ltd.
=0D +# Copyright (c) 2021 Semihalf.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +##########################################################################= ######=0D +#=0D +# Pcd Section - list of all EDK II PCD Entries defined by this Platform=0D +#=0D +##########################################################################= ######=0D +[PcdsFixedAtBuild.common]=0D + # CP115 count=0D + gMarvellTokenSpaceGuid.PcdMaxCpCount|1=0D +=0D + # MPP=0D + gMarvellTokenSpaceGuid.PcdMppChipCount|2=0D +=0D + # APN807 MPP=0D + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE=0D + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000=0D + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20=0D + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 }=0D + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x3 }=0D +=0D + # CP115 #0 MPP=0D + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE=0D + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000=0D + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64=0D + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0= x3, 0x3, 0x3, 0x3 }=0D + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0= x3, 0x0, 0x0, 0x0 }=0D + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x7, 0x7 }=0D + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x7, 0x0, 0x0, 0x0, 0x0, 0x2, 0= x2, 0x2, 0x2, 0x0 }=0D + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x8, 0x8, 0x8, 0x8, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 }=0D + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x6, 0x6, 0x2, 0x0, 0x2, 0xB, 0= xE, 0xE, 0xE, 0xE }=0D + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 }=0D +=0D + # I2C=0D + gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50 }=0D + gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }=0D + gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 }=0D + gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000=0D + gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000=0D +=0D + # SPI=0D + gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680=0D + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000=0D + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000=0D +=0D + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3=0D + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0=0D +=0D + # NonDiscoverableDevices=0D + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 }=0D +=0D + # RTC=0D + gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000=0D +=0D + # Variable store=0D + gMarvellTokenSpaceGuid.PcdSpiMemoryBase|0xEF000000=0D +[PcdsDynamicDefault.common]=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0xEF3C000= 0=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0xEF3E000= 0=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0xEF3D0= 000=0D diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc b/Platform= /SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc new file mode 100644 index 0000000000..6cb82acb13 --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc @@ -0,0 +1,57 @@ +## @file=0D +# Component description file for the CN913x CEx7 Evaluation Board=0D +#=0D +# Copyright (c) 2021 Semihalf=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +##########################################################################= ######=0D +#=0D +# Defines Section - statements that will be processed to create a Makefile= .=0D +#=0D +##########################################################################= ######=0D +[Defines]=0D + PLATFORM_NAME =3D Cn913xCEx7Eval=0D + PLATFORM_GUID =3D 4e2ffdd1-c82e-497e-936b-76217e54848a= =0D + PLATFORM_VERSION =3D 0.1=0D + DSC_SPECIFICATION =3D 0x0001001B=0D + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME)-$(ARCH)=0D + SUPPORTED_ARCHITECTURES =3D AARCH64|ARM=0D + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT=0D + SKUID_IDENTIFIER =3D DEFAULT=0D + FLASH_DEFINITION =3D Silicon/Marvell/Armada7k8k/Armada7k8k= .fdf=0D + BOARD_DXE_FV_COMPONENTS =3D Platform/SolidRun/Cn913xCEx7Eval/Cn91= 3xCEx7Eval.fdf.inc=0D + CAPSULE_ENABLE =3D TRUE=0D +=0D + #=0D + # Network definition=0D + #=0D + DEFINE NETWORK_IP6_ENABLE =3D FALSE=0D + DEFINE NETWORK_TLS_ENABLE =3D FALSE=0D + DEFINE NETWORK_HTTP_BOOT_ENABLE =3D FALSE=0D + DEFINE NETWORK_ISCSI_ENABLE =3D FALSE=0D +=0D +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc=0D +!include MdePkg/MdeLibs.dsc.inc=0D +!include Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc=0D +!include Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc=0D +!include Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc=0D +!include Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc=0D +=0D +[Components.common]=0D + Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf=0D +=0D +[Components.AARCH64]=0D + Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf=0D +=0D +[LibraryClasses.common]=0D + NonDiscoverableInitLib|Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableI= nitLib/NonDiscoverableInitLib.inf=0D + ArmadaBoardDescLib|Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/= BoardDescriptionLib.inf=0D +=0D +[PcdsFixedAtBuild.common]=0D + #Platform description=0D + gMarvellTokenSpaceGuid.PcdProductManufacturer|"SolidRun"=0D + gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN913x CEx7 Evaluation Bo= ard"=0D + gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.1"=0D diff --git a/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDesc= riptionLib.inf b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/Board= DescriptionLib.inf new file mode 100644 index 0000000000..ea13ff7ad7 --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescription= Lib.inf @@ -0,0 +1,30 @@ +## @file=0D +#=0D +# Copyright (C) 2019, Marvell International Ltd. and its affiliates
=0D +# Copyright (C) 2021, Semihalf
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001B=0D + BASE_NAME =3D Cn913xCEx7EvalBoardDescriptionLib=0D + FILE_GUID =3D 97c47d82-b9b9-4bff-9175-3f26671efea6= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D ArmadaBoardDescLib=0D +=0D +[Sources]=0D + BoardDescriptionLib.c=0D +=0D +[Packages]=0D + EmbeddedPkg/EmbeddedPkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + MdePkg/MdePkg.dec=0D + Silicon/Marvell/Marvell.dec=0D +=0D +[LibraryClasses]=0D + DebugLib=0D + IoLib=0D diff --git a/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDis= coverableInitLib.inf b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInit= Lib/NonDiscoverableInitLib.inf new file mode 100644 index 0000000000..c58ba8397a --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverab= leInitLib.inf @@ -0,0 +1,38 @@ +## @file=0D +#=0D +# Copyright (c) 2017, Linaro Ltd. All rights reserved.
=0D +# Copyright (c) 2019, Marvell International Ltd. All rights reserved.
= =0D +# Copyright (c) 2021, Semihalf. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001B=0D + BASE_NAME =3D Cn913xCExEvalNonDiscoverableInitLib=0D + FILE_GUID =3D 8e6a8766-df51-497f-9743-fc0d9170ced8= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D NonDiscoverableInitLib=0D +=0D +[Sources]=0D + NonDiscoverableInitLib.c=0D +=0D +[Packages]=0D + EmbeddedPkg/EmbeddedPkg.dec=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Silicon/Marvell/Marvell.dec=0D +=0D +[LibraryClasses]=0D + DebugLib=0D + IoLib=0D + MvGpioLib=0D +=0D +[Protocols]=0D + gEmbeddedGpioProtocolGuid=0D +=0D +[Depex]=0D + gMarvellPlatformInitCompleteProtocolGuid=0D diff --git a/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDesc= riptionLib.h b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDe= scriptionLib.h new file mode 100644 index 0000000000..6e04c9cd9e --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescription= Lib.h @@ -0,0 +1,31 @@ +/**=0D +*=0D +* Copyright (C) 2021, Semihalf.=0D +*=0D +* SPDX-License-Identifier: BSD-2-Clause-Patent=0D +*=0D +**/=0D +#ifndef BOARD_DESCRIPTION_LIB_H__=0D +#define BOARD_DESCRIPTION_LIB_H__=0D +=0D +#define IO_WIN_ALR_OFFSET(WinId) (0xF06F0000 + 0x0 + (0x10 * (WinId= )))=0D +#define IO_WIN_AHR_OFFSET(WinId) (0xF06F0000 + 0x8 + (0x10 * (WinId= )))=0D +#define IO_WIN_CR_OFFSET(WinId) (0xF06F0000 + 0xC + (0x10 * (WinId= )))=0D +#define IO_WIN_ENABLE_BIT 0x1=0D +#define IO_WIN_ADDRESS_SHIFT 16=0D +#define IO_WIN_ADDRESS_MASK 0xFFFFFFF0=0D +=0D +#define MCI0_TARGET_ID 0x0=0D +#define MCI1_TARGET_ID 0x1=0D +#define CP1_PCIE_WIN64_BASE 0x890000000=0D +#define CP1_PCIE_WIN64_SIZE 0x30000000=0D +#define CP1_PCIE_WIN64_ID 0x5=0D +#define CP2_PCIE_WIN64_BASE 0x8c0000000=0D +#define CP2_PCIE_WIN64_SIZE 0x30000000=0D +#define CP2_PCIE_WIN64_ID 0x6=0D +=0D +#define CP0_GPIO1_DATA_OUT_REG 0xF2440140=0D +#define CP0_GPIO1_OUT_EN_REG 0xF2440144=0D +#define CP0_GPIO1_PIN_MASK (1 << 7)=0D +=0D +#endif=0D diff --git a/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDis= coverableInitLib.h b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLi= b/NonDiscoverableInitLib.h new file mode 100644 index 0000000000..937b84b99d --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverab= leInitLib.h @@ -0,0 +1,13 @@ +/**=0D +*=0D +* Copyright (c) 2021, Semihalf. All rights reserved.=0D +*=0D +* SPDX-License-Identifier: BSD-2-Clause-Patent=0D +*=0D +**/=0D +#ifndef NON_DISCOVERABLE_INIT_LIB_H__=0D +#define NON_DISCOVERABLE_INIT_LIB_H__=0D +=0D +#define CN913X_CEX7_AP_SDMMC_VCCQ_PIN 26=0D +=0D +#endif=0D diff --git a/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDesc= riptionLib.c b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDe= scriptionLib.c new file mode 100644 index 0000000000..f5bb6302fe --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescription= Lib.c @@ -0,0 +1,294 @@ +/**=0D +*=0D +* Copyright (C) 2021, Semihalf.=0D +*=0D +* SPDX-License-Identifier: BSD-2-Clause-Patent=0D +*=0D +**/=0D +=0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include "BoardDescriptionLib.h"=0D +=0D +STATIC=0D +VOID=0D +ConfigureIoWindow (=0D + UINT64 WinBaseAddress,=0D + UINT64 WinSize,=0D + UINTN WinId,=0D + UINT32 WinTargetId=0D + )=0D +{=0D + UINT32 AddressHigh;=0D + UINT32 AddressLow;=0D + UINT64 MaxAddress;=0D +=0D + /* Disable IO window. */=0D + MmioWrite32 (IO_WIN_ALR_OFFSET(WinId), 0);=0D +=0D + /* Calculate the end address. */=0D + MaxAddress =3D (WinBaseAddress + WinSize - 1);=0D +=0D + AddressLow =3D (UINT32)((WinBaseAddress >> IO_WIN_ADDRESS_SHIFT) & IO_WI= N_ADDRESS_MASK);=0D + AddressLow |=3D IO_WIN_ENABLE_BIT;=0D + AddressHigh =3D (UINT32)((MaxAddress >> IO_WIN_ADDRESS_SHIFT) & IO_WIN_A= DDRESS_MASK);=0D +=0D + /* Write start address and end address for IO window. */=0D + MmioWrite32 (IO_WIN_ALR_OFFSET(WinId), AddressLow);=0D + MmioWrite32 (IO_WIN_AHR_OFFSET(WinId), AddressHigh);=0D +=0D + /* Write window target. */=0D + MmioWrite32 (IO_WIN_CR_OFFSET(WinId), WinTargetId);=0D +}=0D +=0D +//=0D +// General purpose routine for per-board initalization=0D +//=0D +EFI_STATUS=0D +ArmadaBoardInit (=0D + VOID=0D + )=0D +{=0D + /*=0D + * Due to lack of sufficient number of IO windows registers,=0D + * the CP1/CP2 PCIE configuration must be performed after the=0D + * early firmware stages. Replace the MCI 0/1 indirect=0D + * windows, which are no longer needed.=0D + */=0D + ConfigureIoWindow (=0D + CP1_PCIE_WIN64_BASE,=0D + CP1_PCIE_WIN64_SIZE,=0D + CP1_PCIE_WIN64_ID,=0D + MCI0_TARGET_ID=0D + );=0D +=0D + ConfigureIoWindow (=0D + CP2_PCIE_WIN64_BASE,=0D + CP2_PCIE_WIN64_SIZE,=0D + CP2_PCIE_WIN64_ID,=0D + MCI1_TARGET_ID=0D + );=0D +=0D + /* Enable FAN */=0D + MmioAnd32 (CP0_GPIO1_DATA_OUT_REG, ~CP0_GPIO1_PIN_MASK);=0D + MmioAnd32 (CP0_GPIO1_OUT_EN_REG, ~CP0_GPIO1_PIN_MASK);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +//=0D +// GPIO Expander=0D +//=0D +EFI_STATUS=0D +EFIAPI=0D +ArmadaBoardGpioExpanderGet (=0D + IN OUT MV_GPIO_EXPANDER **GpioExpanders,=0D + IN OUT UINTN *GpioExpanderCount=0D + )=0D +{=0D + /* No GPIO expanders on board */=0D + *GpioExpanders =3D NULL;=0D + *GpioExpanderCount =3D 0;=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +//=0D +// PCIE=0D +//=0D +STATIC=0D +MV_PCIE_CONTROLLER mPcieController[] =3D {=0D + { /* CP0 PCIE0 @0xF2600000 */=0D + .PcieDbiAddress =3D 0xF2600000,=0D + .ConfigSpaceAddress =3D 0x800000000,=0D + .HaveResetGpio =3D FALSE,=0D + .PcieResetGpio =3D { 0 },=0D + .PcieBusMin =3D 0,=0D + .PcieBusMax =3D 0xFE,=0D + .PcieIoTranslation =3D 0x80FF00000,=0D + .PcieIoWinBase =3D 0x0,=0D + .PcieIoWinSize =3D 0x10000,=0D + .PcieMmio32Translation =3D 0,=0D + .PcieMmio32WinBase =3D 0xC0000000,=0D + .PcieMmio32WinSize =3D 0x20000000,=0D + .PcieMmio64Translation =3D 0,=0D + .PcieMmio64WinBase =3D 0x810000000,=0D + .PcieMmio64WinSize =3D 0x80000000,=0D + },=0D + { /* CP1 PCIE0 @0xF4600000 */=0D + .PcieDbiAddress =3D 0xF4600000,=0D + .ConfigSpaceAddress =3D 0xE2000000,=0D + .HaveResetGpio =3D FALSE,=0D + .PcieResetGpio =3D { 0 },=0D + .PcieBusMin =3D 0,=0D + .PcieBusMax =3D 0xE,=0D + .PcieIoTranslation =3D 0xE2F00000,=0D + .PcieIoWinBase =3D 0x0,=0D + .PcieIoWinSize =3D 0x10000,=0D + .PcieMmio32Translation =3D 0,=0D + .PcieMmio32WinBase =3D 0xE3000000,=0D + .PcieMmio32WinSize =3D 0x1000000,=0D + .PcieMmio64Translation =3D 0,=0D + .PcieMmio64WinBase =3D 0x890000000,=0D + .PcieMmio64WinSize =3D 0x10000000,=0D + },=0D + { /* CP1 PCIE1 @0xF4620000 */=0D + .PcieDbiAddress =3D 0xF4620000,=0D + .ConfigSpaceAddress =3D 0xE4000000,=0D + .HaveResetGpio =3D FALSE,=0D + .PcieResetGpio =3D { 0 },=0D + .PcieBusMin =3D 0,=0D + .PcieBusMax =3D 0xE,=0D + .PcieIoTranslation =3D 0xE4F00000,=0D + .PcieIoWinBase =3D 0x0,=0D + .PcieIoWinSize =3D 0x10000,=0D + .PcieMmio32Translation =3D 0,=0D + .PcieMmio32WinBase =3D 0xE5000000,=0D + .PcieMmio32WinSize =3D 0x1000000,=0D + .PcieMmio64Translation =3D 0,=0D + .PcieMmio64WinBase =3D 0x8A0000000,=0D + .PcieMmio64WinSize =3D 0x10000000,=0D + },=0D + { /* CP1 PCIE2 @0xF4640000 */=0D + .PcieDbiAddress =3D 0xF4640000,=0D + .ConfigSpaceAddress =3D 0xE6000000,=0D + .HaveResetGpio =3D FALSE,=0D + .PcieResetGpio =3D { 0 },=0D + .PcieBusMin =3D 0,=0D + .PcieBusMax =3D 0xE,=0D + .PcieIoTranslation =3D 0xE6F00000,=0D + .PcieIoWinBase =3D 0x0,=0D + .PcieIoWinSize =3D 0x10000,=0D + .PcieMmio32Translation =3D 0,=0D + .PcieMmio32WinBase =3D 0xE7000000,=0D + .PcieMmio32WinSize =3D 0x1000000,=0D + .PcieMmio64Translation =3D 0,=0D + .PcieMmio64WinBase =3D 0x8B0000000,=0D + .PcieMmio64WinSize =3D 0x10000000,=0D + },=0D + { /* CP2 PCIE0 @0xF6600000 */=0D + .PcieDbiAddress =3D 0xF6600000,=0D + .ConfigSpaceAddress =3D 0xE9000000,=0D + .HaveResetGpio =3D FALSE,=0D + .PcieResetGpio =3D { 0 },=0D + .PcieBusMin =3D 0,=0D + .PcieBusMax =3D 0xE,=0D + .PcieIoTranslation =3D 0xE9F00000,=0D + .PcieIoWinBase =3D 0x0,=0D + .PcieIoWinSize =3D 0x10000,=0D + .PcieMmio32Translation =3D 0,=0D + .PcieMmio32WinBase =3D 0xEA000000,=0D + .PcieMmio32WinSize =3D 0x1000000,=0D + .PcieMmio64Translation =3D 0,=0D + .PcieMmio64WinBase =3D 0x8C0000000,=0D + .PcieMmio64WinSize =3D 0x10000000,=0D + },=0D + { /* CP2 PCIE1 @0xF6620000 */=0D + .PcieDbiAddress =3D 0xF6620000,=0D + .ConfigSpaceAddress =3D 0xEB000000,=0D + .HaveResetGpio =3D FALSE,=0D + .PcieResetGpio =3D { 0 },=0D + .PcieBusMin =3D 0,=0D + .PcieBusMax =3D 0xE,=0D + .PcieIoTranslation =3D 0xEBF00000,=0D + .PcieIoWinBase =3D 0x0,=0D + .PcieIoWinSize =3D 0x10000,=0D + .PcieMmio32Translation =3D 0,=0D + .PcieMmio32WinBase =3D 0xEC000000,=0D + .PcieMmio32WinSize =3D 0x1000000,=0D + .PcieMmio64Translation =3D 0,=0D + .PcieMmio64WinBase =3D 0x8D0000000,=0D + .PcieMmio64WinSize =3D 0x10000000,=0D + },=0D + { /* CP2 PCIE2 @0xF6640000 */=0D + .PcieDbiAddress =3D 0xF6640000,=0D + .ConfigSpaceAddress =3D 0xED000000,=0D + .HaveResetGpio =3D FALSE,=0D + .PcieResetGpio =3D { 0 },=0D + .PcieBusMin =3D 0,=0D + .PcieBusMax =3D 0xE,=0D + .PcieIoTranslation =3D 0xEDF00000,=0D + .PcieIoWinBase =3D 0x0,=0D + .PcieIoWinSize =3D 0x10000,=0D + .PcieMmio32Translation =3D 0,=0D + .PcieMmio32WinBase =3D 0xEE000000,=0D + .PcieMmio32WinSize =3D 0x1000000,=0D + .PcieMmio64Translation =3D 0,=0D + .PcieMmio64WinBase =3D 0x8E0000000,=0D + .PcieMmio64WinSize =3D 0x10000000,=0D + },=0D +};=0D +=0D +/**=0D + Return the number and description of PCIE controllers used on the platfo= rm.=0D +=0D + @param[in out] **PcieControllers Array containing PCIE controllers'= =0D + description.=0D + @param[in out] *PcieControllerCount Amount of used PCIE controllers.=0D +=0D + @retval EFI_SUCCESS The data were obtained successfull= y.=0D + @retval other Return error status.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +ArmadaBoardPcieControllerGet (=0D + IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers,=0D + IN OUT UINTN *PcieControllerCount=0D + )=0D +{=0D + *PcieControllers =3D mPcieController;=0D + *PcieControllerCount =3D ARRAY_SIZE (mPcieController);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +//=0D +// Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDe= scLib=0D +//=0D +STATIC=0D +MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] =3D {=0D + { /* eMMC 0xF06E0000 */=0D + 0, /* SOC will be filled by MvBoardDescDxe */=0D + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */=0D + TRUE, /* Xenon1v8Enabled */=0D + /*=0D + * Force 4-bit bus width - work-around for non=0D + * functional HS400 mode.=0D + */=0D + FALSE, /* Xenon8BitBusEnabled */=0D + FALSE, /* XenonSlowModeEnabled */=0D + 0x40, /* XenonTuningStepDivisor */=0D + EmbeddedSlot /* SlotType */=0D + },=0D + { /* SD/MMC 0xF2780000 */=0D + 0, /* SOC will be filled by MvBoardDescDxe */=0D + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */=0D + FALSE, /* Xenon1v8Enabled */=0D + FALSE, /* Xenon8BitBusEnabled */=0D + FALSE, /* XenonSlowModeEnabled */=0D + 0x19, /* XenonTuningStepDivisor */=0D + EmbeddedSlot /* SlotType */=0D + },=0D +};=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +ArmadaBoardDescSdMmcGet (=0D + OUT UINTN *SdMmcDevCount,=0D + OUT MV_BOARD_SDMMC_DESC **SdMmcDesc=0D + )=0D +{=0D + *SdMmcDesc =3D mSdMmcDescTemplate;=0D + *SdMmcDevCount =3D ARRAY_SIZE (mSdMmcDescTemplate);=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDis= coverableInitLib.c b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLi= b/NonDiscoverableInitLib.c new file mode 100644 index 0000000000..18312ac403 --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverab= leInitLib.c @@ -0,0 +1,89 @@ +/**=0D +*=0D +* Copyright (c) 2017, Linaro Ltd. All rights reserved.=0D +* Copyright (c) 2019, Marvell International Ltd. All rights reserved.=0D +* Copyright (c) 2021, Semihalf. All rights reserved.=0D +*=0D +* SPDX-License-Identifier: BSD-2-Clause-Patent=0D +*=0D +**/=0D +=0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +=0D +#include "NonDiscoverableInitLib.h"=0D +=0D +STATIC=0D +EFI_STATUS=0D +EFIAPI=0D +ConfigurePins (=0D + IN CONST MV_GPIO_PIN *VbusPin,=0D + IN UINTN PinCount,=0D + IN MV_GPIO_DRIVER_TYPE DriverType=0D + )=0D +{=0D + EMBEDDED_GPIO_MODE Mode;=0D + EMBEDDED_GPIO_PIN Gpio;=0D + EMBEDDED_GPIO *GpioProtocol;=0D + EFI_STATUS Status;=0D + UINTN Index;=0D +=0D + Status =3D MvGpioGetProtocol (DriverType, &GpioProtocol);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "%a: Unable to find GPIO protocol\n", __FUNCTION_= _));=0D + return Status;=0D + }=0D +=0D + for (Index =3D 0; Index < PinCount; Index++) {=0D + Mode =3D VbusPin->ActiveHigh ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0= ;=0D + Gpio =3D GPIO (VbusPin->ControllerId, VbusPin->PinNumber);=0D + GpioProtocol->Set (GpioProtocol, Gpio, Mode);=0D + VbusPin++;=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +STATIC CONST MV_GPIO_PIN mApSdMmcPins[] =3D {=0D + {=0D + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,=0D + MV_GPIO_CP0_CONTROLLER0,=0D + CN913X_CEX7_AP_SDMMC_VCCQ_PIN,=0D + TRUE,=0D + },=0D +};=0D +=0D +STATIC=0D +EFI_STATUS=0D +EFIAPI=0D +ApSdMmcInit (=0D + IN NON_DISCOVERABLE_DEVICE *This=0D + )=0D +{=0D + return ConfigurePins (mApSdMmcPins,=0D + ARRAY_SIZE (mApSdMmcPins),=0D + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER);=0D +}=0D +=0D +NON_DISCOVERABLE_DEVICE_INIT=0D +EFIAPI=0D +NonDiscoverableDeviceInitializerGet (=0D + IN NON_DISCOVERABLE_DEVICE_TYPE Type,=0D + IN UINTN Index=0D + )=0D +{=0D + if (Type =3D=3D NonDiscoverableDeviceTypeSdhci && Index =3D=3D 0) {=0D + return ApSdMmcInit;=0D + }=0D +=0D + return NULL;=0D +}=0D diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc b/Plat= form/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc new file mode 100644 index 0000000000..6cf2be0b1e --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc @@ -0,0 +1,17 @@ +#=0D +# Copyright (c) 2021 Semihalf=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +=0D +# Per-board additional content of the DXE phase firmware volume=0D +=0D + INF Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf=0D +=0D + # DTB=0D + INF RuleOverride =3D DTB Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATF= ORM_NAME).inf=0D +=0D + # ACPI support=0D +!if $(ARCH) =3D=3D AARCH64=0D + INF RuleOverride =3D ACPITABLE Silicon/Marvell/OcteonTx/AcpiTables/T91/$= (PLATFORM_NAME).inf=0D +!endif=0D --=20 2.29.0