From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lj1-f181.google.com (mail-lj1-f181.google.com [209.85.208.181]) by mx.groups.io with SMTP id smtpd.web11.2139.1628365059673636388 for ; Sat, 07 Aug 2021 12:37:40 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=UTTfDCli; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.208.181, mailfrom: mw@semihalf.com) Received: by mail-lj1-f181.google.com with SMTP id n6so3997506ljp.9 for ; Sat, 07 Aug 2021 12:37:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S7IKZosYxqnvRm+T9UqqoY/XpJXPb6nVEXKaq+kVAH4=; b=UTTfDClixA3DQFFy5HoT7VKhnPL9eZ715wPZW4wCiP12xHA2LO90OfH9jzNGOArxBI JiCT6vI2uTKLSXDGOfsRr9IlGFLgUkIiOVhfE/F3Df2Td6+nG6l9XvUWkib0UtW+U/Zd MuoT0Kxzjy5ck7HFyiAGgCJavQDlBydN0/9OS5RsD0pJCYPUROS+/nnznIl1rIaDIE8p UBg2Z4MNagi4XmhoQmlDG9cpCJOUeOQynqd6fZ924Vixd6m01m+MuuCvL2OSPBKAKb27 B2Sxmp3BgnfYz8PBVj2RDZwgWJtxertEpmV/3miHUJKRO0xIHibI0A0HCbkSJkAXqQ9Y MDKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S7IKZosYxqnvRm+T9UqqoY/XpJXPb6nVEXKaq+kVAH4=; b=Vlxh9n08fQ+89iGzDhXNaiTynL3WdtWncUOUs0jlbri4+ztwUDTNf5sBAgdFr4T2gC Yg3gynqxXKs6iamExMzKqL/S1UvslgFV/T/G7VK3tSvghlQpPq53LL4jtjskMUdc5vBK cnaF5YEPjMT30CDO/ZcwcqUPJMuqeQVYycEvx4Mrpk1JxCgPay2LTfMSSZuytfPqNIuR OStQHReVruxsrCUNSRxT+7jLVgT7WEr+MVd6A8G6D6xY9oEYPfUFZaqN44tp0pY/StGE Tg6CadYjJ5v3wMBWoz2T2D2RH3hCGtn4I9+zwT56PiJNw4aslgT028W2SADW55PF2nus gzbw== X-Gm-Message-State: AOAM532nDqOiTDIr0Jz8UHAPNsVWNfubS4dA8um9F2XkllVR+iYjQGSI /sqUbXWu+PcfekBzhNzoAxbhX9KxRpsFofhn X-Google-Smtp-Source: ABdhPJxnB+tY0QnuxvrM+Yw/SDhrGPoXUNSWqAR6gGpSmaP26E184lqNH1H9tYirYKOpL2Awqjc5JA== X-Received: by 2002:a2e:8113:: with SMTP id d19mr10877103ljg.68.1628365057928; Sat, 07 Aug 2021 12:37:37 -0700 (PDT) Return-Path: Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id bq33sm103635lfb.88.2021.08.07.12.37.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Aug 2021 12:37:37 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, alon.rotman@solid-run.com, Marcin Wojtas Subject: [edk2-non-osi PATCH] SolidRun/Cn913xCEx7Eval: Add DeviceTree Date: Sat, 7 Aug 2021 21:36:41 +0200 Message-Id: <20210807193641.3355697-5-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210807193641.3355697-1-mw@semihalf.com> References: <20210807193641.3355697-1-mw@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable This patch introduces the top device tree for the CN913x CEx7 Evaluation Board, based on the sources which are common for the Cn913x SoCs. Also an .inf file is added to allow its compilation. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn913xCEx7Eval.inf | 22 + Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts | 435 +++++++++= +++++++++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-cex7.dts | 180 ++++++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-cex7.dts | 183 ++++++++ 4 files changed, 820 insertions(+) create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn913xCEx7Eval.= inf create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-cex7.dts create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-cex7.dts diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn913xCEx7Eval.inf b/S= ilicon/Marvell/OcteonTx/DeviceTree/T91/Cn913xCEx7Eval.inf new file mode 100644 index 0000000..3c99227 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn913xCEx7Eval.inf @@ -0,0 +1,22 @@ +## @file=0D +#=0D +# Device tree description of the Marvell CN9130-DB-A platform=0D +#=0D +# Copyright (c) 2021, Semihalf. All rights reserved.=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001B=0D + BASE_NAME =3D Cn913xCEx7EvalDeviceTree=0D + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid=0D + MODULE_TYPE =3D USER_DEFINED=0D + VERSION_STRING =3D 1.0=0D +=0D +[Sources]=0D + cn9132-cex7.dts=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts b/Sili= con/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts new file mode 100644 index 0000000..50e6d69 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright SolidRun Ltd.=0D + *=0D + * Device tree for the CN9130 based COM Express type 7 board.=0D + */=0D +=0D +#define GPIO_ACTIVE_HIGH 0=0D +#define GPIO_ACTIVE_LOW 1=0D +=0D +#include "cn9130.dtsi"=0D +=0D +/ {=0D + model =3D "SolidRun CN9130 based COM Express type 7";=0D +=0D + chosen {=0D + stdout-path =3D "serial0:115200n8";=0D + };=0D +=0D + aliases {=0D + gpio1 =3D &cp0_gpio1;=0D + gpio2 =3D &cp0_gpio2;=0D + i2c0 =3D &cp0_i2c0;=0D + ethernet0 =3D &cp0_eth0; // SFP+ Port=0D + ethernet1 =3D &cp0_eth1; // RGMII=0D + ethernet2 =3D &cp0_eth2; // HS-SGMII=0D + spi1 =3D &cp0_spi0;=0D + spi2 =3D &cp0_spi1;=0D + };=0D +=0D + memory@00000000 {=0D + device_type =3D "memory";=0D + reg =3D <0x0 0x0 0x0 0x80000000>;=0D + };=0D + v_3_3: regulator-3-3v {=0D + compatible =3D "regulator-fixed";=0D + regulator-name =3D "v_3_3";=0D + regulator-min-microvolt =3D <3300000>;=0D + regulator-max-microvolt =3D <3300000>;=0D + regulator-always-on;=0D + status =3D "okay";=0D + };=0D + ap0_reg_sd_vccq: ap0_sd_vccq@0 {=0D + compatible =3D "regulator-gpio";=0D + regulator-name =3D "ap0_sd_vccq";=0D + regulator-min-microvolt =3D <1800000>;=0D + regulator-max-microvolt =3D <1800000>;=0D + states =3D <1800000 0x1 3300000 0x0>;=0D + };=0D +=0D + cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {=0D + compatible =3D "regulator-fixed";=0D + regulator-name =3D "cp0-xhci0-vbus";=0D + regulator-min-microvolt =3D <5000000>;=0D + regulator-max-microvolt =3D <5000000>;=0D + enable-active-high;=0D + };=0D +=0D + cp0_usb3_0_phy0: cp0_usb3_phy@0 {=0D + compatible =3D "usb-nop-xceiv";=0D + vcc-supply =3D <&cp0_reg_usb3_vbus0>;=0D + };=0D +=0D + cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {=0D + compatible =3D "regulator-fixed";=0D + regulator-name =3D "cp0-xhci1-vbus";=0D + regulator-min-microvolt =3D <5000000>;=0D + regulator-max-microvolt =3D <5000000>;=0D + enable-active-high;=0D + };=0D +=0D + cp0_usb3_0_phy1: cp0_usb3_phy@1 {=0D + compatible =3D "usb-nop-xceiv";=0D + vcc-supply =3D <&cp0_reg_usb3_vbus1>;=0D + };=0D +=0D + cp0_reg_sd_vccq: cp0_sd_vccq@0 {=0D + compatible =3D "regulator-gpio";=0D + regulator-name =3D "cp0_sd_vccq";=0D + regulator-min-microvolt =3D <1800000>;=0D + regulator-max-microvolt =3D <3300000>;=0D + states =3D <1800000 0x1=0D + 3300000 0x0>;=0D + };=0D +=0D + cp0_reg_sd_vcc: cp0_sd_vcc@0 {=0D + compatible =3D "regulator-fixed";=0D + regulator-name =3D "cp0_sd_vcc";=0D + regulator-min-microvolt =3D <3300000>;=0D + regulator-max-microvolt =3D <3300000>;=0D + enable-active-high;=0D + regulator-always-on;=0D + };=0D +=0D + cp0_sfp_eth0: sfp-eth@0 {=0D + compatible =3D "sff,sfp";=0D + i2c-bus =3D <&cp0_sfp_i2c>;=0D + mod-def0-gpio =3D <&cp0_gpio1 24 GPIO_ACTIVE_LOW>;=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_sfp_present_pins>;=0D + };=0D +};=0D +=0D +&uart0 {=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_uart2 {=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_uart2_pins>;=0D + status =3D "okay";=0D +};=0D +=0D +/* on-board eMMC */=0D +&ap_sdhci0 {=0D + pinctrl-names =3D "default";=0D + bus-width =3D <8>;=0D + vqmmc-supply =3D <&ap0_reg_sd_vccq>;=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_crypto {=0D + status =3D "disabled";=0D +};=0D +=0D +&cp0_ethernet {=0D + status =3D "okay";=0D +};=0D +=0D +/* SFP+ 10GE */=0D +&cp0_eth0 {=0D + status =3D "okay";=0D + phy-mode =3D "10gbase-kr";=0D + phys =3D <&cp0_comphy4 0>;=0D + managed =3D "in-band-status";=0D + sfp =3D <&cp0_sfp_eth0>;=0D +};=0D +=0D +/* RGMII 1GE */=0D +&cp0_eth1 {=0D + status =3D "okay";=0D + phy =3D <&phy0>;=0D + phy-mode =3D "rgmii-id";=0D +};=0D +=0D +&cp0_gpio1 {=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_gpio2 {=0D + status =3D "okay";=0D +};=0D +=0D +/* Switch uplink */=0D +&cp0_eth2 {=0D + status =3D "okay";=0D + phy-mode =3D "2500base-x";=0D + phys =3D <&cp0_comphy5 2>;=0D +=0D + fixed-link {=0D + speed =3D <2500>;=0D + full-duplex;=0D + };=0D +};=0D +=0D +=0D +/* EEPROM */=0D +&cp0_i2c0 {=0D + status =3D "okay";=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_i2c0_pins>;=0D + clock-frequency =3D <100000>;=0D + /* EEPROM */=0D + eeprom0: eeprom@50 {=0D + compatible =3D "atmel,24c64";=0D + reg =3D <0x50>;=0D + pagesize =3D <0x20>;=0D + };=0D +};=0D +=0D +/* I2C Master */=0D +&cp0_i2c1 {=0D + status =3D "okay";=0D + clock-frequency =3D <100000>;=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_i2c1_pins>;=0D +=0D + i2c-switch@77 {=0D + compatible =3D "nxp,pca9547";=0D + reg =3D <0x77>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + clk_gen_i2c: i2c@0 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + reg =3D <0>;=0D + /*connected to clk generator*/=0D + };=0D + led_i2c: i2c@1 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + reg =3D <1>;=0D + /* i2c_led connected to gpio expander on carrier a= ccording to com-ex type7 */=0D + };=0D + cp0_sfp_i2c: i2c@2 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + reg =3D <2>;=0D + /*connected to sfp cp0_eth0*/=0D + };=0D +=0D + smbus: i2c@3 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + reg =3D <3>;=0D + /* smbus connected to com-ex type7 connector */=0D + current_mon@40 {=0D + compatible =3D "ti,ina220";=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + reg =3D <0x40>;=0D + };=0D + };=0D +=0D + therm_i2c: i2c@4 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + reg =3D <4>;=0D +=0D + fan-control-emc2301@2f {=0D + compatible =3D "smsc,emc2305";=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + reg =3D <0x2f>;=0D + fan@0 {=0D + reg =3D <0>;=0D + pwm-enable =3D <0>;=0D + fan-div =3D <4>;=0D + };=0D + };=0D + };=0D + };=0D +};=0D +&cp0_mdio {=0D + status =3D "okay";=0D + pinctrl-0 =3D <&cp0_ge_mdio_pins>;=0D + phy0: ethernet-phy@0 {=0D + marvell,reg-init =3D <3 16 0 0x1a4a>;=0D + reg =3D <0>;=0D + };=0D +=0D + switch0: switch0@4 {=0D + compatible =3D "marvell,mv88e6085";=0D + reg =3D <4>;=0D + pinctrl-names =3D "default";=0D +=0D + ports {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + port@1 {=0D + reg =3D <1>;=0D + label =3D "lan2";=0D + phy-handle =3D <&switch0phy0>;=0D + };=0D +=0D + port@2 {=0D + reg =3D <2>;=0D + label =3D "lan1";=0D + phy-handle =3D <&switch0phy1>;=0D + };=0D +=0D + port@3 {=0D + reg =3D <3>;=0D + label =3D "lan4";=0D + phy-handle =3D <&switch0phy2>;=0D + };=0D +=0D + port@4 {=0D + reg =3D <4>;=0D + label =3D "lan3";=0D + phy-handle =3D <&switch0phy3>;=0D + };=0D +=0D + port@5 {=0D + reg =3D <5>;=0D + label =3D "cpu";=0D + ethernet =3D <&cp0_eth2>;=0D + };=0D + };=0D +=0D + mdio {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D +=0D + switch0phy0: switch0phy0@11 {=0D + reg =3D <0x11>;=0D + };=0D +=0D + switch0phy1: switch0phy1@12 {=0D + reg =3D <0x12>;=0D + };=0D +=0D + switch0phy2: switch0phy2@13 {=0D + reg =3D <0x13>;=0D + };=0D +=0D + switch0phy3: switch0phy3@14 {=0D + reg =3D <0x14>;=0D + };=0D + };=0D + };=0D +};=0D +=0D +/* PCIE X4 Slot */=0D +&cp0_pcie0 {=0D + status =3D "okay";=0D + num-lanes =3D <4>;=0D + num-viewport =3D <8>;=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp0_comphy0 0=0D + &cp0_comphy1 0=0D + &cp0_comphy2 0=0D + &cp0_comphy3 0>;=0D +};=0D +=0D +/* PCIE X1 Slot */=0D +/*=0D +*&cp0_pcie2 {=0D +* status =3D "okay";=0D +* phys =3D <&cp0_comphy5 2>;=0D +* num-lanes =3D <1>;=0D +*};=0D +*/=0D +=0D +/* SD Card */=0D +&cp0_sdhci0 {=0D + status =3D "okay";=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_sdhci_pins=0D + &cp0_sdhci_cd_pins>;=0D + bus-width =3D <4>;=0D + cd-gpios =3D <&cp0_gpio2 24 GPIO_ACTIVE_LOW>;=0D + no-1-8-v;=0D + vqmmc-supply =3D <&v_3_3>;=0D + vmmc-supply =3D <&v_3_3>;=0D +};=0D +=0D +&cp0_spi1 {=0D + status =3D "okay";=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_spi1_pins=0D + &cp0_spi1_cs1_pins>;=0D + reg =3D <0x700680 0x50>;=0D + spi-flash@0 {=0D + #address-cells =3D <0x1>;=0D + #size-cells =3D <0x1>;=0D + compatible =3D "jedec,spi-nor";=0D + reg =3D <0x0>;=0D + spi-max-frequency =3D <10000000>;=0D + };=0D + spi-flash@1 {=0D + #address-cells =3D <0x1>;=0D + #size-cells =3D <0x1>;=0D + compatible =3D "jedec,spi-nor";=0D + reg =3D <0x1>;=0D + /* On carrier MUX does not allow higher frequencies */=0D + spi-max-frequency =3D <10000000>;=0D + };=0D +};=0D +=0D +&cp0_syscon0 {=0D + cp0_pinctrl: pinctrl {=0D + compatible =3D "marvell,cp115-standalone-pinctrl";=0D +=0D + cp0_ge_mdio_pins: ge-mdio-pins {=0D + marvell,pins =3D "mpp40", "mpp41";=0D + marvell,function =3D "ge";=0D + };=0D +=0D + cp0_i2c0_pins: cp0-i2c-pins-0 {=0D + marvell,pins =3D "mpp37", "mpp38";=0D + marvell,function =3D "i2c0";=0D + };=0D + cp0_i2c1_pins: cp0-i2c-pins-1 {=0D + marvell,pins =3D "mpp35", "mpp36";=0D + marvell,function =3D "i2c1";=0D + };=0D + cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {=0D + marvell,pins =3D "mpp0", "mpp1", "mpp2",=0D + "mpp3", "mpp4", "mpp5",=0D + "mpp6", "mpp7", "mpp8",=0D + "mpp9", "mpp10", "mpp11";=0D + marvell,function =3D "ge0";=0D + };=0D + cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {=0D + marvell,pins =3D "mpp55";=0D + marvell,function =3D "sdio";=0D + };=0D + cp0_sdhci_pins: cp0-sdhi-pins-0 {=0D + marvell,pins =3D "mpp56", "mpp57", "mpp58",= =0D + "mpp59", "mpp60", "mpp61";=0D + marvell,function =3D "sdio";=0D + };=0D + cp0_spi1_pins: cp0-spi-pins-1 {=0D + marvell,pins =3D "mpp13", "mpp14", "mpp15", "mpp16= ";=0D + marvell,function =3D "spi1";=0D + };=0D + cp0_spi1_cs1_pins: cp0-spi-cs1-pins-1 {=0D + marvell,pins =3D "mpp12";=0D + marvell,function =3D "spi1";=0D + };=0D +=0D + cp0_sfp_present_pins: sfp-present-pins {=0D + marvell,pins =3D "mpp24";=0D + marvell,function =3D "gpio";=0D + };=0D + cp0_uart2_pins: uart22-pins {=0D + marvell,pins =3D "mpp50", "mpp51";=0D + marvell,function =3D "uart2";=0D + };=0D +=0D + };=0D +};=0D +=0D +&cp0_usb3_0 {=0D + status =3D "okay";=0D + usb-phy =3D <&cp0_usb3_0_phy0>;=0D + phy-names =3D "usb";=0D +};=0D +=0D +&cp0_usb3_1 {=0D + status =3D "okay";=0D + usb-phy =3D <&cp0_usb3_0_phy1>;=0D + phy-names =3D "usb";=0D +};=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-cex7.dts b/Sili= con/Marvell/OcteonTx/DeviceTree/T91/cn9131-cex7.dts new file mode 100644 index 0000000..7c33ff9 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-cex7.dts @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright SolidRun Ltd.=0D + *=0D + * Device tree for the CN9131 COM Express Type 7 board.=0D + */=0D +=0D +#include "cn9130-cex7.dts"=0D +=0D +/ {=0D + model =3D "SolidRun CN9131 based COM Express type 7";=0D + compatible =3D "marvell,cn9131", "marvell,cn9130",=0D + "marvell,armada-ap807-quad", "marvell,armada-ap807";= =0D +=0D + aliases {=0D + gpio3 =3D &cp1_gpio1;=0D + gpio4 =3D &cp1_gpio2;=0D + ethernet3 =3D &cp1_eth0;=0D + };=0D + cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {=0D + compatible =3D "regulator-fixed";=0D + regulator-name =3D "cp1-xhci0-vbus";=0D + regulator-min-microvolt =3D <5000000>;=0D + regulator-max-microvolt =3D <5000000>;=0D + enable-active-high;=0D + };=0D + cp1_usb3_0_phy0: cp1_usb3_phy0 {=0D + compatible =3D "usb-nop-xceiv";=0D + vcc-supply =3D <&cp1_reg_usb3_vbus0>;=0D + };=0D + cp1_reg_usb3_vbus1: cp1_usb3_vbus@1 {=0D + compatible =3D "regulator-fixed";=0D + regulator-name =3D "cp1-xhci1-vbus";=0D + regulator-min-microvolt =3D <5000000>;=0D + regulator-max-microvolt =3D <5000000>;=0D + enable-active-high;=0D + };=0D + cp1_usb3_0_phy1: cp1_usb3_phy@1 {=0D + compatible =3D "usb-nop-xceiv";=0D + vcc-supply =3D <&cp1_reg_usb3_vbus1>;=0D + };=0D + cp1_sfp_eth0: sfp_eth0{=0D + compatible =3D "sff,sfp";=0D + i2c-bus =3D <&cp1_i2c1>;=0D + mod-def0-gpio =3D <&cp1_gpio2 18 GPIO_ACTIVE_LOW>;=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp1_sfp_present_pins>;=0D + status =3D "okay";=0D + };=0D +};=0D +=0D +/* Instantiate the first slave CP115 */=0D +=0D +#define CP11X_NAME cp1=0D +#define CP11X_BASE f4000000=0D +#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x2000000))=0D +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000=0D +#define CP11X_PCIE0_BASE f4600000=0D +#define CP11X_PCIE1_BASE f4620000=0D +#define CP11X_PCIE2_BASE f4640000=0D +=0D +#include "armada-cp115.dtsi"=0D +=0D +#undef CP11X_NAME=0D +#undef CP11X_BASE=0D +#undef CP11X_PCIEx_MEM_BASE=0D +#undef CP11X_PCIEx_MEM_SIZE=0D +#undef CP11X_PCIE0_BASE=0D +#undef CP11X_PCIE1_BASE=0D +#undef CP11X_PCIE2_BASE=0D +=0D +&cp1_crypto {=0D + status =3D "disabled";=0D +};=0D +=0D +&cp1_ethernet {=0D + status =3D "okay";=0D +};=0D +=0D +/* 5GE PHY0 */=0D +&cp1_eth0 {=0D + status =3D "okay";=0D + phy-mode =3D "5gbase-r";=0D + phys =3D <&cp1_comphy2 0>;=0D + phy =3D <&phy1>;=0D + sfp =3D <&cp1_sfp_eth0>;=0D +};=0D +=0D +&cp1_gpio1 {=0D + status =3D "okay";=0D +};=0D +=0D +&cp1_gpio2 {=0D + status =3D "okay";=0D +};=0D +=0D +&cp1_xmdio {=0D + status =3D "okay";=0D + pinctrl-0 =3D <&cp1_xmdio_pins>;=0D + phy1: ethernet-phy@0 {=0D + compatible =3D "ethernet-phy-ieee802.3-c45";=0D + reg =3D <0>;=0D + };=0D +};=0D +=0D +&cp1_i2c1 {=0D + status =3D "okay";=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp1_i2c1_pins>;=0D + clock-frequency =3D <100000>;=0D +};=0D +=0D +/* PCIE X2 NVME */=0D +&cp1_pcie0 {=0D + pinctrl-names =3D "default";=0D + num-lanes =3D <2>;=0D + num-viewport =3D <8>;=0D + status =3D "okay";=0D + phys =3D <&cp1_comphy0 0=0D + &cp1_comphy1 0>;=0D +};=0D +=0D +/* SATA 1 */=0D +&cp1_sata0 {=0D + status =3D "okay";=0D + sata-port@1 {=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp1_comphy3 1>;=0D + };=0D +};=0D +=0D +/* PCIE X1 WIFI0 */=0D +&cp1_pcie1 {=0D + pinctrl-names =3D "default";=0D + num-lanes =3D <1>;=0D + num-viewport =3D <8>;=0D + status =3D "okay";=0D + phys =3D <&cp1_comphy4 1>;=0D +};=0D +=0D +/* PCIE X1 WIFI1 */=0D +&cp1_pcie2 {=0D + pinctrl-names =3D "default";=0D + num-lanes =3D <1>;=0D + num-viewport =3D <8>;=0D + status =3D "okay";=0D + phys =3D <&cp1_comphy5 2>;=0D +};=0D +=0D +/* PIN Definition */=0D +=0D +&cp1_syscon0 {=0D + cp1_pinctrl: pinctrl {=0D + compatible =3D "marvell,cp115-standalone-pinctrl";=0D +=0D + cp1_i2c1_pins: cp1-i2c-pins-1 {=0D + marvell,pins =3D "mpp35", "mpp36";=0D + marvell,function =3D "i2c1";=0D + };=0D + cp1_xmdio_pins: cp1_xmdio_pins-0 {=0D + marvell,pins =3D "mpp37", "mpp38";=0D + marvell,function =3D "xg";=0D + };=0D + cp1_sfp_present_pins: cp1_sfp_present_pins-0 {=0D + marvell,pins =3D "mpp50";=0D + marvell,function =3D "gpio";=0D + };=0D + };=0D +};=0D +=0D +&cp1_usb3_0 {=0D + status =3D "okay";=0D + sb-phy =3D <&cp1_usb3_0_phy0>;=0D + phy-names =3D "usb";=0D +};=0D +&cp1_usb3_1 {=0D + status =3D "okay";=0D + usb-phy =3D <&cp1_usb3_0_phy1>;=0D + phy-names =3D "usb";=0D +};=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-cex7.dts b/Sili= con/Marvell/OcteonTx/DeviceTree/T91/cn9132-cex7.dts new file mode 100644 index 0000000..aa4136c --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-cex7.dts @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright SolidRun Ltd.=0D + *=0D + * Device tree for the CN9132 based COM Express type 7 board"=0D + */=0D +=0D +#include "cn9131-cex7.dts"=0D +=0D +/ {=0D + model =3D "SolidRun CN9132 based COM Express type 7";=0D + compatible =3D "marvell,cn9132", "marvell,cn9131", "marvel= l,cn9130",=0D + "marvell,armada-ap807-quad", "marvell,armada-ap807= ";=0D +=0D + aliases {=0D + gpio5 =3D &cp2_gpio1;=0D + gpio6 =3D &cp2_gpio2;=0D + ethernet5 =3D &cp2_eth0;=0D + };=0D +=0D + cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {=0D + compatible =3D "regulator-fixed";=0D + regulator-name =3D "cp2-xhci0-vbus";=0D + regulator-min-microvolt =3D <5000000>;=0D + regulator-max-microvolt =3D <5000000>;=0D + enable-active-high;=0D + };=0D +=0D + cp2_usb3_0_phy0: cp2_usb3_phy0 {=0D + compatible =3D "usb-nop-xceiv";=0D + vcc-supply =3D <&cp2_reg_usb3_vbus0>;=0D + };=0D +=0D + cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {=0D + compatible =3D "regulator-fixed";=0D + regulator-name =3D "cp2-xhci1-vbus";=0D + regulator-min-microvolt =3D <5000000>;=0D + regulator-max-microvolt =3D <5000000>;=0D + enable-active-high;=0D + };=0D +=0D + cp2_usb3_0_phy1: cp2_usb3_phy1 {=0D + compatible =3D "usb-nop-xceiv";=0D + vcc-supply =3D <&cp2_reg_usb3_vbus1>;=0D + };=0D +=0D + cp2_sfp_eth0: sfp-eth0 {=0D + compatible =3D "sff,sfp";=0D + i2c-bus =3D <&cp2_i2c1>;=0D + mod-def0-gpio =3D <&cp2_gpio2 18 GPIO_ACTIVE_LOW>;=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp2_sfp_pins>;=0D + status =3D "okay";=0D + };=0D +};=0D +=0D +/* Instantiate the second slave CP115 */=0D +=0D +#define CP11X_NAME cp2=0D +#define CP11X_BASE f6000000=0D +#define CP11X_PCIEx_MEM_BASE(iface) (0xe9000000 + (iface * 0x2000000))=0D +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000=0D +#define CP11X_PCIE0_BASE f6600000=0D +#define CP11X_PCIE1_BASE f6620000=0D +#define CP11X_PCIE2_BASE f6640000=0D +=0D +#include "armada-cp115.dtsi"=0D +=0D +#undef CP11X_NAME=0D +#undef CP11X_BASE=0D +#undef CP11X_PCIEx_MEM_BASE=0D +#undef CP11X_PCIEx_MEM_SIZE=0D +#undef CP11X_PCIE0_BASE=0D +#undef CP11X_PCIE1_BASE=0D +#undef CP11X_PCIE2_BASE=0D +=0D +&cp2_crypto {=0D + status =3D "disabled";=0D +};=0D +=0D +&cp2_ethernet {=0D + status =3D "okay";=0D +};=0D +=0D +/* 10GE Port */=0D +&cp2_eth0 {=0D + status =3D "okay";=0D + phy-mode =3D "5gbase-r";=0D + phys =3D <&cp2_comphy2 0>;=0D + phy =3D <&phy2>;=0D + sfp =3D <&cp2_sfp_eth0>;=0D +};=0D +=0D +&cp2_gpio1 {=0D + status =3D "okay";=0D +};=0D +=0D +&cp2_gpio2 {=0D + status =3D "okay";=0D +};=0D +=0D +&cp2_i2c1 {=0D + status =3D "okay";=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp2_i2c1_pins>;=0D + clock-frequency =3D <100000>;=0D +};=0D +=0D +&cp2_xmdio {=0D + status =3D "okay";=0D + pinctrl-0 =3D <&cp2_xmdio_pins>;=0D + phy2: ethernet-phy@0 {=0D + compatible =3D "ethernet-phy-ieee802.3-c45";=0D + reg =3D <0>;=0D + };=0D +};=0D +=0D +=0D +/* PCIE0 X1 */=0D +&cp2_pcie0 {=0D + status =3D "okay";=0D + num-lanes =3D <1>;=0D + num-viewport =3D <8>;=0D + phys =3D <&cp2_comphy0 0>;=0D +};=0D +=0D +/* PCIE1 X1 */=0D +&cp2_pcie1 {=0D + status =3D "okay";=0D + num-lanes =3D <1>;=0D + num-viewport =3D <8>;=0D + phys =3D <&cp2_comphy4 1>;=0D +};=0D +=0D +/* PCIE2 X1 */=0D +&cp2_pcie2 {=0D + status =3D "okay";=0D + num-lanes =3D <1>;=0D + num-viewport =3D <8>;=0D + phys =3D <&cp2_comphy5 2>;=0D +};=0D +=0D +/* SATA 1 */=0D +&cp2_sata0 {=0D + status =3D "okay";=0D + sata-port@0 {=0D + phys =3D <&cp2_comphy3 1>;=0D + };=0D +};=0D +=0D +&cp2_syscon0 {=0D + cp2_pinctrl: pinctrl {=0D + compatible =3D "marvell,cp115-standalone-pinctrl";=0D +=0D + cp2_xmdio_pins: cp2-xmdio-pins-0 {=0D + marvell,pins =3D "mpp37", "mpp38";=0D + marvell,function =3D "xg";=0D + };=0D +=0D + cp2_i2c1_pins: cp2-i2c-pins-1 {=0D + marvell,pins =3D "mpp35", "mpp36";=0D + marvell,function =3D "i2c1";=0D + };=0D + cp2_sfp_pins: sfp-pins {=0D + marvell,pins =3D "mpp50";=0D + marvell,function =3D "gpio";=0D + };=0D + };=0D +};=0D +=0D +&cp2_usb3_0 {=0D + status =3D "okay";=0D + usb-phy =3D <&cp2_usb3_0_phy0>;=0D + phy-names =3D "usb";=0D +};=0D +=0D +/* USB3 */=0D +&cp2_usb3_1 {=0D + status =3D "okay";=0D + usb-phy =3D <&cp2_usb3_0_phy1>;=0D + phy-names =3D "usb";=0D + phys =3D <&cp2_comphy1 0>;=0D +};=0D --=20 2.29.0