From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) by mx.groups.io with SMTP id smtpd.web11.24371.1628522400519649182 for ; Mon, 09 Aug 2021 08:20:01 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=JOCXkwyJ; spf=pass (domain: linaro.org, ip: 209.85.221.48, mailfrom: etienne.carriere@linaro.org) Received: by mail-wr1-f48.google.com with SMTP id z4so21977119wrv.11 for ; Mon, 09 Aug 2021 08:20:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=bML/B0gES6UIT8mIHwrXDCsU559Pb/FIOj/7ExeO9nU=; b=JOCXkwyJkjvDNdGM6OXTi/Xt9EgyRO9DFxZXCpuP/XtyxecLGtqQ86oDto0HEQw5zP wbQ8+oWEXNwTM282TTHdmkmAhLrXUnWW736q498Tb7o8KebFarMQrcXTgIq6f7CraYjq i+/hGLgb/r2TVLlTkrsit5R2kFttWWimZsdmK4Rum+e1H4jy+bQ10vALIPZ+4begMeVn 7a1E5o8RTwrfH+9IFb8hFLLncpC8Eb4wyy8oeB0pSljZTp4CCewGPlI2lmUQ4XvzsANg pbQPQ5+o1RKzFYstljW0Bv+nhgIk9Rft8erA7UdYqAuB6xw2Jeg0z9K1qdWs4h5wg7Yb t6hQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=bML/B0gES6UIT8mIHwrXDCsU559Pb/FIOj/7ExeO9nU=; b=HPCU4CUBjCJOlgbn4ALJXRezWKihmqzLJ3QKVyQ4t+YBLl6K9xX6U6djsaxj/otFfi 4iCDomla+h1F572nzEfObHPN2bZFDgF7XN+fu/99k63QgSp9cZALWZxg1Tugthw7dcda la+EFUhRLAhGDsQyBH53dhXzxzZM+q7lkPivhzCcn9nTNcAeR4J3n1EXYNbX6POy5dtU Klem9+OaTNN9eTjvkvFXx7focQPLSvAifeYejDpNFR8M4g5BQWE/UFGh2MlmpudEmCWx VzkDvYddBiNnFqkWkA17gr8NVufl5h777ZbAv8/aO2P4xS7BVKgh2uvh5vGEPRgOlCEb LsiQ== X-Gm-Message-State: AOAM530JY8QtyFCdcsy6fZJJbCkmufgX69dJmkhykzqkpklne93gZ1+V WD2qt1IWIZGvyMZPiE4PxBsZw1pqQ2R5cg== X-Google-Smtp-Source: ABdhPJxvXD8v/iPjXE757z8lKl3DXStf6IWiqZBrRW+ZcQk0R1BMEECGwwJ0MOp6y14RNN0KiffzvA== X-Received: by 2002:adf:c549:: with SMTP id s9mr25742831wrf.344.1628522398746; Mon, 09 Aug 2021 08:19:58 -0700 (PDT) Return-Path: Received: from lmecxl0524.lme.st.com ([2a04:cec0:1189:835c:f5e6:d24:9eea:1973]) by smtp.gmail.com with ESMTPSA id j14sm20449971wru.58.2021.08.09.08.19.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Aug 2021 08:19:58 -0700 (PDT) From: "Etienne Carriere" To: devel@edk2.groups.io Cc: Achin Gupta , Ard Biesheuvel , Jiewen Yao , Leif Lindholm , Sami Mujawar , Sughosh Ganu , Liming Gao , Etienne Carriere Subject: [PATCH v5 1/5] ArmPkg/IndustryStandard: 32b/64b agnostic FF-A, Mm SVC and Std SMC IDs Date: Mon, 9 Aug 2021 17:19:42 +0200 Message-Id: <20210809151946.27600-1-etienne.carriere@linaro.org> X-Mailer: git-send-email 2.17.1 Defines ARM_SVC_ID_FFA_* and ARM_SVC_ID_SP_* identifiers for 32bit function IDs as per SMCCC specification. Defines also generic ARM SVC identifier macros to wrap 32bit or 64bit identifiers upon target built architecture. Signed-off-by: Etienne Carriere Reviewed-by: Sami Mujawar --- Changes since v3: - Remove Cc tags and apply review tag. No changes since v2 Changes since v1: - Define ARM_SMC_ID_MM_COMMUNICATE 32b/64b agnostic helper ID in ArmStdSmc.h, as expected by few following commits in this series. --- ArmPkg/Include/IndustryStandard/ArmFfaSvc.h | 12 ++++++++++++ ArmPkg/Include/IndustryStandard/ArmMmSvc.h | 15 +++++++++++++++ ArmPkg/Include/IndustryStandard/ArmStdSmc.h | 8 ++++++++ 3 files changed, 35 insertions(+) diff --git a/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h b/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h index 65b8343ade..ebcb54b28b 100644 --- a/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h +++ b/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h @@ -17,9 +17,21 @@ #define ARM_FFA_SVC_H_ #define ARM_SVC_ID_FFA_VERSION_AARCH32 0x84000063 +#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 0x8400006F +#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 0x84000070 #define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 0xC400006F #define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC4000070 +/* Generic IDs when using AArch32 or AArch64 execution state */ +#ifdef MDE_CPU_AARCH64 +#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 +#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 +#endif +#ifdef MDE_CPU_ARM +#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 +#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 +#endif + #define SPM_MAJOR_VERSION_FFA 1 #define SPM_MINOR_VERSION_FFA 0 diff --git a/ArmPkg/Include/IndustryStandard/ArmMmSvc.h b/ArmPkg/Include/IndustryStandard/ArmMmSvc.h index 33d60ccf17..deb3bc99d2 100644 --- a/ArmPkg/Include/IndustryStandard/ArmMmSvc.h +++ b/ArmPkg/Include/IndustryStandard/ArmMmSvc.h @@ -15,10 +15,25 @@ * privileged operations on its behalf. */ #define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060 +#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 0x84000061 +#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 0x84000064 +#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 0x84000065 #define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061 #define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064 #define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065 +/* Generic IDs when using AArch32 or AArch64 execution state */ +#ifdef MDE_CPU_AARCH64 +#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 +#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 +#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 +#endif +#ifdef MDE_CPU_ARM +#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 +#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 +#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 +#endif + #define SET_MEM_ATTR_DATA_PERM_MASK 0x3 #define SET_MEM_ATTR_DATA_PERM_SHIFT 0 #define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0 diff --git a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h index 67afb0ea2d..9116a291da 100644 --- a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h +++ b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h @@ -49,6 +49,14 @@ #define ARM_SMC_ID_MM_COMMUNICATE_AARCH32 0x84000041 #define ARM_SMC_ID_MM_COMMUNICATE_AARCH64 0xC4000041 +/* Generic ID when using AArch32 or AArch64 execution state */ +#ifdef MDE_CPU_AARCH64 +#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH64 +#endif +#ifdef MDE_CPU_ARM +#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH32 +#endif + /* MM return error codes */ #define ARM_SMC_MM_RET_SUCCESS 0 #define ARM_SMC_MM_RET_NOT_SUPPORTED -1 -- 2.17.1