From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) by mx.groups.io with SMTP id smtpd.web10.24365.1628522401922346721 for ; Mon, 09 Aug 2021 08:20:02 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=YZ+ThFkP; spf=pass (domain: linaro.org, ip: 209.85.128.44, mailfrom: etienne.carriere@linaro.org) Received: by mail-wm1-f44.google.com with SMTP id h24-20020a1ccc180000b029022e0571d1a0so260360wmb.5 for ; Mon, 09 Aug 2021 08:20:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LdNxUhHWg7bfXH2vQEsnwiLPnOmKwa/8RXLkigzYp7E=; b=YZ+ThFkP7PG9d/slK1Au19BvHp/HzYFP2nTdM2eFrWhqOnYfxLblPS7xQRj2Aivaju H/WD9GkeR4bw8rW+x5itGTPM+g5NkuXuLNymGZYbSHBsdUE1ebyhbSKAwDVXduNWkEv0 2DEL+npDnVV+cVt1ZuX18XTyvm54wiRuzmGVnrEjw2+RWY0wVHXCpyBzqgPsjXgu7vCw mdxJpWcMatLLaS4Xer2Pp0JTO10KOHCtjQc/B/JJiB5yoP7f1ucPN4nFrXD4VQVouli8 nHGsruqrruIxRjtv1MbAlXUpB9SpR/USeuI9hl6gnlqsVEfAMLkD+Imjk8m8lw6bxgVE OENQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LdNxUhHWg7bfXH2vQEsnwiLPnOmKwa/8RXLkigzYp7E=; b=VvALzSvk7vHFLw3dlje1T1cXnD9OrcE6nsGrD80zJ+gzp/84xqYPta/rUq/eBP13U/ Rdq1S1YAeQIM6mDXRJcuzkRbE2UofDqLE6lUR5IecHL19qBuNKxrNVkVN0hEIKJf96ot MSfh6JL6xqMnmQ3ePrY0t1n9w1Gj73p5lz+irl8bwDBwmeEb4zxOeLU2VgqcpRwgW5M5 lbzDIfeihZcR6EL5jMX66ydYiG3TCytf7dnRNpnIB6KH5drcZfX/WCcA0OOwJkQAbWww QMz87hVDhg7Wk/w6kg8/8/1POX9pxRg6jE6FJTloau6DhZP+aZ85birhlQJwm31ataD0 NJ1g== X-Gm-Message-State: AOAM532ULZ9mGT/Z+oAcrBkDWO5vqPRhJG31NmlwkUYS8ht6fWA4qnPO upGr5QGEaGGYq2FUn56B8+H2I0jZYakL6w== X-Google-Smtp-Source: ABdhPJw7lwhScPZ842pOgRGvQRGeX/q7XC67qPqg9sBc4kMDQYBKiEb6VtTCP0DRtnsXyVNdPv/XEg== X-Received: by 2002:a1c:9dd5:: with SMTP id g204mr8651272wme.74.1628522400415; Mon, 09 Aug 2021 08:20:00 -0700 (PDT) Return-Path: Received: from lmecxl0524.lme.st.com ([2a04:cec0:1189:835c:f5e6:d24:9eea:1973]) by smtp.gmail.com with ESMTPSA id j14sm20449971wru.58.2021.08.09.08.19.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Aug 2021 08:20:00 -0700 (PDT) From: "Etienne Carriere" To: devel@edk2.groups.io Cc: Achin Gupta , Ard Biesheuvel , Jiewen Yao , Leif Lindholm , Sami Mujawar , Sughosh Ganu , Liming Gao , Etienne Carriere Subject: [PATCH v5 3/5] GenFv: Arm: support images entered in Thumb mode Date: Mon, 9 Aug 2021 17:19:44 +0200 Message-Id: <20210809151946.27600-3-etienne.carriere@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210809151946.27600-1-etienne.carriere@linaro.org> References: <20210809151946.27600-1-etienne.carriere@linaro.org> Change GenFv for Arm architecture to generate a specific jump instruction as image entry instruction, when the target entry label is assembled with Thumb instruction set. This is possible since SecCoreEntryAddress value fetched from the PE32 has its LSBit set when the entry instruction executes in Thumb mode. Signed-off-by: Etienne Carriere Acked-by: Liming Gao Reviewed-by: Sami Mujawar --- No change since v4 Changes since v3: - Removed Cc tags and apply review tags. Changes since v2: - Fix missing parentheses in expression. Changes since v1: - Fix typos in commit log and inline comments - Change if() test operand to be an explicit boolean --- BaseTools/Source/C/GenFv/GenFvInternalLib.c | 38 +++++++++++++++----- 1 file changed, 29 insertions(+), 9 deletions(-) diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source/C/GenFv/GenFvInternalLib.c index 6e296b8ad6..6cf9c84e73 100644 --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c @@ -34,9 +34,27 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "FvLib.h" #include "PeCoffLib.h" -#define ARMT_UNCONDITIONAL_JUMP_INSTRUCTION 0xEB000000 #define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION 0x14000000 +/* + * Arm instruction to jump to Fv entry instruction in Arm or Thumb mode. + * From ARM Arch Ref Manual versions b/c/d, section A8.8.25 BL, BLX (immediate) + * BLX (encoding A2) branches to offset in Thumb instruction set mode. + * BL (encoding A1) branches to offset in Arm instruction set mode. + */ +#define ARM_JUMP_OFFSET_MAX 0xffffff +#define ARM_JUMP_TO_ARM(Offset) (0xeb000000 | ((Offset - 8) >> 2)) + +#define _ARM_JUMP_TO_THUMB(Imm32) (0xfa000000 | \ + (((Imm32) & (1 << 1)) << (24 - 1)) | \ + (((Imm32) >> 2) & 0x7fffff)) +#define ARM_JUMP_TO_THUMB(Offset) _ARM_JUMP_TO_THUMB((Offset) - 8) + +/* + * Arm instruction to retrun from exception (MOVS PC, LR) + */ +#define ARM_RETURN_FROM_EXCEPTION 0xE1B0F07E + BOOLEAN mArm = FALSE; BOOLEAN mRiscV = FALSE; STATIC UINT32 MaxFfsAlignment = 0; @@ -2203,23 +2221,25 @@ Returns: // if we found an SEC core entry point then generate a branch instruction // to it and populate a debugger SWI entry as well if (UpdateVectorSec) { + UINT32 EntryOffset; VerboseMsg("UpdateArmResetVectorIfNeeded updating ARM SEC vector"); - // B SecEntryPoint - signed_immed_24 part +/-32MB offset - // on ARM, the PC is always 8 ahead, so we're not really jumping from the base address, but from base address + 8 - ResetVector[0] = (INT32)(SecCoreEntryAddress - FvInfo->BaseAddress - 8) >> 2; + EntryOffset = (INT32)(SecCoreEntryAddress - FvInfo->BaseAddress); - if (ResetVector[0] > 0x00FFFFFF) { - Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within 32MB of the start of the FV"); + if (EntryOffset > ARM_JUMP_OFFSET_MAX) { + Error(NULL, 0, 3000, "Invalid", "SEC Entry point offset above 1MB of the start of the FV"); return EFI_ABORTED; } - // Add opcode for an unconditional branch with no link. i.e.: " B SecEntryPoint" - ResetVector[0] |= ARMT_UNCONDITIONAL_JUMP_INSTRUCTION; + if ((SecCoreEntryAddress & 1) != 0) { + ResetVector[0] = ARM_JUMP_TO_THUMB(EntryOffset); + } else { + ResetVector[0] = ARM_JUMP_TO_ARM(EntryOffset); + } // SWI handler movs pc,lr. Just in case a debugger uses SWI - ResetVector[2] = 0xE1B0F07E; + ResetVector[2] = ARM_RETURN_FROM_EXCEPTION; // Place holder to support a common interrupt handler from ROM. // Currently not supported. For this to be used the reset vector would not be in this FV -- 2.17.1