From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.3538.1628566586124937640 for ; Mon, 09 Aug 2021 20:36:26 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: jeremy.linton@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C69BA113E; Mon, 9 Aug 2021 20:36:25 -0700 (PDT) Received: from u200856.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7C4EB3F70D; Mon, 9 Aug 2021 20:36:25 -0700 (PDT) From: "Jeremy Linton" To: devel@edk2.groups.io Cc: pete@akeo.ie, ardb+tianocore@kernel.org, awarkentin@vmware.com, Sunny.Wang@arm.com, samer.el-haj-mahmoud@arm.com, Jeremy Linton Subject: [PATCH v2 5/6] Silicon/Broadcom/Bcm27xx: Move linkup check into the cfg accessor Date: Mon, 9 Aug 2021 22:36:17 -0500 Message-Id: <20210810033618.5139-6-jeremy.linton@arm.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210810033618.5139-1-jeremy.linton@arm.com> References: <20210810033618.5139-1-jeremy.linton@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable The existing code fails to create/finish configuring the pcie subsystem if it fails to get a linkup. This is reasonable on the RPi4 because it generally won't happen, and the OS could not see the root port. Now that the OS can see the root port, its a bit odd if it only shows up when something is plugged into the first slot. Lets move the link up check into the config accessor where it will be used to restrict sending CFG TLP's out the port when nothing is plugged in. Thus avoiding a SERROR during probe. Signed-off-by: Jeremy Linton --- .../Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c | 5 -= ---- .../Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 7 += ++++++ 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm= 2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2= 711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c index 8587d2d36d..4d4c584726 100644 --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711Pci= HostBridgeLibConstructor.c +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711Pci= HostBridgeLibConstructor.c @@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor ( } while (((Data & 0x30) !=3D 0x030) && (Timeout)); DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=3D%x) Timeout=3D%d\n",= Data, Timeout)); =20 - if ((Data & 0x30) !=3D 0x30) { - DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=3D%x)\n", Data)); - return EFI_DEVICE_ERROR; - } - if ((Data & 0x80) !=3D 0x80) { DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=3D%x)\n", Dat= a)); return EFI_UNSUPPORTED; diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSeg= mentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegm= entLib.c index 6d15e82fa2..b627e5730b 100644 --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib= .c +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib= .c @@ -105,6 +105,13 @@ PciSegmentLibGetConfigBase ( return 0xFFFFFFFF; } =20 + /* Don't probe slots if the link is down */ + Data =3D MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS); + if ((Data & 0x30) !=3D 0x30) { + DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=3D%x)\n", Da= ta)); + return 0xFFFFFFFF; + } + MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); mPciSegmentLastAccess =3D Address; } --=20 2.13.7