From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web08.3952.1628570223230878935 for ; Mon, 09 Aug 2021 21:37:03 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: nathaniel.l.desimone@intel.com) X-IronPort-AV: E=McAfee;i="6200,9189,10070"; a="214562944" X-IronPort-AV: E=Sophos;i="5.84,309,1620716400"; d="scan'208";a="214562944" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2021 21:37:02 -0700 X-IronPort-AV: E=Sophos;i="5.84,309,1620716400"; d="scan'208";a="421704789" Received: from nldesimo-desk1.amr.corp.intel.com ([10.209.34.61]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2021 21:37:02 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Michael Kubacki , Benjamin Doron Subject: [edk2-platforms] [PATCH V1] KabylakeSiliconPkg: Update SA_MISC_PEI_PREMEM_CONFIG Date: Mon, 9 Aug 2021 21:36:54 -0700 Message-Id: <20210810043654.26833-1-nathaniel.l.desimone@intel.com> X-Mailer: git-send-email 2.27.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Updates SA_MISC_PEI_PREMEM_CONFIG from revision 1 to revision 3. Add initialization of the policy values. Cc: Chasel Chiu Cc: Michael Kubacki Cc: Benjamin Doron Signed-off-by: Nate DeSimone --- .../KabylakeRvp3/OpenBoardPkg.dsc | 24 +++--- .../PeiSiliconPolicyUpdateLib.c | 39 +++++++++- .../PeiSiliconPolicyUpdateLib.inf | 9 ++- .../ConfigBlock/SaMiscPeiPreMemConfig.h | 77 ++++++++++++++++++- .../Library/PeiSaPolicyLib/PeiSaPolicyLib.c | 37 ++++++++- 5 files changed, 169 insertions(+), 17 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 8523ab3f4f..f64555e391 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -182,17 +182,6 @@ # Board-specific ####################################### PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookLib.inf -!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 - # - # FSP API mode - # - SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf -!else - # - # FSP Dispatch mode and non-FSP build (EDK2 build) - # - SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf -!endif [LibraryClasses.IA32.SEC] ####################################### @@ -200,6 +189,7 @@ ####################################### TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SecTestPointCheckLib.inf SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf + SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf [LibraryClasses.common.PEIM] ####################################### @@ -222,6 +212,18 @@ ####################################### # Board Package ####################################### +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 + # + # FSP API mode + # + SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf +!else + # + # FSP Dispatch mode and non-FSP build (EDK2 build) + # + SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf +!endif + # Thunderbolt !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.inf diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c index 5cc7c03c61..2dce9be63c 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c @@ -1,7 +1,7 @@ /** @file Provides silicon policy update library functions. -Copyright (c) 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -398,6 +398,8 @@ SiliconPolicyUpdatePreMem ( SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; MEMORY_CONFIG_NO_CRC *MemConfigNoCrc; VOID *Buffer; + UINTN VariableSize; + VOID *MemorySavedData; UINT8 SpdAddressTable[4]; DEBUG((DEBUG_INFO, "\nUpdating Policy in Pre-Mem\n")); @@ -417,6 +419,41 @@ SiliconPolicyUpdatePreMem ( // Pass board specific SpdAddressTable to policy // CopyMem ((VOID *) MiscPeiPreMemConfig->SpdAddressTable, (VOID *) SpdAddressTable, (sizeof (UINT8) * 4)); + + // + // Set size of SMRAM + // + MiscPeiPreMemConfig->TsegSize = PcdGet32 (PcdTsegSize); + + // + // Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths. + // Note: AmberLake FSP does not implement the FSPM_ARCH_CONFIG_PPI added in FSP 2.1, hence + // the platform specific S3DataPtr must be used instead. + // + VariableSize = 0; + MemorySavedData = NULL; + Status = PeiGetVariable ( + L"MemoryConfig", + &gFspNonVolatileStorageHobGuid, + &MemorySavedData, + &VariableSize + ); + DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHobGuid - %r\n", Status)); + DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize)); + if (!EFI_ERROR (Status)) { + MiscPeiPreMemConfig->S3DataPtr = MemorySavedData; + } + + // + // In FSP Dispatch Mode these BAR values are initialized by SiliconPolicyInitPreMem() in + // KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c; this function calls + // PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI->PeiPreMemPolicyInit() to initialize all Config Blocks + // with default policy values (including these BAR values.) PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI + // is implemented in the FSP. Make sure the value that FSP is using matches the value we are using. + // + ASSERT (PcdGet64 (PcdMchBaseAddress) <= 0xFFFFFFFF); + ASSERT (MiscPeiPreMemConfig->MchBar == (UINT32) PcdGet64 (PcdMchBaseAddress)); + ASSERT (MiscPeiPreMemConfig->SmbusBar == PcdGet16 (PcdSmbusBaseAddress)); } MemConfigNoCrc = NULL; Status = GetConfigBlock (Policy, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc); diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf index 97ec70f611..5c2da68bf9 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -1,7 +1,7 @@ ### @file # Component information file for silicon policy update library # -# Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
+# Copyright (c) 2019 - 2021 Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -11,7 +11,7 @@ INF_VERSION = 0x00010005 BASE_NAME = PeiSiliconPolicyUpdateLib FILE_GUID = 14F5D83D-76A5-4241-BEC5-987E70E233D5 - MODULE_TYPE = BASE + MODULE_TYPE = PEIM VERSION_STRING = 1.0 LIBRARY_CLASS = SiliconPolicyUpdateLib @@ -33,6 +33,7 @@ [Packages] MinPlatformPkg/MinPlatformPkg.dec MdePkg/MdePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec UefiCpuPkg/UefiCpuPkg.dec KabylakeSiliconPkg/SiPkg.dec KabylakeOpenBoardPkg/OpenBoardPkg.dec @@ -49,11 +50,15 @@ gHsioPciePreMemConfigGuid ## CONSUMES gHsioSataPreMemConfigGuid ## CONSUMES gSaMiscPeiPreMemConfigGuid ## CONSUMES + gFspNonVolatileStorageHobGuid ## CONSUMES [Pcd] gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize + gSiPkgTokenSpaceGuid.PcdMchBaseAddress + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress + gSiPkgTokenSpaceGuid.PcdTsegSize gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPeiPreMemConfig.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPeiPreMemConfig.h index 4aa02e3142..2ed587f425 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPeiPreMemConfig.h +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPeiPreMemConfig.h @@ -1,7 +1,7 @@ /** @file Policy details for miscellaneous configuration in System Agent -Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -14,18 +14,91 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define SA_MC_MAX_SOCKETS 4 #endif -#define SA_MISC_PEI_PREMEM_CONFIG_REVISION 1 +#define SA_MISC_PEI_PREMEM_CONFIG_REVISION 3 /** This configuration block is to configure SA Miscellaneous variables during PEI Pre-Mem phase like programming different System Agent BARs, TsegSize, IedSize, MmioSize required etc. Revision 1: - Initial version. + Revision 2: + - Added SgDelayAfterOffMethod, SgDelayAfterLinkEnable and SgGenSpeedChangeEnable. + Revision 3: + - Added BdatTestType and BdatSchema. **/ typedef struct { CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header UINT8 SpdAddressTable[SA_MC_MAX_SOCKETS];///< Offset 28 Memory DIMMs' SPD address for reading SPD data. example: SpdAddressTable[0]=0xA2(C0D0), SpdAddressTable[1]=0xA0(C0D1), SpdAddressTable[2]=0xA2(C1D0), SpdAddressTable[3]=0xA0(C1D1) + VOID *S3DataPtr; ///< Offset 32 Memory data save pointer for S3 resume. The memory space should be allocated and filled with proper S3 resume data on a resume path UINT32 MchBar; ///< Offset 36 Address of System Agent MCHBAR: 0xFED10000 + UINT32 DmiBar; ///< Offset 40 Address of System Agent DMIBAR: 0xFED18000 + UINT32 EpBar; ///< Offset 44 Address of System Agent EPBAR: 0xFED19000 + UINT32 SmbusBar; ///< Offset 48 Address of System Agent SMBUS BAR: 0xEFA0 + UINT32 GdxcBar; ///< Offset 52 Address of System Agent GDXCBAR: 0xFED84000 + /** + Offset 56 Size of TSEG in bytes. (Must be power of 2) + 0x400000: 4MB for Release build (When IED enabled, it will be 8MB) + 0x1000000 : 16MB for Debug build (Regardless IED enabled or disabled) + **/ + UINT32 TsegSize; + UINT32 EdramBar; ///< Offset 60 Address of System Agent EDRAMBAR: 0xFED80000 + /** + Offset 64 + (Test) Size of IED region in bytes. + 0 : IED Disabled (no memory occupied) + 0x400000 : 4MB SMM memory occupied by IED (Part of TSEG) + Note: Enabling IED may also enlarge TsegSize together. + **/ + UINT32 IedSize; + UINT8 UserBd; ///< Offset 68 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server + UINT8 SgMode; ///< Offset 69 SgMode: 0=Disabled, 1=SG Muxed, 2=SG Muxless, 3=PEG + UINT16 SgSubSystemId; ///< Offset 70 Switchable Graphics Subsystem ID: 2212 + UINT16 SgDelayAfterPwrEn; ///< Offset 72 Dgpu Delay after Power enable using Setup option: 0=Minimal, 1000=Maximum, 300=300 microseconds + UINT16 SgDelayAfterHoldReset; ///< Offset 74 Dgpu Delay after Hold Reset using Setup option: 0=Minimal, 1000=Maximum, 100=100 microseconds + UINT32 SkipExtGfxScan:1; ///< (Test) OFfset 76:0 :1=Skip External Gfx Device Scan; 0=Scan for external graphics devices. Set this policy to skip External Graphics card scanning if the platform uses Internal Graphics only. + UINT32 BdatEnable:1; ///< (Test) OFfset 76:1 :This field enables the generation of the BIOS DATA ACPI Tables: 0=FALSE, 1=TRUE\n Please refer to the MRC documentation for more details + UINT32 TxtImplemented:1; ///< OFfset 76:2 :This field currently is used to tell MRC if it should run after TXT initializatoin completed: 0=Run without waiting for TXT, 1=Run after TXT initialization by callback + /** + Offset 76:3 : + (Test) Scan External Discrete Graphics Devices for Legacy Only VGA OpROMs + + When enabled, if the primary graphics device is an external discrete graphics device, Si will scan the + graphics device for legacy only VGA OpROMs. If the primary graphics device only implements legacy VBIOS, then the + LegacyOnlyVgaOpRomDetected field in the SA_DATA_HOB will be set to 1. + + This is intended to ease the implementation of a BIOS feature to automatically enable CSM if the Primary Gfx device + only supports Legacy VBIOS (No UEFI GOP Present). Otherwise disabling CSM won't result in no video being displayed. + This is useful for platforms that implement PCIe slots that allow the end user to install an arbitrary Gfx device. + + This setting will only take effect if SkipExtGfxScan == 0. It is ignored otherwise. + + - Disabled (0x0) : Don't Scan for Legacy Only VGA OpROMs (Default) + - Enabled (0x1) : Scan External Gfx for Legacy Only VGA OpROM + **/ + UINT32 ScanExtGfxForLegacyOpRom:1; + UINT32 RsvdBits0 :28; ///< OFfset 76:4 :Reserved for future use + UINT8 LockPTMregs; ///< (Test) Offset 80 Lock PCU Thermal Management registers: 0=FALSE, 1=TRUE + UINT8 BdatTestType; ///< Offset 81 When BdatEnable is set to TRUE, this option selects the type of data which will be populated in the BIOS Data ACPI Tables: 0=RMT, 1=RMT Per Bit, 2=Margin 2D. + UINT8 BdatSchema; ///< Offset 82 When BdatEnable is set to TRUE, this option selects the BDAT Schema version which will be used to format BDAT Test results: 0=Schema 2, 1=Schema 6B + UINT8 Rsvd1; ///< Offset 83 Reserved for future use + /** + Offset 84 : + Size of reserved MMIO space for PCI devices\n + 0=AUTO, 512=512MB, 768=768MB, 1024=1024MB, 1280=1280MB, 1536=1536MB, 1792=1792MB, + 2048=2048MB, 2304=2304MB, 2560=2560MB, 2816=2816MB, 3072=3072MB\n + When AUTO mode selected, the MMIO size will be calculated by required MMIO size from PCIe devices detected. + **/ + UINT16 MmioSize; + INT16 MmioSizeAdjustment; ///< Offset 86 Increase (given positive value) or Decrease (given negative value) the Reserved MMIO size when Dynamic Tolud/AUTO mode enabled (in MBs): 0=no adjustment + UINT64 AcpiReservedMemoryBase; ///< Offset 88 The Base address of a Reserved memory buffer allocated in previous boot for S3 resume used. Originally it is retrieved from AcpiVariableCompatibility variable. + UINT64 SystemMemoryLength; ///< Offset 96 Total system memory length from previous boot, this is required for S3 resume. Originally it is retrieved from AcpiVariableCompatibility variable. + UINT32 AcpiReservedMemorySize; ///< Offset 104 The Size of a Reserved memory buffer allocated in previous boot for S3 resume used. Originally it is retrieved from AcpiVariableCompatibility variable. + UINT32 OpRomScanTempMmioBar; ///< (Test) Offset 108 Temporary address to MMIO map OpROMs during VGA scanning. Used for ScanExtGfxForLegacyOpRom feature. MUST BE 16MB ALIGNED! + UINT32 OpRomScanTempMmioLimit; ///< (Test) Offset 112 Limit address for OpROM MMIO range. Used for ScanExtGfxForLegacyOpRom feature. (OpROMScanTempMmioLimit - OpRomScanTempMmioBar) MUST BE >= 16MB! + UINT16 SgDelayAfterOffMethod; ///< Offset 128 Dgpu Delay after off method is called using Setup option: 0=Minimal, 1000=Maximum, 300=300 microseconds + UINT16 SgDelayAfterLinkEnable; ///< Offset 130 Delay after link enable method is called using Setup option: 0=Minimal, 1000=Maximum, 100=100 microseconds + UINT8 SgGenSpeedChangeEnable; ///< Offset 132 Enable/Disable Gen speed changes using Setup option: 0=Disable, 1=Enable + UINT8 Rsvd3[3]; ///< Offset 133 Reserved for future use } SA_MISC_PEI_PREMEM_CONFIG; #pragma pack(pop) diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.c index eb18d993e7..5210856346 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.c @@ -1,7 +1,7 @@ /** @file This file provides services for PEI policy default initialization -Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -19,6 +19,9 @@ extern EFI_GUID gMemoryConfigNoCrcGuid; extern EFI_GUID gGraphicsPeiConfigGuid; extern EFI_GUID gVtdConfigGuid; +#define DEFAULT_OPTION_ROM_TEMP_BAR 0x80000000 +#define DEFAULT_OPTION_ROM_TEMP_MEM_LIMIT 0xC0000000 + // // Function call to Load defaults for Individial IP Blocks // @@ -33,6 +36,38 @@ LoadSaMiscPeiPreMemDefault ( DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->Header.GuidHob.Name = %g\n", &MiscPeiPreMemConfig->Header.GuidHob.Name)); DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->Header.GuidHob.Header.HobLength = 0x%x\n", MiscPeiPreMemConfig->Header.GuidHob.Header.HobLength)); + + // + // Policy initialization commented out here is because it's the same with default 0 and no need to re-do again. + // + MiscPeiPreMemConfig->LockPTMregs = 1; + + // + // Initialize the Platform Configuration + // + MiscPeiPreMemConfig->MchBar = (UINT32) PcdGet64 (PcdMchBaseAddress); + MiscPeiPreMemConfig->DmiBar = 0xFED18000; + MiscPeiPreMemConfig->EpBar = 0xFED19000; + MiscPeiPreMemConfig->EdramBar = 0xFED80000; + MiscPeiPreMemConfig->SmbusBar = PcdGet16 (PcdSmbusBaseAddress); + MiscPeiPreMemConfig->TsegSize = PcdGet32 (PcdTsegSize); + MiscPeiPreMemConfig->GdxcBar = 0xFED84000; + + // + // Initialize the Switchable Graphics Default Configuration + // + MiscPeiPreMemConfig->SgDelayAfterHoldReset = 100; //100ms + MiscPeiPreMemConfig->SgDelayAfterPwrEn = 300; //300ms + MiscPeiPreMemConfig->SgDelayAfterOffMethod = 0; + MiscPeiPreMemConfig->SgDelayAfterLinkEnable = 0; + MiscPeiPreMemConfig->SgGenSpeedChangeEnable = 0; + + /// + /// Initialize the DataPtr for S3 resume + /// + MiscPeiPreMemConfig->S3DataPtr = NULL; + MiscPeiPreMemConfig->OpRomScanTempMmioBar = DEFAULT_OPTION_ROM_TEMP_BAR; + MiscPeiPreMemConfig->OpRomScanTempMmioLimit = DEFAULT_OPTION_ROM_TEMP_MEM_LIMIT; } VOID -- 2.27.0.windows.1