From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) by mx.groups.io with SMTP id smtpd.web11.66.1628613652227254785 for ; Tue, 10 Aug 2021 09:40:52 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=VYDJ8TE2; spf=pass (domain: linaro.org, ip: 209.85.221.48, mailfrom: etienne.carriere@linaro.org) Received: by mail-wr1-f48.google.com with SMTP id q10so3886449wro.2 for ; Tue, 10 Aug 2021 09:40:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BvksbF9VBANAN8l+yO5D4ZdlG0TIaZ6BfCyfYSAXr1o=; b=VYDJ8TE2XlrtJb+73d8zlHAPgBDOcErYn22OaNLCa9Wrz4cWp9Qdop2h3y4uV8r+r6 IKm6gRcMb/2gjQj/rWqczsH01ZDwPzUE3phKC3U3Bk2p493ZG9/0nbVPKOsi96d0UXsQ s2G35Lk/5y14h9bgcdHBGESooSNx13q6iQEhyQoF0X55wo1DZf/+nA72Airl2KG55jib ekvDKQtBC9FvGkRSaMeGfnpKSUpqGIxxDtQcUOCLgaDd2ghcgLtB6zjUEzIBFk0HpyRt 26nXIUOuB/kboepP5en+uvVecij4PRipnAZ6DgI3vk5MmnG2SbeI1K9LX3UmUCAxyWWU 6XbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BvksbF9VBANAN8l+yO5D4ZdlG0TIaZ6BfCyfYSAXr1o=; b=T/e0qxnnO50ew49YGxtDyvfMn3fbsNf1U+cLTNcytASadeHoncNK4ovjn/Okiw74Qx iVho6HkNfcpB15Tp3baEUSQy8qbxcdZQsomCnYkov/Pp8uh17n4Ov/+0JMioiZSBVxXe q9hPUyWm5ntRTvQL0sf/RJyW4UtF7XNZ1HKHaxI/ar7FYfuSrBBWATUzhuJwUeQ0BwsG 6Gs58OceP9nNxvYc7J3yyg47Vzcvwf3sDmMG1INuaaPFJWZ2tlBzuH0jHbRSKJTy4AOG bIBXGx4FjUo6ak16aUs5edLoelmEBVEtmL5DKErfmtYYaMxaANzd7hxmVTq8OTYl7NYO 5EJA== X-Gm-Message-State: AOAM5321y1MpS75BQZ9q6qd4T4O07fPjn5EtvfehNXFzRqQOmo8WQS0h fyRu6fq9pyo80yJ1y+XSc7lXbfofaYkksg== X-Google-Smtp-Source: ABdhPJxgXs793al2YtaeQhvGeaz4Qz2HPj/lpCrwEkToVjqUa9kd5f21/2TGEhnBh77Ap0hx7BHDEA== X-Received: by 2002:a5d:58ce:: with SMTP id o14mr13233285wrf.319.1628613650768; Tue, 10 Aug 2021 09:40:50 -0700 (PDT) Return-Path: Received: from lmecxl0524.lme.st.com ([2a04:cec0:10c1:ef71:f5e6:d24:9eea:1973]) by smtp.gmail.com with ESMTPSA id i3sm3196261wmb.17.2021.08.10.09.40.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Aug 2021 09:40:50 -0700 (PDT) From: "Etienne Carriere" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Ilias Apalodimas , Leif Lindholm , Sami Mujawar , Sughosh Ganu , Thomas Abraham , Etienne Carriere Subject: [PATCH v3 4/6] Drivers/OpTee: Add Aarch32 SVC IDs for 32bit Arm targets Date: Tue, 10 Aug 2021 18:40:34 +0200 Message-Id: <20210810164036.15199-5-etienne.carriere@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210810164036.15199-1-etienne.carriere@linaro.org> References: <20210810164036.15199-1-etienne.carriere@linaro.org> Add SMCCC function IDs for RPMB read/write service on 32bit architectures. Define generic SP_SVC_RPMB_READ/SP_SVC_RPMB_WRITE IDs for native target architecture (32b or 64b). Changes OpTeeRpmbFvb.c to use architecture agnostic macro ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ for 32b and 64b support. Cc: Ard Biesheuvel Cc: Ilias Apalodimas Cc: Leif Lindholm Cc: Sami Mujawar Signed-off-by: Etienne Carriere --- No change since v2 Changes since v1: - Use _AARCH64 (resp. _AARCH32) suffix instead of _64 (resp. _32) in the added macros. --- Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.c | 2 +- Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.h | 16 ++++++++++++++-- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.c b/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.c index 5197c95abd..6eb19bed0e 100644 --- a/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.c +++ b/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.c @@ -68,7 +68,7 @@ ReadWriteRpmb ( ZeroMem (&SvcArgs, sizeof (SvcArgs)); - SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64; + SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ; SvcArgs.Arg1 = mStorageId; SvcArgs.Arg2 = 0; SvcArgs.Arg3 = SvcAct; diff --git a/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.h b/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.h index c17fc287ef..9c2a4ea6a5 100644 --- a/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.h +++ b/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.h @@ -13,8 +13,20 @@ contract between OP-TEE and EDK2. For more details check core/arch/arm/include/kernel/stmm_sp.h in OP-TEE **/ -#define SP_SVC_RPMB_READ 0xC4000066 -#define SP_SVC_RPMB_WRITE 0xC4000067 +#define SP_SVC_RPMB_READ_AARCH64 0xC4000066 +#define SP_SVC_RPMB_WRITE_AARCH64 0xC4000067 + +#define SP_SVC_RPMB_READ_AARCH32 0x84000066 +#define SP_SVC_RPMB_WRITE_AARCH32 0x84000067 + +#ifdef MDE_CPU_AARCH64 +#define SP_SVC_RPMB_READ SP_SVC_RPMB_READ_AARCH64 +#define SP_SVC_RPMB_WRITE SP_SVC_RPMB_WRITE_AARCH64 +#endif +#ifdef MDE_CPU_ARM +#define SP_SVC_RPMB_READ SP_SVC_RPMB_READ_AARCH32 +#define SP_SVC_RPMB_WRITE SP_SVC_RPMB_WRITE_AARCH32 +#endif #define FLASH_SIGNATURE SIGNATURE_32 ('r', 'p', 'm', 'b') #define INSTANCE_FROM_FVB_THIS(a) CR (a, MEM_INSTANCE, FvbProtocol, \ -- 2.17.1